DESIGN-FOR-TEST
Facilitating at-speed test
at RTL (Part 2)
By Dr. Ralph Marlett
Product Director
Atrenta Inc.
and
Kiran Vittal
Product Marketing Director
Atrenta Inc.
Part 1 of this series discusses the
problems with at-speed testing,
and the various defect models and
manufacturing test techniques.
This part will tackle at-speed tim-
ing closure rules and at-speed
coverage. It also looks into the
at-speed coverage estimation and
diagnosis of SpyGlass-DFT DSM.
The SpyGlass-DFT DSM
product provides timing closure
analysis and RTL testability for
Figure 1: Complete RTL analysis solution for stuck-at and at-speed testing.
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deep sub-micron (DSM) defects
associated with at-speed testing.
It is touted to provide accurate RTL
fault coverage estimation for tran-
sition delay testing, together with
diagnostics for low fault coverage,
early in the design flow. Figure 2: PLL clock source rule.
The overall flow for Atrenta’s
complete RTL testability solution
is shown in figure 1.
Timing closure rules
Here are some examples of at-
speed rules. These rules identify
issues caused by clocks used in
at-speed tests for timing closure Figure 3: PLL reset rule.
as well as low coverage.
PLL clock rule. This rule veri-
fies that the PLL reference clock
can be controlled from root level
ports. Compliance with this rule
is required to simplify PLL control
Figure 4: PLL clock connection rule.
Figure 5: Asynchronous clocks rule.
Figure 6: Synchronous clocks rule.
during at-speed test mode. The
example shown in figure 2 would
be flagged as a violation.
PLL resest rule. This rule verifies
that the PLL control inputs can
be controlled from root level
ports. Compliance with this rule
is required to simplify PLL control
during at-speed test mode. The
example shown in figure 3 for
a PLL reset would be flagged as a
violation.
PLL connection rule. All flip-
flops must be PLL controlled in
at-speed test mode. The flip-flop
illustrated in figure 4 would be
flagged as a violation. Compliance
with this rule maximises the at-
speed coverage.
Asynchronous logic in the
functional mode should not in-
teract synchronously in the test
mode. In the example in figure
5, any paths that cross the clock
domains Clk1 and Clk2 will be
treated as if they were legitimate
at-speed candidates when, if fact,
they are asynchronous in system
mode. Configuring this logic with
a single test clock could result in
decreased yield.
Synchronous logic in the func-
tional mode should not interact
asynchronously in the test mode.
If this rule is not followed then
some at-speed faults will be con-
sidered as untestable which can
result in passing chips that will not
operate properly at system speed.
In figure 6, all paths between
Logic1 and Logic2 would not be
tested.
Required frequencies must be
achieved. Constraints for PLL logic
provide for specifying frequencies
and frequency multipliers. In the
example in figure 7, if the user has
specified the required frequencies
Figure 7: Required frequencies for at-speed test must be achieved.
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Figure 8: Clock domain crossing – Red path indicates invalid faults.
Figure 9: Mixed domains – Green path indicates valid faults.
at internal nodes, then this rule
will verify that it can be achieved.
At-speed vs stuck-at
At speed fault selection. The strict
clocking requirement for at-speed
testing implies that the launching
clock and the capturing clock be
synchronous. Transition faults on
the path illustrated in red in fig-
ure 8 are launched by Clk1 but
captured on Clk2. If Clk1 and Clk2
are not synchronous then the rela-
tive timing between them cannot
be guaranteed. The conclusion is
that the candidates for at speed
tests must be in the same clock
domain. Skew management
within a domain ensures that two
clock tests can be reliably per-
formed within the domain.
Notice that transition faults
along the path marked in green
in figure 9 are launched and
captured on the same clock and
therefore are at-speed testable.
Stuck-at coverage depends
on the amount of scan in the
design. Ignoring such factors as
latch transparency or black boxes,
if all flip-flops are scannable,
then nearly 100% test coverage
is a reasonable expectation since
tests for stuck-at faults requires
that the fault be controlled and
observed. As scan is added to a
circuit, the fraction of logic that
can be controlled and observed
increases and therefore test cover-
age for stuck-at faults increases.
SpyGlass-DFT treats the Q-pins
of scannable flip-flops as control-
lable and D-pins as observable so,
as the scan-ability increases, the
estimated test coverage increases.
In launch by first capture at-
speed tests, not only must control
and observe of the transition pin
be satisfied (similar to stuck-at
testing) but a third condition is
also necessary to have control on
the D-pin of the scan flop. Scan-
ability of the logic combination-
ally connected to the transition
pin provides the necessary control
and observe so that the first two
conditions are satisfied.
The next state of the launch
flip-flop must be controlled to the
complement of the scan-in state.
A rising edge event requires the
scan-in of 0 and a next state on
the D-pin of the launch flip-flop
to be a 1. A falling edge event re-
quires the scan-in of 1 and a next
state on the D-pin of the launch
flip-flop to be a 0.
If some flip-flops in the D-pin
fan-in cone of a launch flip-flop
are not scannable, then the next
state function of that flip-flop
may not be controllable. Such un-
controllable next state functions
prevent flip-flops from launching
dynamic events. The result is
that coverage of at-speed tests,
using the launch on first capture
method, is generally less than the
stuck-at coverage. A fundamental
reason is that the output control-
lability of scan flip-flops becomes
dependent on the system mode
controllability of their D-pins.
ASIC vendors have reported
that even when the stuck-at
coverage is in the high 90’s, it is
often the case that the at-speed
coverage is much less. Vendors
also report that none of their
current software tools give any
clue as to how to fix the problem
or are even able to predict this
coverage drop at the RTL stage.
Test engineers must run at-speed
ATPG to determine coverage.
Effort to fix low coverage during
ATPG affects design schedules,
or designers compromise on test
quality if it is too late to make de-
sign changes.

Calculation overview
Launch events. Any scannable flip-
flop, whose D-pin has incomplete
controllability in system mode,
will jeopardise at-speed coverage
for logic fed by this flip-flop. For
example, if the D-pin cannot be
controlled to either 0 or 1 then no
dynamic events can be launched
from this flip-flop. If the D-pin can
be controlled to 0 but not 1, then
1 => 0 events can be launched
but not 0 => 1 events. Finally, if
the D-pin can be controlled to 1
but not 0 then only 0 => 1 event
can be launched.
Clock domains. At-speed tests
require the launch clock and the
capture clock to be the same Figure 10: SpyGlass-DFT DSM Info_transitionCoverage rule and diagnostics/
clock. This means that only paths
that begin and end on flip-flops
on the same test clock are candi-
dates for at-speed testing. If this
is not the case, clock timing is
not guaranteed and therefore at-
speed testing would not produce
reliable results.
False paths and multi-cycle
paths. Faults on false paths can be
excluded from the test coverage
calculation but will be included in
the fault coverage.
Faults on multi-cycle paths will
be included in test coverage if the
number of registers on a multi-
cycle path is less than or is equal
to the number of capture clocks. Figure 11: D-pin uncontrollable in at-speed mode.
Otherwise, such faults will not be
included in test coverage.
Diagnostics. As described in
the previous section, an impor-
tant reason for low of at-speed
coverage is uncontrollability for
the next state functions. The test-
ability analysis of SpyGlass-DFT
DSM determines which flip-flops
have uncontrollable D-pins. The
fan-in cones for these D-pins
are then analysed to identify the
cause of uncontrollability such
as non-scanned flip-flop, black
box, non-transparent latch or
X-generator. Figure 10 shows
a sample testability report from
SpyGlass-DFT DSM. Figure 12: Blocked at-speed faults.

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Causes of low at-speed
coverage
Uncontrollability. As discussed
earlier, incomplete controllability
for next state functions in system
mode is a cause for decreased
at-speed coverage. Such cases
prevent launch events and thereby
prevent generation of specific tests
even though such transitions may
be possible in normal functions.
This uncontrollability may be
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caused by flip-flops that are not
scanned, by black boxes that are
not scanned wrapped or other
types of X-generators.
The flip-flop coloured in red in
figure 11 is not controllable be-
cause of the X-source in its fan-in
cone.
Blocked paths. Test mode sig-
nals may block functional paths
so that faults along these paths
cannot be at-speed tested. An ex-
ample of this is shown in figure 12.
Summary
This series discusses at-speed
testing challenges and discusses
a solution for facilitating at-speed
test at the register-transfer level.
The RTL approach is important
because designers and test engi-
neers usually verify the test cover-
age only at the gate level during
the final ATPG stage. This RTL solu-
tion thus saves weeks of effort by
fixing potential issues up-front.
The SpyGlass-DFT DSM a tool
that is touted to accelerate design
turnaround times by identifying
timing closure issues caused by
at-speed testing – early at RTL. It
provides RTL fault coverage esti-
mation for transition delay testing,
together with diagnostics for low
fault coverage early in the design
flow.