UNIT – 2

PART-1

BASIC COMPUTER
ORGANIZATION AND DESIGN
(How Basic Computer Operations Can Be Specified With Register Transfer Statements)

BY
K.SATYASREE
ASSISTANT PROFESSOR
ECE DEPARTMENT
VARDHAMAN COLLEGE OF ENGINEERING
 CONTENTS
 Instruction Codes

 Computer Registers

 Computer Instructions

 Timing And Control

 Instruction Cycle

 Register – Reference Instructions

 Memory – Reference Instructions

 Input – Output And Interrupt

2
 Instruction Codes
 Internal organization of a computer is defined by the sequence of micro-
operations it performs on data stored in its registers.

 Computer can be instructed about the specific sequence of operations it must

perform.
 User controls this process by means of a Program.

 Program: set of instructions that specify the operations, operands, and the
sequence by which processing has to occur.

 Instruction: a binary code that specifies a sequence of micro-operations for the

computer.

 The computer reads each instruction from memory and places it in a control
register. The control then interprets the binary code of the instruction and
proceeds to execute it by issuing a sequence of micro-operations. – Instruction
Cycle
 Instruction Code: group of bits that instruct the computer to perform a
specific operations.
Instruction code is usually divided into two parts: opcode and
address(operand)

Instruction format =

 Operation Code (opcode):

 group of bits that define the operation
 Eg: add, subtract, multiply, shift, complement.
 No. of bits required for opcode depends on no. of operations available in
computer.
 n bit opcode => 2n (or less) operations

 Address (operand):
 specifies the location of operands (registers or memory words)
 Memory words are specified by their address
 Registers are specified by their k-bit binary code
 k-bit address => 2k registers
 Stored Program Concept:
 Storage of instructions in a computer memory to enable it to perform a
variety of tasks in sequence.
 Introduced by Von Neumann
 proposed that a program be electronically stored in binary-number format
in a memory device so that instructions could be modified by the computer
as determined by intermediate computational results.

 Types of Architectures:

 Princeton / Von Neumann Architecture

 data and programs in single memory
 same address space for both programs and memory
 required two cycle to execute instruction

 Harvard Architecture
 separate program and data memory
 Separate address space for both programs and memory
 Required only one instruction cycle
 Stored Program Organization:
 simplest way to organize a computer

 one processor register: Accumulator (AC)

 operation is performed with memory operand and contents of AC

 Store each instruction code(program) and operand (data) in 16-bit memory word

 instruction code format with two separate parts

 opcode:
4-bits of 16-bit memory word
=> 24=16possible operations
 address:
12-bits of 16-bit memory word
=>212 = 4096 possible addresses
=> Memory size = 4096 words
 Addressing Mode:
 way in which address of operand is specified in the instruction

 Immediate Addressing Mode:

 second part of instruction contains the operand (data)
 Eg: MVI A, 20H ----------8085 Micro-processor
MOV AX, 2000H---- 8086 Micro-processor

 Direct Addressing Mode:

 second part of instruction contains address of operand.
 Eg: LDA 2000H -----------8085 Micro-processor
MOV AL, [2000H] --- 8086 Micro-processor

 Indirect addressing Mode:

 bits in the second part of the instruction designate an address of a memory
word in which address of operand is found.
 Eg: MOV M, A (M=> HL pair contents) -----------8085 Micro-processor
MOV BX, [CX] ------------------------------------- 8086 Micro-processor
Direct Addressing if I=0
Indirect Addressing if I=1
 Computer Registers
 What is the need for computer registers?

 List of Registers for basic computer

 Common bus structure
 Registers and memory are connected to common bus.
 Select lines S2, S1 and S0 specify the register for which the bus output is intended
 Particular register whose LD (Load) input is enabled receives data from the bus
during the next clock pulse transition.
 Memory receives bus contents if write input is enabled
 Memory places its 16-bit output onto bus when read input is activated and select
line is 111.
 Registers DR, AC, IR and TR have 16-bits each
 Registers AC and PC have 12-bits each as they hold memory address (12-bit
address)
 When contents of AR or PC are applied to 16-bit common bus, the 4 most
significant bits are set to 0’s.
 When AR or PC receive information from bus, only the 12 least significant bits
are transferred into the register.
 Register INPR and OUTR have 8-bits each and communicate with eight least
significant bits in the bus.
 INTR receives a character from an input device which is transferred to AC.
 OUTR receives a character from AC and delivers it to an output device.
 Registers having LD (load), INR (increment) and CLR (clear) are equivalent to
binary counter with parallel load and synchronous clear.
 16 inputs of AC come from an adder and logic circuit

 Adder and logic circuit has 3 sets of inputs

 16 inputs come from the outputs of AC
 register micro-operations :complement AC, shift AC
 16 inputs come from data register DR
 arithmetic and logic micro-operations: add DR to AC
 8 bit inputs come from INPR

 Two micro-operations can be performed at the same time.

 Eg: DR AC and AC DR
1. Place contents of AC on the bus with S2S1S0 = 100
2. Enabling LD input to DR
3. Transferring the content of DR through the adder and logic
circuit into AC
4. Enabling LD input of AC
 Computer Instructions
 Basic Computer Instruction Code Formats
 Each format has 16 bits
 Opcode part contains 3 bits and remaining 13 bits depend on operation encountered.
 Type of instruction is recognized by the computer control from the four bits in
positions 12 through 15 of the instruction.

 Memory – Reference Instruction

 Uses 12 bits to specify an address
 1 bit to specify addressing mode (I)
 I = 0 => Direct addressing; I=1 => Indirect addressing

 Register – Reference Instruction

 recognized by an opcode of 111 and 0 in the leftmost bit (15th bit)
 specifies an operation on or test of the AC register
 an operand from memory is not required
=> remaining 12 bits are used to specify operation or test to be executed

 Input- Output Instruction

 doesn't need a reference to memory
 recognized by opcode 111 with a 1 in the leftmost bit of the instruction.
 remaining 12 bits are used to specify the type of input – output operation or test
performed.
 Basic Computer Instructions
 Only three bits of instruction are used for operation code.
 Maximum 8 distinct operations can be performed
 As register –reference and input-output instructions use the
remaining 12 bits as part of opcode, total no. of instructions can
exceed 8.
 Total no. of instructions in basic computer = 25

Memory – Reference Instructions

Register – Reference Instructions

I/P –O/P Instructions

 Symbol Designation: a 3-letter word

 Hexadecimal-Code: equivalent to hexadecimal no. of the binary code used for

instruction

 Memory – Reference Instruction

 address part of 12 bits
 address part is denoted by 3 x’s which stand for 3 hexadecimal digits corresponding to 12
bit address
 last bit I =0 => hexadecimal digit = 0 to 6
 last bit I=1 => hexadecimal digit = 8 to E

 Register – Reference Instruction

 uses 16 bits to specify an operation
 left most bits are always 0111 = 7(hexadecimal)
 remaining three hexadecimal digits are binary equivalent of remaining 12 bits

 Input- Output Instruction

 uses 16 bits to specify an operation
 left most bits are always 1111 = F(hexadecimal)
 Instruction Set Completeness
 Set of instructions are said to be complete if the computer
includes a sufficient no. instructions in each of the following
cases:
 Arithmetic, Logical and Shift instructions : ADD, CMA, INC,
AND, CLA
 Instructions for moving information to and from memory and
processor registers: LDA, STA
 Program control instructions together with instructions that check
status conditions: BUN, BSA, ISZ, SPA, SNA, SZA, SZE
 Input and Output instructions: INP, OUT
 Set of instructions in basic computer is complete but not
sufficient because frequently used operations such as subtract,
multiply, OR and XOR are not performed rapidly.
 Timing And Control
 The timing of all registers in the basic computer is controlled by a master
clock generator.

 Clock pulses are applied to all flip-flops and registers in the system, including
the flip-flops and registers in the control unit.

 There are two types of control organization:

 Hardwired Control
Control logic is implemented with gates, flip-flops, decoders and other
digital circuits:
Drawback: Requires changes in wiring among various components if the design is
to be modified.

 Micro-programmed control
Control information is stored in control memory. Control memory is
programmed to initiate the sequence of micro-operations.
Advantage: Any changes can be done by updating the micro-program in control
memory
Control unit Block diagram
 Instruction Cycle
 Each instruction cycle is subdivided into sub-cycles or phases

 Fetch an instruction from memory

 Decode the instruction
 Read effective address from the memory if the instruction has an indirect
address
 Execute the instruction

 Upon completion of step 4, the control goes back to step 1 to fetch, decode,
and execute the next instruction.

 This process continues indefinitely unless a HALT instruction is encountered.

 Fetch and decode RTL statements

T0: PC  AR

T1: IR  M[AR],
PC  PC + 1

T2: D7,..,D0  DECODE (IR(12-14)),

I  IR(15),
AR  IR(0-11)
Register – Reference Instructions
Memory– Reference Instructions
Input – Output Configuration
 The 1-bit flag register FGI is a control bit.
 Initially, FGI is 0.
 FGI is set to 1 to indicate that the input device has some new
information, i.e., INPR has some data.
 FGI is set to 0 when the information is accepted by computer.
 This is used to synchronize the speeds of processor and input devices.
 As long as FGI is 1 input data in INPR cannot be changed.

 FGO works similar to FGI except for in the opposite direction.

 FGO is initially 1.
 When AC has something to display on output device, it is sent to
OUTR and FGO is set to 0.
 FGO is set to 1 when data is accepted by output device.
 As long as FGO is 0, the data in OUTR cannot be altered.
Interrupt Cycle Flowchart
Input – Output Instructions
COMPLETE FLOWCHART
FOR
COMPUTER OPERATION
THANK YOU