14-Bit, 150 MSPS, 1.

8 V
Analog-to-Digital Converter
AD9254
FEATURES FUNCTIONAL BLOCK DIAGRAM
1.8 V analog supply operation AVDD DRVDD

1.8 V to 3.3 V output supply AD9254

SNR = 71.8 dBc (72.8 dBFS) to 70 MHz input VIN+
8-STAGE
SHA MDAC1 A/D
SFDR = 84 dBc to 70 MHz input VIN–
1 1/2-BIT PIPELINE

Low power: 430 mW @ 150 MSPS 4 8 3

A/D
Differential input with 650 MHz bandwidth REFT

On-chip voltage reference and sample-and-hold amplifier REFB

CORRECTION LOGIC OR
DNL = ±0.4 LSB
15
Flexible analog input: 1 V p-p to 2 V p-p range OUTPUT BUFFERS DCO
Offset binary, Gray code, or twos complement data format
D13 (MSB)
Clock duty cycle stabilizer VREF
D0 (LSB)
Data output clock
SENSE SCLK/DFS
0.5V CLOCK
Serial port control DUTY CYCLE MODE
SELECT SDIO/DCS
REF STABILIZER
Built-in selectable digital test pattern generation CSB
SELECT

Programmable clock and data alignment

06216-001
AGND CLK+ CLK– PDWN DRGND
APPLICATIONS
Ultrasound equipment Figure 1.
IF sampling in communications receivers
CDMA2000, WCDMA, TD-SCDMA, and WiMax
Battery-powered instruments
Hand-held scopemeters
Low cost digital oscilloscopes The digital output data is presented in offset binary, Gray code, or
twos complement formats. A data output clock (DCO) is provided
Macro, micro, and pico cell infrastructure
to ensure proper latch timing with receiving logic.
GENERAL DESCRIPTION
The AD9254 is available in a 48-lead LFCSP_VQ and is specified
The AD9254 is a monolithic, single 1.8 V supply, 14-bit, 150 MSPS
over the industrial temperature range (−40°C to +85°C).
analog-to-digital converter (ADC), featuring a high performance
sample-and-hold amplifier (SHA) and on-chip voltage reference.
PRODUCT HIGHLIGHTS
The product uses a multistage differential pipeline architecture
with output error correction logic to provide 14-bit accuracy at 1. The AD9254 operates from a single 1.8 V power supply
150 MSPS data rates and guarantees no missing codes over the and features a separate digital output driver supply to
full operating temperature range. accommodate 1.8 V to 3.3 V logic families.
The wide bandwidth, truly differential SHA allows a variety of 2. The patented SHA input maintains excellent performance
user-selectable input ranges and offsets, including single-ended for input frequencies up to 225 MHz.
applications. It is suitable for multiplexed systems that switch
full-scale voltage levels in successive channels and for sampling 3. The clock DCS maintains overall ADC performance over a
single-channel inputs at frequencies well beyond the Nyquist rate. wide range of clock pulse widths.
Combined with power and cost savings over previously available
4. A standard serial port interface supports various product
ADCs, the AD9254 is suitable for applications in communications,
features and functions, such as data formatting (offset
imaging, and medical ultrasound.
binary, twos complement, or Gray coding), enabling the
A differential clock input controls all internal conversion cycles. clock DCS, power-down, and voltage reference mode.
A duty cycle stabilizer (DCS) compensates for wide variations in
the clock duty cycle while maintaining excellent overall ADC 5. The AD9254 is pin-compatible with the AD9233, allowing
performance. a simple migration from 12 bits to 14 bits.

Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com
Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved.
AD9254

TABLE OF CONTENTS
Features .............................................................................................. 1 Timing ......................................................................................... 20

Applications....................................................................................... 1 Serial Port Interface (SPI).............................................................. 21

General Description ......................................................................... 1 Configuration Using the SPI..................................................... 21

Functional Block Diagram .............................................................. 1 Hardware Interface..................................................................... 21

Product Highlights ........................................................................... 1 Configuration Without the SPI ................................................ 21

Revision History ............................................................................... 2 Memory Map .................................................................................. 22

Specifications..................................................................................... 3 Reading the Memory Map Register Table............................... 22

DC Specifications ......................................................................... 3 Memory Map Register Table..................................................... 23

AC Specifications.......................................................................... 4 Layout Considerations................................................................... 25

Digital Specifications ................................................................... 5 Power and Ground Recommendations ................................... 25

Switching Specifications .............................................................. 6 CML ............................................................................................. 25

Timing Diagram ........................................................................... 6 RBIAS........................................................................................... 25

Absolute Maximum Ratings............................................................ 7 Reference Decoupling................................................................ 25

Thermal Resistance ...................................................................... 7 Evaluation Board ............................................................................ 26

ESD Caution.................................................................................. 7 Power Supplies ............................................................................ 26

Pin Configuration and Function Descriptions............................. 8 Input Signals................................................................................ 26

Equivalent Circuits ........................................................................... 9 Output Signals ............................................................................ 26

Typical Performance Characteristics ........................................... 10 Default Operation and Jumper Selection Settings................. 27

Theory of Operation ...................................................................... 14 Alternative Clock Configurations............................................ 27

Analog Input Considerations.................................................... 14 Alternative Analog Input Drive Configuration...................... 27

Differential Input Configurations ............................................ 15 Schematics................................................................................... 29

Voltage Reference ....................................................................... 16 Evaluation Board Layout........................................................... 34

Clock Input Considerations ...................................................... 17 Bill of Materials........................................................................... 37

Jitter Considerations .................................................................. 19 Outline Dimensions ....................................................................... 40

Power Dissipation and Standby Mode..................................... 19 Ordering Guide .......................................................................... 40

Digital Outputs ........................................................................... 20

REVISION HISTORY
10/06—Revision 0: Initial Version

Rev. 0 | Page 2 of 40
 AD9254

SPECIFICATIONS
DC SPECIFICATIONS
AVDD = 1.8 V; DRVDD = 2.5 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS enabled,
unless otherwise noted.
Table 1.
AD9254BCPZ-150
Parameter Temperature Min Typ Max Unit
RESOLUTION Full 14 Bits
ACCURACY
No Missing Codes Full Guaranteed
Offset Error Full ±0.3 ±0.8 % FSR
Gain Error Full ±0.6 ±4.5 % FSR
Differential Nonlinearity (DNL) 1 25°C ±0.4 LSB
Full ±1.0 LSB
Integral Nonlinearity (INL)1 25°C ±1.5 LSB
Full ±5.0 LSB
TEMPERATURE DRIFT
Offset Error Full ±15 ppm/°C
Gain Error Full ±95 ppm/°C
INTERNAL VOLTAGE REFERENCE
Output Voltage Error (1 V Mode) Full ±5 ±35 mV
Load Regulation @ 1.0 mA Full 7 mV
INPUT REFERRED NOISE
VREF = 1.0 V 25°C 1.3 LSB rms
ANALOG INPUT
Input Span, VREF = 1.0 V Full 2 V p-p
Input Capacitance 2 Full 8 pF
REFERENCE INPUT RESISTANCE Full 6 kΩ
POWER SUPPLIES
Supply Voltage
AVDD Full 1.7 1.8 1.9 V
DRVDD Full 1.7 2.5 3.6 V
Supply Current
IAVDD1 Full 240 260 mA
IDRVDD1(DRVDD = 1.8 V) Full 11 mA
IDRVDD1 (DRVDD = 3.3 V) Full 23 mA
POWER CONSUMPTION
DC Input Full 430 470 mW
Sine Wave Input1 (DRVDD = 1.8 V) Full 450 mW
Sine Wave Input1 (DRVDD = 3.3 V) Full 506 mW
Standby Power 3 Full 40 mW
Power-Down Power Full 1.8 mW
1
Measured with a low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit.
2
Input capacitance refers to the effective capacitance between one differential input pin and AGND. Refer to Figure 4 for the equivalent analog input structure.
3
Standby power is measured with a dc input, the CLK pin inactive (set to AVDD or AGND).

Rev. 0 | Page 3 of 40
AD9254
AC SPECIFICATIONS
AVDD = 1.8 V; DRVDD = 2.5 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS enabled,
unless otherwise noted.
Table 2.
AD9254BCPZ-150
Parameter 1 Temperature Min Typ Max Unit
SIGNAL-TO-NOISE-RATIO (SNR)
fIN = 2.4 MHz 25°C 72.0 dBc
fIN = 70 MHz 25°C 71.8 dBc
Full 70.0 dBc
fIN = 100 MHz 25°C 71.6 dBc
fIN = 170 MHz 25°C 70.8 dBc
SIGNAL-TO-NOISE AND DISTORTION (SINAD)
fIN = 2.4 MHz 25°C 71.7 dBc
fIN = 70 MHz 25°C 71.0 dBc
Full 69.0 dBc
fIN = 100 MHz 25°C 70.6 dBc
fIN = 170 MHz 25°C 69.8 dBc
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 2.4 MHz 25°C 11.7 Bits
fIN = 70 MHz 25°C 11.7 Bits
fIN = 100 MHz 25°C 11.6 Bits
fIN = 170 MHz 25°C 11.5 Bits
WORST SECOND OR THIRD HARMONIC
fIN = 2.4 MHz 25°C −90 dBc
fIN = 70 MHz 25°C −84 dBc
Full −74 dBc
fIN = 100 MHz 25°C −83 dBc
fIN = 170 MHz 25°C −80 dBc
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fIN = 2.4 MHz 25°C 90 dBc
fIN = 70 MHz 25°C 84 dBc
Full 74 dBc
fIN = 100 MHz 25°C 83 dBc
fIN = 170 MHz 25°C 80 dBc
WORST OTHER (HARMONIC OR SPUR)
fIN = 2.4 MHz 25°C −93 dBc
fIN = 70 MHz 25°C −93 dBc
Full −85 dBc
fIN = 100 MHz 25°C −90 dBc
fIN = 170 MHz 25°C −90 dBc
TWO-TONE SFDR
fIN = 29 MHz (−7 dBFS ), 32 MHz (−7 dBFS ) 25°C 90 dBFS
fIN = 169 MHz (−7 dBFS ), 172 MHz (−7 dBFS ) 25°C 90 dBFS
ANALOG INPUT BANDWIDTH 25°C 650 MHz
1
See Application Note AN-835, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.

Rev. 0 | Page 4 of 40
 AD9254
DIGITAL SPECIFICATIONS
AVDD = 1.8 V; DRVDD = 2.5 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS enabled,
unless otherwise noted.
Table 3.
AD9254BCPZ-150
Parameter Temperature Min Typ Max Unit
DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)
Logic Compliance CMOS/LVDS/LVPECL
Internal Common-Mode Bias Full 1.2 V
Differential Input Voltage Full 0.2 6 V p-p
Input Voltage Range Full AVDD − 0.3 AVDD + 1.6 V
Input Common-Mode Range Full 1.1 AVDD V
High Level Input Voltage (VIH) Full 1.2 3.6 V
Low Level Input Voltage (VIL) Full 0 0.8 V
High Level Input Current (IIH) Full −10 +10 μA
Low Level Input Current (IIL) Full −10 +10 μA
Input Resistance Full 8 10 12 kΩ
Input Capacitance Full 4 pF
LOGIC INPUTS (SCLK/DFS, OEB, PWDN)
High Level Input Voltage (VIH) Full 1.2 3.6 V
Low Level Input Voltage (VIL) Full 0 0.8 V
High Level Input Current (IIH) Full −50 −75 μA
Low Level Input Current (IIL) Full −10 +10 μA
Input Resistance Full 30 kΩ
Input Capacitance Full 2 pF
LOGIC INPUTS (CSB)
High Level Input Voltage (VIH) Full 1.2 3.6 V
Low Level Input Voltage (VIL) Full 0 0.8 V
High Level Input Current (IIH) Full −10 +10 μA
Low Level Input Current (IIL) Full +40 +135 μA
Input Resistance Full 26 kΩ
Input Capacitance Full 2 pF
LOGIC INPUTS (SDIO/DCS)
High Level Input Voltage (VIH) Full 1.2 DRVDD + 0.3 V
Low Level Input Voltage (VIL) Full 0 0.8 V
High Level Input Current (IIH) Full −10 +10 μA
Low Level Input Current (IIL) Full +40 +130 μA
Input Resistance Full 26 kΩ
Input Capacitance Full 5 pF
DIGITAL OUTPUTS
DRVDD = 3.3 V
High Level Output Voltage (VOH, IOH = 50 μA) Full 3.29 V
High Level Output Voltage (VOH, IOH = 0.5 mA) Full 3.25 V
Low Level Output Voltage (VOL, IOL = 1.6 mA) Full 0.2 V
Low Level Output Voltage (VOL, IOL = 50 μA) Full 0.05 V
DRVDD = 1.8 V
High Level Output Voltage (VOH, IOH = 50 μA) Full 1.79 V
High Level Output Voltage (VOH, IOH = 0.5 mA) Full 1.75 V
Low Level Output Voltage (VOL, IOL = 1.6 mA) Full 0.2 V
Low Level Output Voltage (VOL, IOL = 50 μA) Full 0.05 V

Rev. 0 | Page 5 of 40
AD9254
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 2.5 V, unless otherwise noted.
Table 4.
AD9254BCPZ-150
Parameter 1 Temperature Min Typ Max Unit
CLOCK INPUT PARAMETERS
Conversion Rate, DCS Enabled Full 20 150 MSPS
Conversion Rate, DCS Disabled Full 10 150 MSPS
CLK Period Full 6.7 ns
CLK Pulse Width High, DCS Enabled Full 2.0 3.3 4.7 ns
CLK Pulse Width High, DCS Disabled Full 3.0 3.3 3.7 ns
DATA OUTPUT PARAMETERS
Data Propagation Delay (tPD) 2 Full 3.1 3.9 4.8 ns
DCO Propagation Delay (tDCO) Full 4.4 ns
Setup Time (tS) Full 1.9 2.9 ns
Hold Time (tH) Full 3.0 3.8 ns
Pipeline Delay (Latency) Full 12 Cycles
Aperture Delay (tA) Full 0.8 ns
Aperture Uncertainty (Jitter, tJ) Full 0.1 ps rms
Wake-Up Time 3 Full 350 μs
OUT-OF-RANGE RECOVERY TIME Full 3 Cycles
SERIAL PORT INTERFACE 4
SCLK Period (tCLK) Full 40 ns
SCLK Pulse Width High Time (tHI) Full 16 ns
SCLK Pulse Width Low Time (tLO) Full 16 ns
SDIO to SCLK Setup Time (tDS) Full 5 ns
SDIO to SCLK Hold Time (tDH) Full 2 ns
CSB to SCLK Setup Time (tS) Full 5 ns
CSB to SCLK Hold Time (tH) Full 2 ns
1
See Application Note AN-835, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.
2
Output propagation delay is measured from CLK 50% transition to DATA 50% transition, with 5 pF load.
3
Wake-up time is dependent on the value of the decoupling capacitors, values shown with 0.1 μF capacitor across REFT and REFB.
4
See Figure 50 and the Serial Port Interface (SPI) section.

TIMING DIAGRAM
N+2
N+1
N+3
N
N+4
N+8
tA
N+5
N+6 N+7
tCLK
CLK+

CLK–
tPD

DATA N – 13 N – 12 N – 11 N – 10 N–9 N–8 N–7 N–6 N–5 N–4

tS tH tDCO tCLK
06216-002

DCO

Figure 2. Timing Diagram

Rev. 0 | Page 6 of 40
 AD9254

ABSOLUTE MAXIMUM RATINGS

Table 5. Stresses above those listed under Absolute Maximum Ratings
Parameter Rating may cause permanent damage to the device. This is a stress
ELECTRICAL rating only; functional operation of the device at these or any
AVDD to AGND −0.3 V to +2.0 V other conditions above those indicated in the operational
DRVDD to DGND −0.3 V to +3.9 V section of this specification is not implied. Exposure to absolute
AGND to DGND −0.3 V to +0.3 V maximum rating conditions for extended periods may affect
AVDD to DRVDD −3.9 V to +2.0 V device reliability.
D0 through D13 to DGND −0.3 V to DRVDD + 0.3 V
DCO to DGND −0.3 V to DRVDD + 0.3 V THERMAL RESISTANCE
OR to DGND −0.3 V to DRVDD + 0.3 V The exposed paddle must be soldered to the ground plane for
CLK+ to AGND −0.3 V to +3.9 V the LFCSP_VQ package. Soldering the exposed paddle to the
CLK− to AGND −0.3 V to +3.9 V customer board increases the reliability of the solder joints,
VIN+ to AGND −0.3 V to AVDD + 0.2 V maximizing the thermal capability of the package.
VIN− to AGND −0.3 V to AVDD + 0.2 V Table 6. Thermal Resistance
VREF to AGND −0.3 V to AVDD + 0.2 V
Package Type θJA θJC Unit
SENSE to AGND −0.3 V to AVDD + 0.2 V
48-lead LFCSP_VQ (CP-48-3) 26.4 2.4 °C/W
REFT to AGND −0.3 V to AVDD + 0.2 V
REFB to AGND −0.3 V to AVDD + 0.2 V Typical θJA and θJC are specified for a 4-layer board in still air.
SDIO/DCS to DGND −0.3 V to DRVDD + 0.3 V Airflow increases heat dissipation, effectively reducing θJA. In
PDWN to AGND −0.3 V to +3.9 V addition, metal in direct contact with the package leads from
CSB to AGND −0.3 V to +3.9 V metal traces and through holes, ground, and power planes,
SCLK/DFS to AGND −0.3 V to +3.9 V reduces the θJA.
OEB to AGND −0.3 V to +3.9 V
ENVIRONMENTAL
Storage Temperature Range –65°C to +125°C ESD CAUTION
Operating Temperature Range –40°C to +85°C
Lead Temperature 300°C
(Soldering 10 Sec)
Junction Temperature 150°C

Rev. 0 | Page 7 of 40
AD9254

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

D0 (LSB)
DRGND
DRVDD

AGND

AGND
AVDD

AVDD

CLK+
CLK–
DCO
OEB
D1
48
47
46
45
44
43
42
41
40
39
38
37
D2 1 36 PDWN
PIN 1
D3 2 INDICATOR 35 RBIAS
D4 3 34 CML
D5 4 33 AVDD
D6 5 32 AGND
D7 6 AD9254 31 VIN–
DRGND 7 TOP VIEW 30 VIN+
DRVDD 8 (Not to Scale) 29 AGND
D8 9 28 REFT
D9 10 27 REFB
D10 11 26 VREF
D11 12 25 SENSE

21
13
14
15
16
17
18
19
20

22
23
24
OR

SDIO/DCS
SCLK/DFS
CSB
AGND

AGND
D12

DRGND

AVDD

AVDD
DRVDD
D13 (MSB)

06216-003
Figure 3. Pin Configuration

Table 7. Pin Function Description

Pin No. Mnemonic Description
0, 21, 23, 29, 32, AGND Analog Ground. (Pin 0 is the exposed thermal pad on the bottom of the package.)
37, 41
45, 46, 1 to 6, D0 (LSB) to D13 (MSB) Data Output Bits.
9 to 14
7, 16, 47 DRGND Digital Output Ground.
8, 17, 48 DRVDD Digital Output Driver Supply (1.8 V to 3.3 V).
15 OR Out-of-Range Indicator.
18 SDIO/DCS Serial Port Interface (SPI) Data Input/Output (Serial Port Mode); Duty Cycle Stabilizer Select
(External Pin Mode). See Table 10.
19 SCLK/DFS Serial Port Interface Clock (Serial Port Mode); Data Format Select Pin (External Pin Mode).
20 CSB Serial Port Interface Chip Select (Active Low). See Table 10.
22, 24, 33, 40, 42 AVDD Analog Power Supply.
25 SENSE Reference Mode Selection. See Table 9.
26 VREF Voltage Reference Input/Output.
27 REFB Differential Reference (−).
28 REFT Differential Reference (+).
30 VIN+ Analog Input Pin (+).
31 VIN– Analog Input Pin (−).
34 CML Common-Mode Level Bias Output.
35 RBIAS External Bias Resistor Connection. A 10 kΩ resistor must be connected between this pin and
analog ground (AGND).
36 PDWN Power-Down Function Select.
38 CLK+ Clock Input (+).
39 CLK– Clock Input (−).
43 OEB Output Enable (Active Low).
44 DCO Data Clock Output.

Rev. 0 | Page 8 of 40
 AD9254

EQUIVALENT CIRCUITS
1kΩ
SCLK/DFS
VIN OEB
PDWN 30kΩ

06216-004

06216-008
Figure 4. Equivalent Analog Input Circuit Figure 8. Equivalent SCLK/DFS, OEB, PDWN Input Circuit

AVDD

AVDD

1.2V 26kΩ
1kΩ
CSB
10kΩ 10kΩ
CLK+ CLK–

06216-009
06216-005

Figure 5. Equivalent Clock Input Circuit Figure 9. Equivalent CSB Input Circuit

DRVDD 1kΩ
SENSE

1kΩ
SDIO/DCS

06216-010
06216-006

Figure 6. Equivalent SDIO/DCS Input Circuit Figure 10. Equivalent Sense Circuit

DRVDD

AVDD

VREF
06216-011

6kΩ
06216-007

DRGND
Figure 11. Equivalent VREF Circuit
Figure 7. Equivalent Digital Output Circuit

Rev. 0 | Page 9 of 40
AD9254

TYPICAL PERFORMANCE CHARACTERISTICS

AVDD = 1.8 V; DRVDD = 2.5 V; maximum sample rate, DCS enabled, 1 V internal reference; 2 V p-p differential input; AIN = −1.0 dBFS;
64k sample; TA = 25°C, unless otherwise noted.
0 0
150MSPS 150MSPS
2.3MHz @ –1dBFS 100.3MHz @ –1dBFS
SNR = 72.0dBc (73.0dBFS) SNR = 71.6dBc (72.6dBFS)
–20 –20
ENOB = 11.7 BITS ENOB = 11.6 BITS
SFDR = 90.0dBc SFDR = 83dBc
AMPLITUDE (dBFS)

AMPLITUDE (dBFS)
–40 –40

–60 –60

–80 –80

–100 –100

–120 –120
06216-012

06216-015
0 18.75 37.50 56.25 75.00 0 18.75 37.50 56.25 75.00
FREQUENCY (MHz) FREQUENCY (MHz)

Figure 12. AD9254 Single-Tone FFT with fIN = 2.3 MHz Figure 15. AD9254 Single-Tone FFT with fIN = 100.3 MHz

0 0
150MSPS 150MSPS
30.3MHz @ –1dBFS 140.3MHz @ –1dBFS
SNR = 71.9dBc (72.9dBFS) SNR = 71.5dBc (72.5dBFS)
–20 –20
ENOB = 11.7 BITS ENOB = 11.5 BITS
SFDR = 88dBc SFDR = 81dBc
AMPLITUDE (dBFS)

AMPLITUDE (dBFS)

–40 –40

–60 –60

–80 –80

–100 –100

–120 –120
06216-013

06216-016
0 18.75 37.50 56.25 75.00 0 18.75 37.50 56.25 75.00
FREQUENCY (MHz) FREQUENCY (MHz)

Figure 13. AD9254 Single-Tone FFT with fIN = 30.3 MHz Figure 16. AD9254 Single-Tone FFT with fIN = 140.3 MHz

0 0
150MSPS 150MSPS
70.3MHz @ –1dBFS 170.3MHz @ –1dBFS
SNR = 71.8dBc (72.8dBFS) SNR = 70.8dBc (71.8dBFS)
–20 –20
ENOB = 11.7 BITS ENOB = 11.5 BITS
SFDR = 84dBc SFDR = 80dBc
AMPLITUDE (dBFS)

AMPLITUDE (dBFS)

–40 –40

–60 –60

–80 –80

–100 –100

–120 –120
06216-014

06216-017

0 18.75 37.50 56.25 75.00 0 18.75 37.50 56.25 75.00

FREQUENCY (MHz) FREQUENCY (MHz)

Figure 14. AD9254 Single-Tone FFT with fIN = 70.3 MHz Figure 17. AD9254 Single-Tone FFT with fIN = 170.3 MHz

Rev. 0 | Page 10 of 40
 AD9254
0 120
150MSPS
250.3MHz @ –1dBFS SFDR (dBFS)
SNR = 69.3dBc (70.3dBFS)
–20 100
ENOB = 11.3 BITS
SFDR = 79dBc

SNR/SFDR (dBc and dBFS)

AMPLITUDE (dBFS)

–40 80 SNR (dBFS)

–60 60

–80 40
SFDR (dBc)
85dBc
REFERENCE LINE
–100 20
SNR (dBc)
–120 0

06216-018

06216-021
0 18.75 37.50 56.25 75.00 –90 –80 –70 –60 –50 –40 –30 –20 –10 0
FREQUENCY (MHz) INPUT AMPLITUDE (dBFS)

Figure 18. AD9254 Single-Tone FFT with fIN = 250.3 MHz Figure 21. AD9254 Single-Tone SNR/SFDR vs. Input Amplitude (AIN)
with fIN = 2.4 MHz

0 0
150MSPS
fIN1 = 29.1MHz @ –7dBFS
fIN2 = 32.1MHz @ –7dBFS

SFDR/WORST IMD3 (dBc and dBFS)

–20 –20
SFDR = 83.2dBc (90.2dBFS)
WoIMD3 = –83.9dBc (–90.9dBFS) SFDR (–dBc)
AMPLITUDE (dBFS)

–40 –40
WORST IMD3 (dBc)

–60 –60

–80 –80

SFDR (–dBFS)
–100 –100

WORST IMD3 (dBFS)

–120 –120
06216-019

06216-022
0 18.75 37.50 56.25 75.00 –90 –78 –66 –54 –42 –30 –18 –6
FREQUENCY (MHz) INPUT AMPLITUDE (dBFS)

Figure 19. AD9254 Two-Tone FFT with fIN1 = 29.1 MHz, fIN2 = 32.1 MHz Figure 22. AD9254 Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN)
with fIN1 = 29.1 MHz, fIN2 = 32.1 MHz

90 90
SFDR +25°C
SFDR –40°C SFDR –40°C
85 85

SFDR +25°C
80 80
SNR/SFDR (dBc)
SNR/SFDR (dBc)

SFDR +85°C
75 75
SNR –40°C
SFDR +85°C
70 70
SNR +25°C SNR –40°C

65 65
SNR +25°C
SNR +85°C
SNR +85°C
60 60
06216-023
06216-020

0 50 100 150 200 250 300 350 400 0 50 100 150 200 250 300 350 400
INPUT FREQUENCY (MHz) INPUT FREQUENCY (MHz)

Figure 20. AD9254 Single-Tone SNR/SFDR vs. Input Frequency (fIN) and Figure 23. AD9254 Single-Tone SNR/SFDR vs. Input Frequency (fIN) and
Temperature with 2 V p-p Full Scale Temperature with 1 V p-p Full Scale

Rev. 0 | Page 11 of 40
AD9254
0 2.0
150MSPS
fIN1 = 169.1MHz @ –7dBFS
fIN2 = 172.1MHz @ –7dBFS 1.5
–20
SFDR = 83dBc (90dBFS)
WoIMD3 = –83dBc (90dBFS) 1.0
AMPLITUDE (dBFS)

–40

INL ERROR (LSB)

0.5

–60 0

–0.5
–80
–1.0

–100
–1.5

–120 –2.0

06216-031
06216-024
0 18.75 37.50 56.25 75.00 0 2048 4096 6144 8192 10240 12288 14336 16384
FREQUENCY (MHz) OUTPUT CODE

Figure 24. AD9254 Two-Tone FFT with fIN1 = 169.1 MHz, fIN2 = 172.1 MHz Figure 27. AD9254 INL with fIN = 10.3 MHz

95 12000
32768 SAMPLES
1.25 LSB rms
90 10000

SFDR
85 8000
NUMBER OF HITS
SNR/SFDR (dBc)

80 6000

75 4000
SNR

70 2000

65 0

06216-032
06216-025

10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 N–5N–4N–3N–2N–1 N N+1N+2N+3N+4N+5

CLOCK FREQUENCY (MSPS) CODE

Figure 25. AD9254 Single-Tone SNR/SFDR vs. Clock Frequency (fCLK) Figure 28. AD9254 Grounded Input Histogram
with fIN = 2.4 MHz

0 0

OFFSET ERROR
SFDR/WORST IMD3 (dBc and dBFS)

–20
–0.5
SFDR (–dBc)

–40
ERROR (%FS)

WORST IMD3 (dBc) –1.0

–60

–1.5
–80 GAIN ERROR

SFDR (–dBFS) –2.0

–100

WORST IMD3 (dBFS)

–120 –2.5
06216-033
06216-027

–90 –78 –66 –54 –42 –30 –18 –6 –40 –20 0 20 40 60 80

INPUT AMPLITUDE (dBFS) TEMPERATURE (°C)

Figure 26. AD9254 Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) Figure 29. AD9254 Gain and Offset vs. Temperature
with fIN1 = 169.1 MHz, fIN2 = 172.11 MHz

Rev. 0 | Page 12 of 40
 AD9254
0.5

0.4

0.3

0.2
DNL ERROR (LSB)

0.1

–0.1

–0.2

–0.3

–0.4

–0.5

06216-034
0 2048 4096 6144 8192 10240 12288 14336 16384
OTUPUT CODE

Figure 30. AD9254 DNL with fIN = 10.3 MHz

Rev. 0 | Page 13 of 40
AD9254
THEORY OF OPERATION
The AD9254 architecture consists of a front-end sample-and-
hold amplifier (SHA) followed by a pipelined switched capacitor
ADC. The quantized outputs from each stage are combined into
a final 14-bit result in the digital correction logic. The pipeline
architecture permits the first stage to operate on a new input
sample, while the remaining stages operate on preceding samples.
Sampling occurs on the rising edge of the clock.
Each stage of the pipeline, excluding the last, consists of a low
resolution flash ADC connected to a switched capacitor DAC
and interstage residue amplifier (MDAC). The residue amplifier
magnifies the difference between the reconstructed DAC output
and the flash input for the next stage in the pipeline. One bit of
redundancy is used in each stage to facilitate digital correction
of flash errors. The last stage consists only of a flash ADC.
The input stage contains a differential SHA that can be ac- or
dc-coupled in differential or single-ended modes. The output
staging block aligns the data, carries out the error correction,
and passes the data to the output buffers. The output buffers
are powered from a separate supply, allowing adjustment of the
output voltage swing. During power-down, the output buffers
go into a high impedance state.
ANALOG INPUT CONSIDERATIONS
The analog input to the AD9254 is a differential switched
capacitor SHA that has been designed for optimum
performance while processing a differential input signal.
The clock signal alternately switches the SHA between sample
mode and hold mode (see Figure 31). When the SHA is switched
into sample mode, the signal source must be capable of charging
the sample capacitors and settling within one-half of a clock
cycle. A small resistor in series with each input can help reduce
the peak transient current required from the output stage of the
driving source.
A shunt capacitor can be placed across the inputs to provide
dynamic charging currents. This passive network creates a low-
pass filter at the ADC input; therefore, the precise values are
dependent upon the application.
In IF undersampling applications, any shunt capacitors should
be reduced. In combination with the driving source impedance,
these capacitors would limit the input bandwidth. For more
information, see Application Note AN-742, Frequency Domain
Response of Switched-Capacitor ADCs; Application Note AN-827,
A Resonant Approach to Interfacing Amplifiers to Switched-
Capacitor ADCs; and the Analog Dialogue article, “Transformer-
Coupled Front-End for Wideband A/D Converters.”
Rev. 0 | Page 14 of 40
S
CH
S
CS
VIN+
CPIN, PAR S
H
CS
VIN–
CPIN, PAR CH
06216-035
S
Figure 31. Switched-Capacitor SHA Input
For best dynamic performance, the source impedances driving
VIN+ and VIN− should match such that common-mode settling
errors are symmetrical. These errors are reduced by the
common-mode rejection of the ADC.
An internal differential reference buffer creates two reference
voltages used to define the input span of the ADC core. The
span of the ADC core is set by the buffer to be 2 × VREF. The
reference voltages are not available to the user. Two bypass points,
REFT and REFB, are brought out for decoupling to reduce the
noise contributed by the internal reference buffer. It is recom-
mended that REFT be decoupled to REFB by a 0.1 μF capacitor,
as described in the Layout Considerations section.
Input Common Mode
The analog inputs of the AD9254 are not internally dc-biased.
In ac-coupled applications, the user must provide this bias
externally. Setting the device such that VCM = 0.55 × AVDD is
recommended for optimum performance; however, the device
functions over a wider range with reasonable performance (see
Figure 30). An on-board common-mode voltage reference is
included in the design and is available from the CML pin.
Optimum performance is achieved when the common-mode
voltage of the analog input is set by the CML pin voltage
(typically 0.55 × AVDD). The CML pin must be decoupled to
ground by a 0.1 μF capacitor, as described in the Layout
Considerations section.
 AD9254
DIFFERENTIAL INPUT CONFIGURATIONS As an alternative to using a transformer-coupled input at
Optimum performance is achieved by driving the AD9254 in a frequencies in the second Nyquist zone, the AD8352 differential
differential input configuration. For baseband applications, the driver can be used (see Figure 36).
AD8138 differential driver provides excellent performance and a In any configuration, the value of the shunt capacitor, C,
flexible interface to the ADC. The output common-mode voltage is dependent on the input frequency and source impedance and
of the AD8138 is easily set with the CML pin of the AD9254 (see may need to be reduced or removed. Table 8 displays recom-
Figure 32), and the driver can be configured in a Sallen-Key filter mended values to set the RC network. However, these values are
topology to provide band limiting of the input signal. dependent on the input signal and should only be used as a
starting guide.
1V p-p 49.9Ω
499Ω Table 8. RC Network Recommended Values
R
VIN+ AVDD Frequency Range (MHz) R Series (Ω) C Differential (pF)
499Ω
0 to 70 33 15
AD8138 C AD9254
0.1µF
70 to 200 33 5
523Ω R
VIN– CML 200 to 300 15 5

06216-036
499Ω >300 15 Open

Figure 32. Differential Input Configuration Using the AD8138 Single-Ended Input Configuration
Although not recommended, it is possible to operate the
For baseband applications where SNR is a key parameter, AD9254 in a single-ended input configuration, as long as the
differential transformer coupling is the recommended input input voltage swing is within the AVDD supply. Single-ended
configuration (see Figure 33). The CML voltage can be operation can provide adequate performance in cost-sensitive
connected to the center tap of the secondary winding of the applications.
transformer to bias the analog input.
In this configuration, SFDR and distortion performance
The signal characteristics must be considered when selecting degrade due to the large input common-mode swing. If the
a transformer. Most RF transformers saturate at frequencies source impedances on each input are matched, there should be
below a few megahertz, and excessive signal power can cause little effect on SNR performance. Figure 34 details a typical
core saturation, which leads to distortion. single-ended input configuration.
R
VIN+ AVDD
10µF
1kΩ
2V p-p
49.9Ω C AD9254 R
VIN+
R CML 49.9Ω 0.1µF
VIN– 1kΩ
1V p-p
AVDD C AD9254
1kΩ
R
06216-037

0.1µF VIN–
10µF 0.1µF 1kΩ

06216-038
Figure 33. Differential Transformer-Coupled Configuration
Figure 34. Single-Ended Input Configuration
At input frequencies in the second Nyquist zone and above, the
noise performance of most amplifiers is not adequate to achieve
the true SNR performance of the AD9254. For applications
where SNR is a key parameter, transformer coupling is the
recommended input. For applications where SFDR is a key
parameter, differential double balun coupling is the recom-
mended input configuration (see Figure 35).

Rev. 0 | Page 15 of 40
AD9254

0.1µF 0.1µF R
2V p-p VIN+
25Ω
PA S S P C AD9254
25Ω 0.1µF
0.1µF R

06216-039
VIN– CML

Figure 35. Differential Double Balun Input Configuration

VCC

0.1µF
0.1µF
0Ω 16
8, 13
1 11 0.1µF R
2 VIN+
200Ω
RD RG AD8352 C AD9254
CD 3 200Ω
10 0.1µF R
VIN– CML
4
5
14
0Ω 0.1µF
0.1µF

06216-040
0.1µF

Figure 36. Differential Input Configuration Using the AD8352

Table 9. Reference Configuration Summary

Resulting Differential
Selected Mode SENSE Voltage Resulting VREF (V) Span (V p-p)
External Reference AVDD N/A 2 × external reference
Internal Fixed Reference VREF 0.5 1.0
Programmable Reference 0.2 V to VREF 2 × VREF
0.5 × ⎛⎜1 +
R2 ⎞
⎟ (see Figure 38)
⎝ R1 ⎠
Internal Fixed Reference AGND to 0.2 V 1.0 2.0

VOLTAGE REFERENCE
A stable and accurate voltage reference is built into the AD9254.
The input range is adjustable by varying the reference voltage
applied to the AD9254, using either the internal reference or an
externally applied reference voltage. The input span of the ADC
tracks reference voltage changes linearly. The various reference
modes are summarized in the following sections. The Reference
Decoupling section describes the best practices and require-
ments for PCB layout of the reference.
Internal Reference Connection
A comparator within the AD9254 detects the potential at the
SENSE pin and configures the reference into four possible
states, as summarized in Table 9. If SENSE is grounded, the
reference amplifier switch is connected to the internal resistor
divider (see Figure 37), setting VREF to 1 V.
Connecting the SENSE pin to VREF switches the reference
amplifier input to the SENSE pin, completing the loop and
providing a 0.5 V reference output. If a resistor divider is
connected external to the chip, as shown in Figure 38, the
switch sets to the SENSE pin. This puts the reference amplifier
in a noninverting mode with the VREF output defined as
VREF = 0.5 ⎛⎜1 +
R2 ⎞
⎟
⎝ R1 ⎠
If the SENSE pin is connected to AVDD, the reference amplifier
is disabled, and an external reference voltage can be applied to
the VREF pin (see the External Reference Operation section).
The input range of the ADC always equals twice the voltage at
the reference pin for either an internal or an external reference.

Rev. 0 | Page 16 of 40
 AD9254
VIN+ External Reference Operation

–
ADC
VIN– CORE

–
REFT The use of an external reference may be necessary to enhance
the gain accuracy of the ADC or improve thermal drift
0.1µF characteristics. Figure 40 shows the typical drift characteristics
of the internal reference in both 1 V and 0.5 V modes.
REFB 10
VREF

0.1µF 0.1µF

REFERENCE VOLTAGE ERROR (mV)

SELECT 8 VREF = 1V
LOGIC
SENSE

0.5V 6 VREF = 0.5V

06216-041
AD9254 4

Figure 37. Internal Reference Configuration

2

VIN+
–

ADC
VIN– CORE 0
–

06216-044
–40 –20 0 20 40 60 80
REFT
TEMPERATURE (°C)

0.1µF
Figure 40. Typical VREF Drift

REFB
When the SENSE pin is tied to AVDD, the internal reference is
VREF disabled, allowing the use of an external reference. An internal
0.1µF 0.1µF R2 resistor divider loads the external reference with an equivalent
SELECT
LOGIC 6 kΩ load (see Figure 11). In addition, an internal buffer
SENSE
generates the positive and negative full-scale references for the
0.5V
ADC core. Therefore, the external reference must be limited to
R1
a maximum of 1 V.
06216-042

AD9254
CLOCK INPUT CONSIDERATIONS
Figure 38. Programmable Reference Configuration For optimum performance, the AD9254 sample clock inputs
(CLK+ and CLK−) should be clocked with a differential signal.
If the internal reference of the AD9254 is used to drive multiple
The signal is typically ac-coupled into the CLK+ pin and the
converters to improve gain matching, the loading of the reference
CLK− pin via a transformer or capacitors. These pins are biased
by the other converters must be considered. Figure 39 depicts
internally (see Figure 5) and require no external bias.
how the internal reference voltage is affected by loading.
0 Clock Input Options
VREF = 0.5V The AD9254 has a very flexible clock input structure. The clock
REFERENCE VOLTAGE ERROR (%)

–0.25 input can be a CMOS, LVDS, LVPECL, or sine wave signal.

Regardless of the type of signal used, the jitter of the clock
VREF = 1V
source is of the most concern, as described in the Jitter
–0.50
Considerations section.

–0.75
Figure 41 shows one preferred method for clocking the
AD9254. A low jitter clock source is converted from single-
ended to a differential signal using an RF transformer. The
–1.00
back-to-back Schottky diodes across the transformer secondary
limit clock excursions into the AD9254 to approximately 0.8 V p-p
–1.25 differential. This helps prevent the large voltage swings of the
06216-043

0 0.5 1.0 1.5 2.0

clock from feeding through to other portions of the AD9254,
LOAD CURRENT (mA)
while preserving the fast rise and fall times of the signal, which
Figure 39. VREF Accuracy vs. Load
are critical to a low jitter performance.

Rev. 0 | Page 17 of 40
AD9254

VCC
MINI-CIRCUITS
ADT1–1WT, 1:1Z 0.1µF OPTIONAL
1kΩ 100Ω 0.1µF
0.1µF 0.1µF CLOCK AD951x
XFMR CMOS DRIVER CLK+
CLOCK CLK+ INPUT
INPUT 50Ω1 1kΩ ADC
50Ω 100Ω ADC
0.1µF AD9254 AD9254
CLK– CLK–
SCHOTTKY

06216-045
0.1µF DIODES: 0.1µF 39kΩ

06216-048
HMS2812
150Ω RESISTOR IS OPTIONAL.
Figure 41. Transformer Coupled Differential Clock
Figure 44. Single-Ended 1.8 V CMOS Sample Clock
If a low jitter clock source is not available, another option is to
ac-couple a differential PECL signal to the sample clock input VCC
OPTIONAL 0.1µF
pins as shown in Figure 42. The AD9510/AD9511/AD9512/ 0.1µF 1kΩ 100Ω
CLOCK AD951x
CLK+
AD9513/AD9514/AD9515 family of clock drivers offers INPUT CMOS DRIVER
50Ω1 1kΩ ADC
excellent jitter performance. AD9254
0.1µF
CLK–

06216-049
150Ω RESISTOR IS OPTIONAL.
0.1µF 0.1µF
CLOCK CLK CLK+
INPUT Figure 45. Single-Ended 3.3 V CMOS Sample Clock
100Ω
ADC
AD951x AD9254
0.1µF PECL DRIVER 0.1µF
Clock Duty Cycle
CLOCK CLK–
CLK
INPUT
240Ω 240Ω
Typical high speed ADCs use both clock edges to generate a
50Ω1 50Ω1
variety of internal timing signals. As a result, these ADCs may
06216-046

150Ω RESISTORS ARE OPTIONAL. be sensitive to clock duty cycle. Commonly, a ±5% tolerance is
Figure 42. Differential PECL Sample Clock required on the clock duty cycle to maintain dynamic
performance characteristics.
A third option is to ac-couple a differential LVDS signal to the
sample clock input pins, as shown in Figure 43. The AD9510/ The AD9254 contains a duty cycle stabilizer (DCS) that retimes
AD9511/AD9512/AD9513/AD9514/AD9515 family of clock the nonsampling, or falling edge, providing an internal clock
drivers offers excellent jitter performance. signal with a nominal 50% duty cycle. This allows a wide range
of clock input duty cycles without affecting the performance of
the AD9254. Noise and distortion performance are nearly flat
0.1µF 0.1µF for a wide range of duty cycles when the DCS is on, as shown in
CLOCK CLK CLK+
INPUT Figure 28.
100Ω ADC
AD951x
0.1µF LVDS DRIVER
AD9254
0.1µF Jitter in the rising edge of the input is still of paramount concern
CLOCK CLK CLK–
INPUT and is not reduced by the internal stabilization circuit. The duty
50Ω1 50Ω1
cycle control loop does not function for clock rates less than
06216-047

150Ω RESISTORS ARE OPTIONAL.
Figure 43. Differential LVDS Sample Clock
In some applications, it is acceptable to drive the sample clock
inputs with a single-ended CMOS signal. In such applications,
directly drive CLK+ from a CMOS gate, while bypassing the
CLK− pin to ground using a 0.1 μF capacitor in parallel with a
39 kΩ resistor (see Figure 44). CLK+ can be directly driven
from a CMOS gate. This input is designed to withstand input
voltages up to 3.6 V, making the selection of the drive logic
voltage very flexible. When driving CLK+ with a 1.8 V CMOS
signal, biasing the CLK− pin with a 0.1 μF capacitor in parallel
with a 39 kΩ resistor (see Figure 44) is required. The 39 kΩ
resistor is not required when driving CLK+ with a 3.3 V CMOS
signal (see Figure 45).
20 MHz nominally. The loop has a time constant associated
with it that needs to be considered in applications where the
clock rate can change dynamically. This requires a wait time
of 1.5 μs to 5 μs after a dynamic clock frequency increase (or
decrease) before the DCS loop is relocked to the input signal.
During the time period the loop is not locked, the DCS loop is
bypassed, and the internal device timing is dependent on the
duty cycle of the input clock signal. In such an application, it
may be appropriate to disable the duty cycle stabilizer. In all
other applications, enabling the DCS circuit is recommended
to maximize ac performance.

Rev. 0 | Page 18 of 40
 AD9254
The DCS can be enabled or disabled by setting the SDIO/DCS POWER DISSIPATION AND STANDBY MODE
pin when operating in the external pin mode (see Table 10), or The power dissipated by the AD9254 is proportional to its sample
via the SPI, as described in Table 13. rate (see Figure 47). The digital power dissipation is determined
Table 10. Mode Selection (External Pin Mode) primarily by the strength of the digital drivers and the load on each
Voltage at Pin SCLK/DFS SDIO/DCS output bit. Maximum DRVDD current (IDRVDD) can be calculated as
AGND Binary (default) DCS disabled fCLK
I DRVDD = VDRVDD × CLOAD × ×N
AVDD Twos complement DCS enabled 2
(default)
where N is the number of output bits, 14 in the AD9254.
JITTER CONSIDERATIONS
This maximum current occurs when every output bit switches
High speed, high resolution ADCs are sensitive to the quality of
on every clock cycle, that is, a full-scale square wave at the
the clock input. The degradation in SNR at a given input
Nyquist frequency, fCLK/2. In practice, the DRVDD current is
frequency (fIN) due to jitter (tJ) is calculated as follows:
established by the average number of output bits switching,
SNR = −20 log (2π × fIN × tJ) which is determined by the sample rate and the characteristics
of the analog input signal. Reducing the capacitive load
In the equation, the rms aperture jitter represents the root mean
presented to the output drivers can minimize digital power
square of all jitter sources, which include the clock input, analog
consumption. The data in Figure 47 was taken under the same
input signal, and ADC aperture jitter specification. IF under-
operating conditions as the data for the Typical Performance
sampling applications are particularly sensitive to jitter, as
Characteristics section, with a 5 pF load on each output driver.
shown in Figure 46.
500 300
75
480
0.05ps 250
70 460
MEASURED I (AVDD)
PERFORMANCE 440
65 0.20ps 200

CURRENT (mA)
POWER (mW)

420
SNR (dBc)

60 400 150
0.5ps POWER
380
55
100
360
1.0ps
50
1.50ps 340
50
2.00ps 320
45 I (DRVDD)
2.50ps
3.00ps 300 0

06216-051
40 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
06216-050

1 10 100 1000 CLOCK FREQUENCY (MHz)

INPUT FREQUENCY (MHz)
Figure 46. SNR vs. Input Frequency and Jitter
Treat the clock input as an analog signal in cases where aperture
jitter can affect the dynamic range of the AD9254. Power supplies
for clock drivers should be separated from the ADC output
driver supplies to avoid modulating the clock signal with digital
noise. The power supplies should also not be shared with analog
input circuits, such as buffers, to avoid the clock modulating onto
the input signal or vice versa. Low jitter, crystal-controlled oscil-
lators make the best clock sources. If the clock is generated from
another type of source (by gating, dividing, or other methods),
it should be retimed by the original clock at the last step.
Refer to Application Notes AN-501, Aperture Uncertainty and
ADC System Performance; and AN-756, Sampled Systems and
the Effects of Clock Phase Noise and Jitter, for more in-depth
information about jitter performance as it relates to ADCs.
Figure 47. AD9254 Power and Current vs. Clock Frequency fIN = 30 MHz
Power-Down Mode
By asserting the PDWN pin high, the AD9254 is placed in power-
down mode. In this state, the ADC typically dissipates 1.8 mW.
During power-down, the output drivers are placed in a high
impedance state. Reasserting the PDWN pin low returns the
AD9254 to its normal operational mode. This pin is both 1.8 V
and 3.3 V tolerant.
Low power dissipation in power-down mode is achieved by
shutting down the reference, reference buffer, biasing networks,
and clock. The decoupling capacitors on REFT and REFB are
discharged when entering power-down mode and then must be
recharged when returning to normal operation. As a result, the
wake-up time is related to the time spent in power-down mode;
and shorter power-down cycles result in proportionally shorter
wake-up times. With the recommended 0.1 μF decoupling capaci-
tors on REFT and REFB, it takes approximately 0.25 ms to fully
discharge the reference buffer decoupling capacitors and 0.35 ms to
restore full operation.

Rev. 0 | Page 19 of 40
AD9254
Standby Mode By logically AND’ing the OR bit with the MSB and its complement,
When using the SPI port interface, the user can place the ADC overrange high or underrange low conditions can be detected.
in power-down or standby modes. Standby mode allows the Table 11 is a truth table for the overrange/underrange circuit in
user to keep the internal reference circuitry powered when Figure 49, which uses NAND gates.
faster wake-up times are required (see the Memory Map section). MSB
OVER = 1

DIGITAL OUTPUTS OR

06216-053
UNDER = 1
The AD9254 output drivers can be configured to interface with MSB

1.8 V to 3.3 V logic families by matching DRVDD to the digital Figure 49. Overrange/Underrange Logic
supply of the interfaced logic. The output drivers are sized to
Table 11. Overrange/Underrange Truth Table
provide sufficient output current to drive a wide variety of logic
OR MSB Analog Input Is:
families. However, large drive currents tend to cause current
0 0 Within range
glitches on the supplies that may affect converter performance.
0 1 Within range
Applications requiring the ADC to drive large capacitive loads
1 0 Underrange
or large fan-outs may require external buffers or latches.
1 1 Overrange
The output data format can be selected for either offset binary Digital Output Enable Function (OEB)
or twos complement by setting the SCLK/DFS pin when operat-
The AD9254 has three-state ability. If the OEB pin is low, the
ing in the external pin mode (see Table 10). As detailed in the
output data drivers are enabled. If the OEB pin is high, the
Interfacing to High Speed ADCs via SPI user manual, the data
output data drivers are placed in a high impedance state. This is
format can be selected for either offset binary, twos complement,
or Gray code when using the SPI control. not intended for rapid access to the data bus. Note that OEB is
referenced to the digital supplies (DRVDD) and should not
Out-of-Range (OR) Condition exceed that supply voltage.
An out-of-range condition exists when the analog input voltage
TIMING
is beyond the input range of the ADC. OR is a digital output
that is updated along with the data output corresponding to the The lowest typical conversion rate of the AD9254 is 10 MSPS.
particular sampled input voltage. Thus, OR has the same At clock rates below 10 MSPS, dynamic performance can degrade.
pipeline latency as the digital data. The AD9254 provides latched data outputs with a pipeline delay
OR DATA OUTPUTS
+FS – 1 LSB of twelve clock cycles. Data outputs are available one propaga-
1 11 1111 1111 1111 OR tion delay (tPD) after the rising edge of the clock signal.
0 11 1111 1111 1111
0 11 1111 1111 1110
–FS + 1/2 LSB The length of the output data lines and the loads placed on
them should be minimized to reduce transients within the
0 00 0000 0000 0001
0 00 0000 0000 0000 AD9254. These transients can degrade the dynamic performance
1 00 0000 0000 0000 of the converter.
06216-052

–FS +FS
–FS – 1/2 LSB +FS – 1/2 LSB Data Clock Output (DCO)
Figure 48. OR Relation to Input Voltage and Output Data The AD9254 also provides data clock output (DCO) intended for
capturing the data in an external register. The data outputs are valid
OR is low when the analog input voltage is within the analog
on the rising edge of DCO, unless the DCO clock polarity has been
input range and high when the analog input voltage exceeds the
changed via the SPI. See Figure 2 for a graphical timing
input range, as shown in Figure 48. OR remains high until the
description.
analog input returns to within the input range and another
conversion is completed.
Table 12. Output Data Format
Gray Code Mode
Input (V) Condition (V) Binary Output Mode Twos Complement Mode (SPI Accessible) OR
VIN+ – VIN– < –VREF – 0.5 LSB 00 0000 0000 0000 10 0000 0000 0000 11 0000 0000 0000 1
VIN+ – VIN– = –VREF 00 0000 0000 0000 10 0000 0000 0000 11 0000 0000 0000 0
VIN+ – VIN– =0 10 0000 0000 0000 00 0000 0000 0000 00 0000 0000 0000 0
VIN+ – VIN– = +VREF – 1.0 LSB 11 1111 1111 1111 01 1111 1111 1111 10 0000 0000 0000 0
VIN+ – VIN– > +VREF – 0.5 LSB 11 1111 1111 1111 01 1111 1111 1111 10 0000 0000 0000 1

Rev. 0 | Page 20 of 40

SERIAL PORT INTERFACE (SPI)
The AD9254 serial port interface (SPI) allows the user to
configure the converter for specific functions or operations
through a structured register space provided inside the ADC.
This provides the user added flexibility and customization
depending on the application. Addresses are accessed via the
serial port and may be written to or read from via the port.
Memory is organized into bytes that are further divided into
fields, as documented in the Memory Map section. For detailed
operational information, see the Interfacing to High Speed ADCs
via SPI user manual.
CONFIGURATION USING THE SPI
As summarized in Table 13, three pins define the SPI of this
ADC. The SCLK/DFS pin synchronizes the read and write data
presented to the ADC. The SDIO/DCS dual-purpose pin allows
data to be sent to and read from the internal ADC memory map
registers. The CSB pin is an active low control that enables or
disables the read and write cycles.
Table 13. Serial Port Interface Pins
Pin Name Function
SCLK/DFS SCLK (serial clock) is the serial shift clock in. SCLK
synchronizes serial interface reads and writes.
SDIO/DCS SDIO (serial data input/output) is a dual-purpose
pin. The typical role for this pin is an input and
output, depending on the instruction being sent
and the relative position in the timing frame.
CSB CSB (chip select bar) is an active-low control that
gates the read and write cycles.
The falling edge of the CSB in conjunction with the rising edge
of the SCLK determines the start of the framing. Figure 50 and
Table 14 provide examples of the serial timing and its definitions.
Other modes involving the CSB are available. The CSB can be
held low indefinitely to permanently enable the device (this is
called streaming). The CSB can stall high between bytes to
allow for additional external timing. When CSB is tied high, SPI
functions are placed in a high impedance mode. This mode
turns on any SPI pin secondary functions.
During an instruction phase, a 16-bit instruction is transmitted.
Data follows the instruction phase and the length is determined
by the W0 bit and the W1 bit. All data is composed of 8-bit
words. The first bit of each individual byte of serial data
indicates whether a read or write command is issued. This
allows the serial data input/output (SDIO) pin to change
direction from an input to an output.
Rev. 0 | Page 21 of 40
AD9254
In addition to word length, the instruction phase determines if
the serial frame is a read or write operation, allowing the serial
port to be used to both program the chip as well as read the
contents of the on-chip memory. If the instruction is a readback
operation, performing a readback causes the serial data
input/output (SDIO) pin to change direction from an input to
an output at the appropriate point in the serial frame.
Data can be sent in MSB- or in LSB-first mode. MSB first is the
default on power-up and can be changed via the configuration
register. For more information, see the Interfacing to High Speed
ADCs via SPI user manual.
Table 14. SPI Timing Diagram Specifications
Name Description
tDS Setup time between data and rising edge of SCLK
tDH Hold time between data and rising edge of SCLK
tCLK Period of the clock
tS Setup time between CSB and SCLK
tH Hold time between CSB and SCLK
tHI Minimum period that SCLK should be in a logic
high state
tLO Minimum period that SCLK should be in a logic
low state
HARDWARE INTERFACE
The pins described in Table 13 comprise the physical interface
between the user’s programming device and the serial port of
the AD9254. The SCLK and CSB pins function as inputs when
using the SPI interface. The SDIO pin is bidirectional, functioning
as an input during write phases and as an output during readback.
The SPI interface is flexible enough to be controlled by either
PROM or PIC microcontrollers. This provides the user with the
ability to use an alternate method to program the ADC. One
method is described in detail in Application Note AN-812,
Microcontroller-Based Serial Port Interface Boot Circuit.
When the SPI interface is not used, some pins serve a dual
function. When strapped to AVDD or ground during device
power on, the pins are associated with a specific function.
CONFIGURATION WITHOUT THE SPI
In applications that do not interface to the SPI control registers,
the SDIO/DCS and SCLK/DFS pins serve as stand-alone
CMOS-compatible control pins. When the device is powered
up, it is assumed that the user intends to use the pins as static
control lines for the output data format and duty cycle stabilizer
(see Table 10). In this mode, the CSB chip select should be
connected to AVDD, which disables the serial port interface.
For more information, see the Interfacing to High Speed ADCs
via SPI user manual.
AD9254
Default Values
MEMORY MAP Coming out of reset, critical registers are loaded with default
READING THE MEMORY MAP REGISTER TABLE values. The default values for the registers are shown in
Each row in the memory map register table has eight address Table 15.
locations. The memory map is roughly divided into three
Logic Levels
sections: the chip configuration registers map (Address 0x00 to
Address 0x02), the device index and transfer registers map An explanation of two registers follows:
(Address 0xFF), and the ADC functions map (Address 0x08 to
• “Bit is set” is synonymous with “Bit is set to Logic 1” or
Address 0x18).
“Writing Logic 1 for the bit.”
Table 15 displays the register address number in hexadecimal in
the first column. The last column displays the default value for • “Clear a bit” is synonymous with “Bit is set to Logic 0” or
“Writing Logic 0 for the bit.”
each hexadecimal address. The Bit 7 (MSB) column is the start
of the default hexadecimal value given. For example, SPI-Accessible Features
Hexadecimal Address 0x14, output_phase, has a hexadecimal
A list of features accessible via the SPI and a brief description of
default value of 0x00. This means Bit 3 = 0, Bit 2 = 0, Bit 1 = 1,
what the user can do with these features follows. These features
and Bit 0 = 1 or 0011 in binary. This setting is the default output
are described in detail in the Interfacing to High Speed ADCs via
clock or DCO phase adjust option. The default value adjusts the
SPI user manual.
DCO phase 90° relative to the nominal DCO edge and 180°
relative to the data edge. For more information on this function, • Modes: Set either power-down or standby mode.
consult the Interfacing to High Speed ADCs via SPI user manual.
• Clock: Access the DCS via the SPI.
Open Locations
Locations marked as open are currently not supported for this • Offset: Digitally adjust the converter offset.
device. When required, these locations should be written with
• Test I/O: Set test modes to have known data on output bits.
0s. Writing to these locations is required only when part of an
address location is open (for example, Address 0x14). If the • Output Mode: Setup outputs, vary the strength of the
entire address location is open (Address 0x13), then the address output drivers.
location does not need to be written.
• Output Phase: Set the output clock polarity.

• VREF: Set the reference voltage.

tDS tHI tCLK tH

tS tDH tLO
CSB

SCLK DON’T CARE DON’T CARE

SDIO DON’T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 D5 D4 D3 D2 D1 D0 DON’T CARE

06216-054

Figure 50. Serial Port Interface Timing Diagram

Rev. 0 | Page 22 of 40
 AD9254
MEMORY MAP REGISTER TABLE
Table 15. Memory Map Register
Default
Addr. Bit 7 Bit 0 Value Default Notes/
(Hex) Parameter Name (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) (Hex) Comments
Chip Configuration Registers
00 chip_port_config 0 LSB first Soft 1 1 Soft LSB first 0 0x18 The nibbles
0 = Off reset reset 0 = Off should be
(Default) 0 = Off 0 = Off (Default) mirrored. See
(Default) (Default) the Interfacing to
1 = On 1 = On
High Speed ADCs
1 = On 1 = On
via SPI user
manual.
01 chip_id 8-bit Chip ID Bits 7:0 Read Default is unique
(AD9254 = 0x00), (default) only chip ID, different
for each device.
02 chip_grade Open Open Open Open Child ID Open Open Open Read Child ID used to
0 = 150 only differentiate
MSPS speed grades.
Device Index and Transfer Registers
FF device_update Open Open Open Open Open Open Open SW 0x00 Synchronously
transfer transfers data
from the master
shift register to
the slave.
Global ADC Functions
08 modes Open Open PDWN Open Open Internal power-down mode 0x00 Determines
0—Full 000—normal (power-up) various generic
001—full power-down modes of chip
1—
Standby 010—standby operation. See
011—normal (power-up) the Power
Note: External PDWN pin Dissipation and
overrides this setting. Standby Mode
and the SPI-
Accessible
Features
sections.
09 clock Open Open Open Open Open Open Open Duty 0x01 See the Clock
cycle Duty Cycle
stabilizer section and the
0— SPI-Accessible
disabled
Features section.
1—
enabled

Rev. 0 | Page 23 of 40
AD9254

Default Default
Addr. Bit 7 Bit 0 Value Notes/
(Hex) Parameter Name (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) (Hex) Comments
Flexible ADC Functions
10 offset Digital Offset Adjust<5:0> Offset in LSBs 0x00 Adjustable for
011111 +31 offset inherent
011110 +30 in the
011101 +29 converter. See
… SPI-
000010 +2 Accessible
000001 +1 Features
000000 0 (Default) section.
111111 1
111110 −2
111101 −3
...
100001 −31
100000 −32
0D test_io PN23 PN9 Global Output Test Options 0x00 See the
0 = normal 0 = normal 000—off Interfacing to
(Default) (Default) 001—midscale short High Speed
1 = reset 1 = reset 010—+FS short ADCs via SPI
user manual.
011—−FS short
100—checker board output
101—PN 23 sequence
110—PN 9
111—one/zero word toggle
14 output_mode Output Driver Open Output Open Output Data Format Select 0x00 Configures the
Configuration Disable Data 00—offset binary outputs and
00 for DRVDD = 2.5 V to 1— Invert (default) the format of
3.3 V disabled 1= 01—twos the data.
0— invert complement
10 for DRVDD = 1.8 V
enabled 1 10—Gray Code
16 output_phase Output Clock Open Open Open Open Open Open Open 0x00 See the SPI-
Polarity Accessible
1 = inverted Features
0 = normal section.
(Default)
18 VREF Internal Reference Open Open Open Open Open Open 0xC0 See the SPI-
Resistor Divider Accessible
00—VREF = 1.25 V Features
01—VREF = 1.5 V section.
10—VREF = 1.75 V
11—VREF = 2.00 V
(Default)
1
External output enable (OEB) pin must be high.

Rev. 0 | Page 24 of 40
 AD9254

LAYOUT CONSIDERATIONS
SILKSCREEN PARTITION
POWER AND GROUND RECOMMENDATIONS PIN 1 INDICATOR

When connecting power to the AD9254, it is recommended

that two separate supplies be used: one for analog (AVDD, 1.8 V
nominal) and one for digital (DRVDD, 1.8 V to 3.3 V nominal).
If only a single 1.8 V supply is available, it is routed to AVDD

06216-055
first, then tapped off and isolated with a ferrite bead or filter
choke with decoupling capacitors proceeding connection to
Figure 51. Typical PCB Layout
DRVDD. The user can employ several different decoupling
capacitors to cover both high and low frequencies. These should CML
be located close to the point of entry at the PC board level and
The CML pin should be decoupled to ground with a 0.1 μF
close to the parts with minimal trace length.
capacitor, as shown in Figure 33.
A single PC board ground plane is sufficient when using the
AD9254. With proper decoupling and smart partitioning of
RBIAS
analog, digital, and clock sections of the PC board, optimum The AD9254 requires the user to place a 10 kΩ resistor between
performance is easily achieved. the RBIAS pin and ground. This resister sets the master current
reference of the ADC core and should have at least a 1% tolerance.
Exposed Paddle Thermal Heat Slug Recommendations
It is required that the exposed paddle on the underside of the REFERENCE DECOUPLING
ADC be connected to analog ground (AGND) to achieve the The VREF pin should be externally decoupled to ground with a
best electrical and thermal performance of the AD9254. An low ESR 1.0 μF capacitor in parallel with a 0.1 μF ceramic low
exposed, continuous copper plane on the PCB should mate to ESR capacitor. In all reference configurations, REFT and REFB
the AD9254 exposed paddle, Pin 0. The copper plane should are bypass points provided for reducing the noise contributed
have several vias to achieve the lowest possible resistive thermal by the internal reference buffer. It is recommended that an
path for heat dissipation to flow through the bottom of the PCB. external 0.1 μF ceramic capacitor be placed across REFT/REFB.
These vias should be solder-filled or plugged. While placement of this 0.1 μF capacitor is not required, the SNR
performance degrades by approximately 0.1 dB without it. All
To maximize the coverage and adhesion between the ADC and reference decoupling capacitors should be placed as close to the
PCB, partition the continuous plane by overlaying a silkscreen ADC as possible with minimal trace lengths.
on the PCB into several uniform sections. This provides several
tie points between the two during the reflow process. Using one
continuous plane with no partitions guarantees only one tie point
between the ADC and PCB. See Figure 51 for a PCB layout
example. For detailed information on packaging and the PCB
layout of chip scale packages, see Application Note AN-772,
A Design and Manufacturing Guide for the Lead Frame Chip
Scale Package.

Rev. 0 | Page 25 of 40
AD9254

EVALUATION BOARD
The AD9254 evaluation board provides all of the support circuitry
required to operate the ADC in its various modes and configu-
rations. The converter can be driven differentially through a double
balun configuration (default) or through the AD8352 differential
driver. The ADC can also be driven in a single-ended fashion.
Separate power pins are provided to isolate the DUT from the
AD8352 drive circuitry. Each input configuration can be selected
by proper connection of various components (see Figure 53 to
Figure 63). Figure 52 shows the typical bench characterization
setup used to evaluate the ac performance of the AD9254.
It is critical that the signal sources used for the analog input and
clock have very low phase noise (<1 ps rms jitter) to realize the
optimum performance of the converter. Proper filtering of the
analog input signal to remove harmonics and lower the integrated
or broadband noise at the input is also necessary to achieve the
specified noise performance.
See Figure 53 to Figure 57 for the complete schematics and
layout diagrams that demonstrate the routing and grounding
techniques that should be applied at the system level.
POWER SUPPLIES
This evaluation board comes with a wall-mountable switching
power supply that provides a 6 V, 2 A maximum output.
Connect the supply to the rated 100 V ac to 240 V ac wall outlet
at 47 Hz to 63 Hz. The other end is a 2.1 mm inner diameter
jack that connects to the PCB at P500. Once on the PC board,
the 6 V supply is fused and conditioned before connecting to
five low dropout linear regulators that supply the proper bias to
each of the various sections on the board.
When operating the evaluation board in a nondefault condition,
L501, L503, L504, L508, and L509 can be removed to disconnect
the switching power supply. This enables the user to individually
bias each section of the board. Use P501 to connect a different
supply for each section. At least one 1.8 V supply is needed with
a 1 A current capability for AVDD_DUT and DRVDD_DUT;
however, it is recommended that separate supplies be used for
analog and digital. To operate the evaluation board using the
AD8352 option, a separate 5.0 V supply (AMP_VDD) with a
1 A current capability is needed. To operate the evaluation
board using the alternate SPI options, a separate 3.3 V analog
supply is needed, in addition to the other supplies. The 3.3 V
supply (AVDD_3.3V) should have a 1 A current capability as
well. Solder Jumpers J501, J502, and J505 allow the user to
combine these supplies (see Figure 57 for more details).
INPUT SIGNALS
When connecting the clock and analog source, use clean signal
generators with low phase noise, such as Rohde & Schwarz SMHU
or Agilent HP8644 signal generators or the equivalent. Use one
meter long, shielded, RG-58, 50 Ω coaxial cable for making
connections to the evaluation board. Enter the desired frequency
and amplitude for the ADC. Typically, most evaluation boards
from Analog Devices, Inc. can accept a ~2.8 V p-p or 13 dBm
sine wave input for the clock. When connecting the analog
input source, it is recommended to use a multipole, narrow-
band, band-pass filter with 50 Ω terminations. Analog Devices
uses TTE®, Allen Avionics, and K&L® types of band-pass filters.
Connect the filter directly to the evaluation board, if possible.
OUTPUT SIGNALS
The parallel CMOS outputs interface directly with the Analog
Devices standard single-channel FIFO data capture board
(HSC-ADC-EVALB-SC). For more information on the FIFO
boards and their optional settings, visit www.analog.com/FIFO.

WALL OUTLET
100V TO 240V AC
47Hz TO 63Hz
6V DC
2A MAX
5.0V 1.8V 2.5V 3.3V 3.3V 3.3V
– + – + – + – + – + – +
SWITCHING
POWER
SUPPLY
VDL

GND

VCC
GND

GND

GND

GND

GND
AMP_VDD

AVDD_3.3V
AVDD_DUT

DRVDD_DUT

PC
RUNNING
ROHDE & SCHWARZ, ADC
SMHU, HSC-ADC-EVALB-SC ANALYZER
BAND-PASS FIFO DATA AND SPI
2V p-p SIGNAL AIN
FILTER AD9254 CAPTURE USER
SYNTHESIZER
EVALUATION BOARD 14-BIT BOARD SOFTWARE
ROHDE & SCHWARZ, PARALLEL USB
SMHU, CLK CMOS CONNECTION
06216-056

2V p-p SIGNAL
SYNTHESIZER SPI SPI SPI

Figure 52. Evaluation Board Connection

Rev. 0 | Page 26 of 40

DEFAULT OPERATION AND JUMPER SELECTION
SETTINGS
The following is a list of the default and optional settings or
modes allowed on the AD9254 Rev. A evaluation board.
POWER
Connect the switching power supply that is supplied in the
evaluation kit between a rated 100 V ac to 240 V ac wall outlet
at 47 Hz to 63 Hz and P500.
VIN
The evaluation board is set up for a double balun configuration
analog input with optimum 50 Ω impedance matching out to
70 MHz. For more bandwidth response, the differential capacitor
across the analog inputs can be changed or removed (see Table 8).
The common mode of the analog inputs is developed from the
center tap of the transformer via the CML pin of the ADC (see
the Analog Input Considerations section).
VREF
VREF is set to 1.0 V by tying the SENSE pin to ground via
JP507 (Pin 1 and Pin 2). This causes the ADC to operate in
2.0 V p-p full-scale range. A separate external reference option
is also included on the evaluation board. Connect JP507
between Pin 2 and Pin 3, connect JP501, and provide an external
reference at E500. Proper use of the VREF options is detailed
in the Voltage Reference section.
RBIAS
RBIAS requires a 10 kΩ resistor (R503) to ground and is used to
set the ADC core bias current.
CLOCK
The default clock input circuitry is derived from a simple
transformer-coupled circuit using a high bandwidth 1:1
impedance ratio transformer (T503) that adds a very low amount
of jitter to the clock path. The clock input is 50 Ω terminated
and ac-coupled to handle single-ended sine wave inputs. The
transformer converts the single-ended input to a differential
signal that is clipped before entering the ADC clock inputs.
PDWN
To enable the power-down feature, connect JP506, shorting the
PDWN pin to AVDD.
CSB
The CSB pin is internally pulled-up, setting the chip into
external pin mode, to ignore the SDIO and SCLK information.
To connect the control of the CSB pin to the SPI circuitry on the
evaluation board, connect JP1 Pin 1 and Pin 2. To set the chip
into serial pin mode, and enable the SPI information on the
SDIO and SCLK pins, tie JP1 low (connect Pin 2 and Pin 3) in
the always enabled mode.
Rev. 0 | Page 27 of 40
AD9254
SCLK/DFS
If the SPI port is in external pin mode, the SCLK/DFS pin sets the
data format of the outputs. If the pin is left floating, the pin is
internally pulled down, setting the default condition to binary.
Connecting JP2 Pin 2 and Pin 3 sets the format to twos comple-
ment. If the SPI port is in serial pin mode, connecting JP2 Pin 1
and Pin 2 connects the SCLK pin to the on-board SPI circuitry
(see the Serial Port Interface (SPI) section).
SDIO/DCS
If the SPI port is in external pin mode, the SDIO/DCS pin acts
to set the duty cycle stabilizer. If the pin is left floating, the pin is
internally pulled up, setting the default condition to DCS enabled.
To disable the DCS, connect JP3 Pin 2 and Pin 3. If the SPI port
is in serial pin mode, connecting JP3 Pin 1 and Pin 2 connects the
SDIO pin to the on-board SPI circuitry (see the Serial Port
Interface (SPI) section).
ALTERNATIVE CLOCK CONFIGURATIONS
A differential LVPECL clock can also be used to clock the ADC
input using the AD9515 (U500). When using this drive option,
the components listed in Table 16 need to be populated. Consult
the AD9515 data sheet for further information.
To configure the analog input to drive the AD9515 instead of
the default transformer option, the following components need
to be added, removed, and/or changed.
1. Remove R507, R508, C532, and C533 in the default clock
path.
2. Populate R505 with a 0 Ω resistor and C531 in the default
clock path.
3. Populate R511, R512, R513, R515 to R524, U500, R580,
R582, R583, R584, C536, C537, and R586.
If using an oscillator, two oscillator footprint options are also
available (OSC500) to check the performance of the ADC.
JP508 provides the user flexibility in using the enable pin, which
is common on most oscillators. Populate OSC500, R575, R587,
and R588 to use this option.
ALTERNATIVE ANALOG INPUT DRIVE
CONFIGURATION
This section provides a brief description of the alternative
analog input drive configuration using the AD8352. When
using this particular drive option, some components need to be
populated, as listed in Table 16. For more details on the AD8352
differential driver, including how it works and its optional pin
settings, consult the AD8352 data sheet.
AD9254
To configure the analog input to drive the AD8352 instead of Note that to terminate the input path, only one of the
the default transformer option, the following components need following components should be populated: R9, R592, or
to be added, removed, and/or changed: the combination of R590 and R591).

1. Remove C1 and C2 in the default analog input path. 4. Populate C529 with a 5 pF capacitor in the analog input
path.
2. Populate R3 and R4 with 200 Ω resistors in the analog
input path. Currently, R561 and R562 are populated with 0 Ω resistors to
allow signal connection. This area allows the user to design a
3. Populate the optional amplifier input path with all filter if additional requirements are necessary.
components except R594, R595, and C502.

Rev. 0 | Page 28 of 40
 SCHEMATICS

DOUBLE BALUN / XFMR INPUT

C1 AMPOUT+ R561 R566

.1UF 0 33

RC0402 RC0402
VIN+
S500 R560 C528
0.1UF

RC040 2
SMAEDGE 0
R3
1 2 5 T500 1 T501 25

RC0402
RC0402
RC0402

R571
Ain RC0603

CC0402
1 5 0
R2 2 R565 R574 R563
GND;3,4,5 0 P S S P DNI RC0402 CML DNI DNI CC0402 C529
4 3 2 20PF
RC0402

RC040 2
R502 ETC1-1-13 3 ETC1-1-13 4 C510
50 R4 .1UF
C2 25 R562 R567
DNI 0
.1UF 33
R1

RC060 3
DNI RC0402 RC0402
VIN-
T502 CML
DNI RC0402
AMPOUT-
R6 1 6
DNI

RC0402
S503 R7 C3
DNI 2 5 R5 When using R1, remove R3, R4,R6.
SMAEDGE DNI CML RC0402
0
1 2 3 4
Replace R5 with 0.1UF cap VIN+ VIN-
RC0603 Replace C1, C2 with 0 ohm resistors.

CC0402
Ain/
GND;3,4,5 D500 D501
C509 DNI
.1UF 3 DNI 3
R8
DNI
When using T502, remove T500, T501.
HSMS281 2
HSMS281 2

Repalce C1, C2 with 0 ohm resistors. 1 2 1 2

RC060 3
Remove R3, R4. Place R6, R502,. OPTIONAL AMP INPUT
R594 DUTAVDD DUTAVDD
10K
DNI
AMPVDD

disable
J500 C502
R595 .1UF
1 3

Rev. 0 | Page 29 of 40
C4 10K DNI
S504 R10 AMPVDD DNI
SMA200UP
0 C500 2
0 DNI DNI .1UF R593 enable
DNI 0
1 2 DNI
Ampin RC0603

CC0402
DNI GND;3,4,5 16 15 14 13 R535 0 DNI
VIP ENB VCC
R9 1 VCM 12
AMPOUT+
R591 RC0402
DNI GND
25 RDP C504
DNI .1UF
5 T1 1 2 11 DNI
VOP

RC060 3
C501 RGP
2 R592 R597 R598
P S 0.3PF U511

Figure 53. Evaluation Board Schematic, DUT Analog Inputs

DNI 4.3K 100
RGN
4 3 DNI DNI DNI 3 VON 10
R590 AD8352
25 RDN DNI R536 0 DNI
DNI DNI 4 9
SIGNAL=GND;17 GND
VIN GND VCC
AMPOUT-
RC0402

S505 R12 C5 5 6 7 8 C505

SMA200UP 0 DNI 0 DNI .1UF
DNI
1 2 R596
RC0603 C503 0

CC0402
Ampin/ .1UF DNI
GND;3,4,5 DNI AMPVDD
DNI
R11
0
DNI
For amplifier (AD8352):
Install all optional Amp input components.
R590/R591,R9,R592 Only one should be installed at a time.

RC060 3
Remove C1, C2.
06216-057
Set R3=R4=200 OHM.
AD9254
 AD9254

DUT 25 24
SENSE SENSE AVDD DUTAVDD
26 23 JP1
VREF VREF AGND 1 3
27 22 CSB_DUT
REFB AVDD DUTAVDD
2
C554 28 21 JP2
CC0402 0.1UF REFT AGND 1 3
SCLK_DTP JP3
29 20 1 3
AGND CSB 2
SDIO_ODM
30 19 2
VIN+ VIN+ SCLK/DFS
31 18
VIN- VIN- SDIO/DCS
32 17
AGND DRVDD DUTDRVDD
33 16
AVDD DRGND
34 15 DOR
CML CML OR TP503
35 14 D13
RBIAS D13 (MSB) TP501
36 13
R503 PDWN D12 D12
C556
0.1UF 10K
CC0603 JP506 chip corners
DNI
VDL
37 12
AGND D11 D11

RC060 3
38 11
CLK CLK+ D10 D10
39 EPAD 10 A1 B1 C1
CLK CLK- D9 D9
OE3 74VCX16224 OE4 FIFOCLK A2 B2 SDI_CHA C2
40 9 25 24
DUTAVDD AVDD D8 D8 RP502 22 RP502 22
41 8 DOR I15 O15 FDOR A3 B3 C3
9 8 10 7 26 23
AGND DRVDD RP502 22
JP502 D13 I14 O14 FD13 FD13 A4 B4 C4
42 7 11 6 27 22
DNI AVDD DRGND U509
GND5 GND4 FD12 A5 B5 C5
43 6 28 21
OEB D7 D7 RP502 22
D12 O13 FD12 FD11 A6 B6 CSB1_CHA C6
DCO 44 5 12 5 I13
TP504 DCO D6 D6 RP502 22 29 20
D11 I12 O12 FD11 FD10 A7 B7 C7
D0 45 4 13 4 30 19
TP500 D0 (LSB) D5 D5
VCC3 VCC2 FD9 A8 B8 SDO_CHA C8
46 U510 3 31 18
D1 D1 D4 D4 RP502 22
D10 I11 O11 FD10 FD8 A9 B9 C9
47 2 14 3 32 17
DRGND D3 D3 RP502 22
D9 I10 O10 FD9 FD7 A10 B10 SCLK_CHA C10
48 1 D2 15 2 33 16
DUTDRVDD DRVDD D2 TP502
GND6 GND3 FD6 A11 B11 C11
RP502 22 34 15
D8 I9 O9 FD8 FD5 A12 B12 C12
16 1 35 14
AD9246LFCSP RP501 22 RP501 22
D7 I8 O8 FD7 FD4 A13 B13 C13

Rev. 0 | Page 30 of 40
9 8 11 6 36 13
RP501 22 RP501 22
D6 I7 O7 FD6 FD3 A14 B14 C14
10 7 12 5 37 12
RP501 22
D5 I6 O6 FD5 FD2 A15 B15 C15
13 4 38 11
GND7 GND2 FD1 A16 B16 C16
RP501 22 39 10
JP507 D4 I5 O5 FD4 FD0 A17 B17 C17
3 1 14 3 40 9
E500 DUTAVDD RP501 22
D3 I4 O4 FD3 FDOR A18 B18 C18
2 15 2 41 8
JP501 JP500 VCC4 VCC1 A19 B19 C19
RP501 22 42 7
E X T _V RE F SEN SE
D2 I3 O3 FD2 A20 B20 C20
DNI DNI 16 1 43 6
R500 RP500 22
D1 I2 O2 FD1
DNI 5 4 44 5 J503 J503 J503
R0402
GND8 GND1
RP500 22 45 4
VREF
D0 I1 O1 FD0
6 3 46 3
R501 RP500 22 RP500 22 OUTPUT CONNECTOR
C553 DCO I0 O0 FIFOCLK
CC0402 C555 CC0805 DNI 8 1 7 2

Figure 54. Evaluation Board Schematic, DUT, VREF, and Digital Output Interface
0.1UF 1.0UF 47 2
R0402
OE2 OE1
48 1

OUTPUT BUFFER

06216-058
 AVDD_3P3V
R587 10K DNI JP508 DISABLE
XFMR/AD9515 RC0402
DNI 3 ENABLE 1

Clock Circuitry 2
OSC500 DNI

RC0402
14 1
AD9515 LOGIC SETUP
VCC OE R588
AVDD_3P3V R514 0
R575 10K
12 VCC 3 DNI R513 0
0 OE DNI DNI
DNI
10 5 RC0603 RC0603
OUT GND
S0
8 7
OUT GND
RC0402
CB3LV-3C R525 0
DNI R515 0
C530 DNI
0.1UF R508 C533
OPT_CLK R506 0.1UF RC0603 RC0603
SMAEDGE 0 0
S501 T503 S1
RC0603
1 6 RC0603 CLK

CC0402
CC0402
CLK 3 R527 0
DNI R517 0
GND;3,4,5 D502 DNI
C531 R507
2 5 HSMS2812 RC0603 RC0603
0.1UF 0 C532
DNI OPT_CLK R509 0.1UF S2
SMAEDGE DNI 0 2
S502 1
RC0603
3 4 RC0603 CLK R526 0
DNI R516 0

CC0402
CC0402
CLK/ DNI
GND;3,4,5 RC0603 RC0603
C511
R512 .1UF S3
R505
R504 0
49.9
DNI 49.9 R531 0
DNI R521 0 DNI

RC060 3
RC0603 RC0603

RC060 3
RC060 3
S4
To use AD9515 (OPT _CLK), remove R507, R508, C533, C532. R530 0
DNI R520 0 DNI
Place C531,R505=0. RC0603 RC0603

S5

R528 0
DNI R518 0 DNI
AVDD_3P3V
RC0603 RC0603

S6
C536
0.1UF R529 0

RC0402
RC0402
DNI DNI

RC0402
R576 R519 0 DNI
DNI R581 R580
DNI 10K R586 CLK RC0603 RC0603

4.12K DNI
CC0402

DNI S7
R510
RC0402

Rev. 0 | Page 31 of 40
DNI RC0402 R534 0
R582
1 2 100 DNI R524 0
RC0603 DNI
OPT_CLK C537
DNI DNI

32
31
33
0.1UF RC0603 RC0603
U500

RC0402
23 DNI
2 OUT0 S8
CLK

GN D

RSET
3 22
R577 CLKB OUT0B CLK
R533 0

GND_PAD
DNI
CC0402

R511 AD9515 DNI R523 0

5 DNI
RC0402
RC0402

DNI SYNCB
1 2 AVDD_3P3V;1,4,17,20,21,24,26,29,30 R584 R583 RC0603 RC0603
RC0603 240
OPT_CLK 19 240
NC=27,28 OUT1 S9
DNI DNI
18
OUT1B

RC0402
RC0402
VREF
S0
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10

Figure 55. Evaluation Board Schematic, DUT Clock Input

R532 0
DNI

6
7
8
9
10
11
12
13
14
15
16
25
R579 R578 R522 0 DNI
DNI DNI
E501 RC0603 RC0603

S9
S8
S7
S6
S5
S4
S3
S2
S1
S0

S10

S10
E502
CC0402

RC0402

C534
R585 0.1UF
100 DNI
DNI

E503
CC0402

C535
0.1UF
DNI

06216-059
AD9254
 AD9254

SDI_CH A
SDO_CHA

CSB1_CHA

SCLK_CHA
REMOVE WHEN USING OR PROGRAMMING PIC (U506)

SPI CIRCUITRY +5V=PROGRAMMING ONLY=AMPVDD

+3.3V=NORMAL OPERATION=AVDD_3P3V

RC0603
RC0603
RC0603
RC0603
JP509
1 3
A VD D _3 P3V A M PVD D R555 R557 R556 R554
0 0 0 0
2 DNI

U506 DNI
DNI
S1 DNI 1 8
R558 VDD VSS
1 4.7K 2 7
3 GP5 GP0 R547 RC0603 DUTAVDD AVDD_3P3V
C557 CC0603 3 6 4.7K DNI
GP4 GP1 R545 RC0603

RC060 3
0.1UF SOIC8
4 5 4.7K DNI
MCLR GP2 R546 RC0603
RC0603
RC0603

DNI PIC12F629 4.7K DNI

R551 R553
1K 1K
1 2
RC0603

2 2 1
4 R559
D505 DNI
261
Optional
DNI
U508
E504
1 6
A1 Y1
2 5
GND VCC
RC0603

GP0
GP1
R550
3 4

9
MCLR-GP3 7
5
3
PICVCC 1
A2 Y2
10K

NC7WZ07

Rev. 0 | Page 32 of 40
PIC-HEADER J504 R552
HEADER UP MALE DNI 1K
AVDD_3P3V

8
6
4
2

10
RC0603

SDIO_ODM
RC0603

R549

GP0
GP1
10K

PICVCC
U507

Figure 56. Evaluation Board Schematic, SPI Circuitry

MCLR-GP3
1 6 SCLK_DTP
A1 Y1
2 5
GND VCC
3 4 CSB_DUT
A2 Y2
RC0603

When using PICSPI controlled port, populate R545, R546, R547. NC7WZ16
R548
When using PICSPI controlled port, remove R555, R556, R557. 10K
For FIFO controlled port, populate R555, R556, R557.

06216-060
 DUTAVDD=1.8V
DUTDRVDD=2.5V
D503 TP506 VDL=3.3V
Power Supply Input 3A
FER500 SHOT_RECT U502 L504 AMPVDD=5V
6V, 2A max F500 CHOKE_COIL DO-214AB ADP3339AKC-1.8 10UH AVDD_3.3V=3.3V
PWR_IN PWR_IN 3 2
IN P U T OU TP UT1 LC1210 DUTAVDDIN
4 3 4
OUTPUT4

1
P500 SMDC110F TP507
1
C519 C518
1UF 1UF U501 L501

GND

2
CR500
10UH

1
C527 D504 ADP3339AKC-5
10UF S2A_RECT PWR_IN 3 2
IN P U T O UTP UT 1 LC1210 AMPVDDIN
2 2A 4
OUTPUT4
3 DO-214AA
7.5V POWER R589 C523 C522
CON005
2.5MM JACK 1UF 1UF

GND
261 TP505

1
U503 L503
ADP3339AKC-2.5 10UH
3 2
PWR_IN IN P U T OU TP UT1 LC1210 DUTDRVDDIN
4
OUTPUT4 TP513
C521 C520
1UF 1UF U505 L509

GND
ADP3339AKC-3.3 10UH

1
3 2
PWR_IN IN P U T O UTP UT 1 LC1210 AVDD_3P3V
4
OUTPUT4
C525
C513
1UF
1UF
GND

TP508
1

OPTIONAL POWER CONNECTION L505 U504 L508

10UH ADP3339AKC-3.3 10UH
P501 3 2
1 AMPVDDIN PWR_IN IN P U T OU TP UT1 LC1210 VDLIN
P1 LC1210 AMPVDD 4
OUTPUT4
2 GND
P2 C524 C526
C549
ACASE 1UF 1UF

GND
3 DUTAVDDIN 1OUF C514

1
P3 J505 6.3V 0.1UF
4 GND
P4
5 DUTDRVDDIN
P5 L507
10UH
6 GND
P6
LC1210 VDL
7 VDLIN
P7
C550
8 GND ACASE 1OUF
P8 C515 AVDD_3P3V
6.3V 0.1UF
9 AVDD_3P3VIN
P9
AMPVDD
10 GND L502
P10 10UH

Rev. 0 | Page 33 of 40
C567 C568
LC1210 DUTAVDD CC0603 CC0603 C545 C544 C546 C543
0.1UF 0.1UF CC0402 CC0402 CC0402 CC0402
0.1UF 0.1UF 0.1UF 0.1UF
C551
ACASE 1OUF C516
J502 6.3V 0.1UF AVDD_3P3V

L506 VDL
10UH 0.1UF 0.1UF
LC1210 DUTDRVDD C564 C565 CC0603 CC0603
CC0603 CC0603
0.1UF 0.1UF C540 C539 C542 C538
CC0402 CC0402 CC0402 CC0402
C558 C559 0.1UF 0.1UF 0.1UF 0.1UF
C552
ACASE 1OUF C517

Figure 57. Evaluation Board Schematic, Power Supply Inputs

J501 6.3V 0.1UF GROUND
TEST POINTS

L500 DUTAVDD H501 H502

10UH
TP510
TP512
TP509

TP511

LC1210 AVDD_3P3V C569 C575 C566 C570 C574 H500

CC0603 CC0603 CC0603 CC0603 CC0603 H503
0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
C548
ACASE 1OUF C512
6.3V 0.1UF Mounting Holes
Connected to Ground

DUTDRVDD

C573 C572 C599

CC0603 CC0603 CC0603
0.1UF 0.1UF 0.1UF

To use optional power connection

Remove L501,L503,L504,L508,L509.
06216-061
AD9254
AD9254
EVALUATION BOARD LAYOUT

06216-062
Figure 58. Evaluation Board Layout, Primary Side

06216-063

Figure 59. Evaluation Board Layout, Secondary Side (Mirrored Image)

Rev. 0 | Page 34 of 40
 AD9254

06216-064
Figure 60. Evaluation Board Layout, Ground Plane

06216-065

Figure 61. Evaluation Board Layout, Power Plane

Rev. 0 | Page 35 of 40
AD9254

06216-066
Figure 62. Evaluation Board Layout, Silkscreen Primary Side

06216-067

Figure 63. Evaluation Board Layout, Silkscreen Secondary Side (Mirrored Image)

Rev. 0 | Page 36 of 40
 AD9254
BILL OF MATERIALS
Table 16. Evaluation Board Bill of Materials (BOM)
Omit
Item Qty. (DNP) Reference Designator Device Package Description Supplier/Part Number
1 1 AD9246CE_REVA PCB PCB ADI
2 24 C1, C2, C509, C510, C511, C512, Capacitor 0402 0.1 μF
C514, C515, C516, C517, C528,
C530, C532, C533, C538, C539,
C540, C542, C543, C544, C545,
C546, C554, C555
12 C3, C500, C502, C503, C504,
C505, C531, C534, C535, C536,
C537, C557
3 1 C501 Capacitor 0402 0.3 pF
4 2 C4, C5 Resistor 0402 0Ω
5 10 C513, C518, C519, C520, C521, Capacitor 0402 1.0 μF
C522, C523, C524, C525, C526
6 1 C527 Capacitor 1206 10 μF
7 1 C529 Capacitor 0402 20 pF
8 5 C548, C549, C550, C551, C552 Capacitor ACASE 10 μF
9 1 C553 Capacitor 0805 1.0 μF
10 15 C556, C558, C559, C564, C565, Capacitor 0603 0.1 μF
C566, C567, C568, C569, C570,
C572, C573, C574, C575, C599

11 1 CR500 LED 0603 green Panasonic

LNJ314G8TRA
12 1 D502 Diode SOT-23 30 V, 20 mA, HSMS2812
2 D500, D501 dual Schottky
13 1 D503 Diode DO-214AB 3 A, 30 V, SMC Micro Commercial
Components SK33-
TPMSCT-ND
14 1 D504 Diode DO-214AA 2 A, 50 V, SMC Micro Commercial
Components S2A-
TPMSTR-ND
15 1 D505 LED LN1461C AMB Amber LED
16 1 F500 Fuse 1210 6.0 V, 2.2 A Tyco, Raychem
trip current NANOSMDC110F-2
resettable fuse
17 1 FER500 Choke 2020 Murata
DLW5BSN191SQ2
18 1 J500 Jumper Solder jumper
19 3 J501, J502, J505 Jumper Solder jumper
20 1 J503 Connector 120 pin Male header Samtec TSW-140-08-G-T-RA
21 1 J504 Connector 10 pin Male, 2 × 5 Samtec
22 3 JP1, JP2, JP3 Jumper 3 pin Male, straight Samtec TSW-103-07-G-S
23 4 JP500, JP501, JP502, JP506 Jumper 2 pin Male, straight Samtec TSW-102-07-G-S
24 1 JP507 Jumper 3-pin Male, straight Samtec TSW-103-07-G-S
2 JP508, JP509 jumper
25 10 L500, L501, L502, L503, L504, Ferrite Bead 3.2 mm × Digikey P9811CT-ND
L505, L506, L507, L508, L509 2.5 mm ×
1.6 mm
26 1 OSC500 Oscillator SMT 125 MHz or CTS Reeves CB3LV-3C
105 MHz
27 1 P500 Connector PJ-102A DC power jack Digikey CP-102A-ND

Rev. 0 | Page 37 of 40
AD9254
Omit
Item Qty. (DNP) Reference Designator Device Package Description Supplier/Part Number
28 1 P501 Connector 10 pin Male, straight PTMICRO10
29 6 R1, R6, R563, R565, R574, R577 Resistor 0402 DNI
30 5 R2, R5, R561, R562, R571 Resistor 0402 0Ω
6 R10, R11, R12, R535, R536, R575
31 2 R3, R4 Resistor 0402 25 Ω
32 6 R7, R8, R9, R502, R510, R511 Resistor 0603 DNI
33 6 R500, R501, R576, R578, R579, Resistor 0402 DNI
R581
34 4 R503, R548, R549, R550 Resistor 0603 10 kΩ
35 1 R504 Resistor 0603 49.9 Ω
1 R505
36 9 R506, R508, R509, R512, R554, Resistor 0603 0Ω
R555, R556, R557, R560
23 R507, R513, R514, R515, R516,
R517, R518, R519, R520, R521,
R522, R523, R524, R525, R526,
R527, R528, R529, R530, R531,
R532, R533, R534,
37 4 R545, R546, R547, R558 Resistor 0603 4.7 kΩ
38 3 R551, R552, R553 Resistor 0603 1 kΩ
39 1 R559 Resistor 0603 261 Ω
40 2 R566, R567 Resistor 0402 33 Ω
41 3 R582, R585, R598 Resistor 0402 100 Ω
42 2 R583, R584 Resistor 0402 240 Ω
43 1 R586 Resistor 0402 4.12 kΩ
44 3 R580, R587, R588 Resistor 0402 10 kΩ
45 1 R589 Resistor 0603 261 Ω
46 2 R590, R591 Resistor 0402 25 Ω
47 1 R592 Resistor 0402 DNI
48 2 R593, R596 Resistor 0402 0Ω
49 2 R594, R595 Resistor 0402 10 kΩ
50 1 R597 Resistor 0402 4.3 kΩ
51 1 RP500 Resistor RCA74204 22 Ω
52 2 RP501, RP502 Resistor RCA74208 22 Ω
53 1 S1 Switch Momentary Panasonic EVQ-PLDA15
(normally
open)
54 2 S500, S501 Connector SMAEDGE SMA edge
2 S502, S503 right angle
55 2 S504, S505 Connector SMA200UP SMA RF 5-pin
upright
56 2 T500, T501 Transformer SM-22 M/A-Com ETC1-1-13
1 T1
57 1 T503 Transformer CD542 Mini-Circuits ADT1-1WT
1 T502
58 1 U500 IC 32-pin Clock ADI AD9515BCPZ
LFCSP _VQ distribution
59 1 U501 IC SOT-223 Voltage ADI ADP3339AKCZ-5
regulator

Rev. 0 | Page 38 of 40
 AD9254
Omit
Item Qty. (DNP) Reference Designator Device Package Description Supplier/Part Number
60 1 U502 IC SOT-223 Voltage ADI ADP3339AKCZ-1.8
regulator
61 1 U503 IC SOT-223 Voltage ADI ADP3339AKCZ-2.5
regulator
62 2 U504, U505 IC SOT-223 Voltage ADI ADP3339AKCZ-3.3
regulator
63 1 U506 IC 8-pin SOIC 8-bit Microchip PIC12F629
microcontroller
64 1 U507 IC SC70 Dual buffer Fairchild NC7WZ16
65 1 U508 IC SC70 Dual buffer Fairchild NC7WZ07
66 1 U509 IC 48-pin Buffer/line Fairchild 74VCX162244
TSSOP driver
67 1 U510 DUT 48-pin ADC ADI AD9254BCPZ
(AD9254) LFCSP_VQ
68 1 U511 (or Z500) IC 16-pin Differential ADI AD8352ACPZ
LFCSP_VQ amplifier
Total 128 107

Rev. 0 | Page 39 of 40
AD9254

OUTLINE DIMENSIONS
0.30
7.00 0.60 MAX 0.23
BSC SQ
0.60 MAX 0.18
PIN 1
INDICATOR
37 48
36 1
PIN 1
INDICATOR

TOP EXPOSED 4.25

6.75
VIEW BSC SQ PAD 4.10 SQ
(BOTTOM VIEW)
3.95

0.50
0.40 25 12
24 13
0.30
0.25 MIN
5.50
0.80 MAX REF
1.00 12° MAX 0.65 TYP
0.85
0.05 MAX
0.80
0.02 NOM
0.50 BSC COPLANARITY
0.20 REF 0.08
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2

Figure 64. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

7 mm × 7 mm Body, Very Thin Quad (CP-48-3)
Dimensions shown in millimeters

ORDERING GUIDE
Model Temperature Range Package Description Package Option
AD9254BCPZ-150 1, 2 –40°C to +85°C 48-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-48-3
AD9254BCPZRL7–1501, 2 –40°C to +85°C 48-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-48-3
AD9254-150EBZ1 Evaluation Board
1
Z = Pb-free part.
2
It is required that the exposed paddle be soldered to the AGND plane to achieve the best electrical and thermal performance.

©2006 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D06216-0-10/06(0)

Rev. 0 | Page 40 of 40