Gate Fringe Induced Barrier Lowering in Underlap FinFET

Structures and its Optimization

Angada B. Sachid, Dinesh K. Sharma, Senior Member, IEEE , V. Ramgopal Rao, Senior

Member, IEEE

Centre for Nanoelectronics, Department of Electrical Engineering

Indian Institute of Technology Bombay, Mumbai – 400076, India

{angada, dinesh, rrao}@ee.iitb.ac.in

Tel: +91-22-25767456, Fax: +91-22-25723707

ABSTRACT

The difficulty to fabricate and control precisely defined doping profiles in the

source/drain underlap regions of FinFETs necessitates the use of undoped gate underlap

regions as the technology scales down. We present a phenomenon called the Gate Fringe

Induced Barrier Lowering (GFIBL) in FinFETs with undoped underlap regions. In these

FinFETs, we show that GFIBL can be effectively used to improve ION. We propose the

use of high-κ spacers in such FinFETs to enhance the effect of GFIBL, and thereby

achieve better device and circuit performance. When compared to the underlap FinFETs

with Si3N4 spacers, with κ=20 spacers, we report 80% increase in ION at iso-IOFF

conditions and 15% decrease in the inverter delay for a fan out of 4.

Index Terms – FinFET, short-channel effects, CMOS scaling, fringe induced barrier

lowering, high-κ materials.

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 I. INTRODUCTION

FinFETs are the most promising candidates among the emerging multiple-gate devices

for the sub-32 nm technology nodes due to their superior scalability and ease of

processing. FinFETs have been demonstrated with both overlap [1] and underlap regions

[2]. FinFETs with graded or abrupt gate overlaps show a higher IOFF as the technologies

are scaled [3], which suggests that overlap regions need to be carefully optimized in these

devices. Due to this reason, the use of underlaps with an optimized graded doping profile

has received considerable interest recently [3][4]. As we continue to scale down FinFETs,

the fins need to get thinner in order to control Short-Channel Effects (SCE) [4]. Doping

profiles in such thin fins are not only difficult to experimentally realize [5], but the

process variations also lead to a large variation in the device characteristics. The use of

undoped underlaps with abrupt source/drain junctions seems to be an attractive

technology option for the future technology nodes. The effect of underlap length (LUN) on

the DC characteristics of FinFETs with Si3N4 spacers is shown in Figure 1 which clearly

establishes the need for underlaps. In this paper, we report for the first time a

phenomenon called the Gate Fringe Induced Barrier Lowering (GFIBL) in underlap

FinFETs. The conclusions from GFIBL suggest that the use of high-κ spacers in FinFETs

with undoped underlaps could offer an interesting alternative to improving the device and

circuit performance.

II. DEVICE STRUCTURE

We have used a 2D FinFET structure (Figure 2a) with a channel length (LG) of 20 nm, fin

thickness (TFIN) of 10 nm, and an effective oxide thickness of 0.75 nm [6]. LUN is kept at

20 nm and the gate electrode thickness (TG) is kept at twice the LG value unless stated

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otherwise. The source/drain and source/drain extension dopings are 1020 cm-3, while the

channel and underlap doping values are kept at 1015 cm-3. The threshold voltage (VT) of

the device is set to about 0.2 V for all the data presented here. The simulations are

performed using the Sentaurus design suite [7] with the drift-diffusion mobility, density

gradient quantum correction and band-to-band tunneling models turned on.

III. GATE FRINGE INDUCED BARRIER LOWERING (GFIBL)

GFIBL occurs in FinFETs with undoped underlap regions. The fringing field lines from

the gate electrode terminate in the source/drain underlap regions. Figure 2b (Left) shows

that the gate-electrode thickness (TG) modulates the barrier in this region. Figure 2b

(Right) shows that the barrier does not lower completely when VGS = VDD (= 1 V). This

barrier lowering in the underlap regions allows more carriers from the source to enter into

the channel region resulting in higher ION (Figure 3a), which eventually saturates for TG >

25 nm.

GFIBL is indeed quite different from the Fringe-Induced Barrier Lowering (FIBL) which

is observed in high-κ gate dielectrics [8]-[11]. In FIBL, the additional coupling through

the high-κ gate dielectric degrades the SCE in FinFETs [12]. However, GFIBL does not

degrade VT or sub-threshold slope or IOFF (Figure 3a) since it is confined to the undoped

underlap regions, and does not affect the barrier under the gate. Figure 3b shows that as

the underlap length is decreased, the effect of GFIBL and hence the difference in ION with

different TG decreases, vanishing when the S/D regions touch the gate edge.

IV. UNDERLAP FinFETs WITH HIGH-κ SPACERS

We propose the use of high-κ (κ > 7.5) spacers to increase the electric field coupling

between the gate electrode and the underlap regions so as to further lower the barrier in

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the source-underlap region. Figure 4 shows that the ION increases with increasing κ due to

the enhanced GFIBL. When compared to Si3N4 (κ = 7.5) spacers, ION increases by about

80% for spacers with κ = 20. IOFF degrades significantly for κ > 20 as the increase in the

electric field on the drain side causes a higher band-to-band tunneling. The ION / IOFF ratio

peaks at κ ≈ 18. As shown, the use of high-κ spacers linearly increases the fringe

capacitance component of the total gate capacitance, CGG (Figure 5). When compared to

Si3N4 spacers, the CGG increases by about 50% for spacers with κ = 20. The circuit delay

which is a function of the load capacitance and the drive current now depends on their

relative rate of change with κ. Figure 5 shows a considerable decrease in the propagation

delay (tP) for 1 < κ < 20 after which tP saturates. When compared to underlap FinFETs

with Si3N4 spacers, with κ = 20 spacers, there is 15% decrease in the delay of an inverter

with fan out 4.

V. CONCLUSION

We present a new phenomenon called GFIBL in FinFETs with undoped underlap

regions. We further show that the use of high-κ spacers in FinFETs enhances GFIBL,

which considerably increases ION. Using an optimal value of κ for the spacers, it is

possible to improve the device drive currents by about 80% and the transient performance

of FinFET circuits by about 15% in aggressively scaled FinFET technologies.

ACKNOWLEDGMENT

We wish to thank Prof. Anil K.G. and other students in the Microelectronics Group of the

Department of Electrical Engineering, IIT Bombay, for stimulating discussions. We also

wish to thank Synopsys Inc. for providing their advanced simulation tools to make this

simulation study possible.

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 VI. REFERENCES

1. H.-S. P. Wong, K. K. Chan, Y. Taur, Self-aligned (top and bottom) double-gate

MOSFET with a 25 nm thick silicon channel, International Electron Devices

Meeting, pp. 427-430, December 1997.

2. X. Huang, W-C. Lee, C. Kuo, D. Hisamoto, L. Chang, J. Kedzierski, E. Anderson, H.

Takeuchi, Y-K. Choi, K. Asano, V. Subramanian, T-J. King, J. Bokor, C. Hu, Sub-50

nm p-channel FinFET, IEEE Transactions on Electron Devices, Vol. 48, No. 5, pp.

880-886, May 2001.

3. V. Trivedi, J. G. Fossum, M. M. Chowdhury, Nanoscale FinFETs with gate-

source/drain underlaps, IEEE Transactions on Electronic Device, Vol. 52, No. 1, pp.

56-62, January 2005.

4. J. Kedzierski, M. Ieong, E. Nowak, T. S. Kanarsky, Y. Zhang, R. Roy, D. Boyd, D.

Fried, H.-S. P. Wong, Extension and source/drain design for high-performance

FinFET devices, IEEE Transactions on Electronic Device, Vol. 50, No. 4, pp. 952-

958, April 2003.

5. D. Pham, L. Larson, J.-W. Yang, FinFET device junction formation challenges,

International Workshop on Junction Technology, pp. 73-77, May 2006.

6. International Technology Roadmap for Semiconductors, 2005. http://public.itrs.net

7. Synopsys Sentaurus Design Suite. www.synopsys.com

8. G. C.-F. Yeap, S. Krishnan, M.-R. Lin, Fringing-induced barrier lowering (FIBL) in

sub-100 nm MOSFETs with high-κ gate dielectrics, Electronic Letters, Vol 34. No.

11, pp. 1150-1152, May 1998.

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9. Nihar R. Mohapatra, Madhav P. Desai, Siva G. Narendra, V. Ramgopal Rao, The

effect of high-κ gate dielectrics on deep sub-micrometer CMOS device and circuit

performance, IEEE Transactions on Electron Devices, Vol. 49, No. 5, pp. 826-831,

May 2002.

10. Q. Chen, L. Wang, J. D. Meindl, Fringe-induced barrier lowering (FIBL) induced

threshold voltage model for double-gate MOSFETs, Solid-State Electronics, Vol. 49,

No. 2, pp. 271-274, February 2005.

11. B.-Y. Tsui, L.-F. Chin, A comprehensive study of the FIBL of nanoscale MOSFETs,

IEEE Transactions on Electronic Device, Vol. 51, No. 10, pp. 1733-1735, October

2004.

12. C. R. Manoj, V. Ramgopal Rao, Impact of high-κ gate dielectrics on the device and

circuit performance of nanoscale FinFETs, IEEE Electron Device Letters, Vol. 28,

No. 4, pp. 295-297, April 2007.

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 VII. FIGURE CAPTIONS

Figure 1 – DC characteristics of a pure underlap FinFET with Si3N4 spacers (VDD = 1 V)

as a function of the underlap length.

Figure 2 (a) – The top cross-sectional view of the FinFET structure showing the gate

length (LG), underlap length (LUN), extension region length (LEXT) and physical oxide

thickness (TOX).

Figure 2 (b) – Variation of conduction band energy as a function of X at various gate-

electrode thicknesses (Left) and at VG = 0 and VG = VDD (= 1 V) (Right)

Figure 3 (a) – DC characteristics of a pure underlap FinFET as a function of TG.

Figure 3 (b) – ION of an undoped underlap FinFET for TG = 2 nm and TG = 40 nm as a

function of LUN.

Figure 4 – DC characteristics of an undoped underlap FinFET with high-κ spacer as a

function of spacer κ.

Figure 5 – Total gate capacitance of an underlap FinFET with high-κ spacers and the

transient characteristics of an inverter with fan out = 4 as a function of spacer κ.

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Figure 1. Angada B. Sachid et. al.

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Figure 2. Angada B. Sachid et. al.

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Figure 3. Angada B. Sachid et. al.

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Figure 4. Angada B. Sachid et. al.

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Figure 5. Angada B. Sachid et. al.

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