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Int. J. Electron. Commun.

(AEÜ) 67 (2013) 1058–1067

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RF CMOS active inductor band pass filter with post fabrication

Saiyu Ren ∗ , Chris Benedik
Wright State University, Department of Electrical Engineering, Dayton, OH 4543, USA

a r t i c l e i n f o a b s t r a c t

Article history: This paper presents an active inductor bandpass filter (BPF) architecture with selectable 50  driving
Received 5 March 2013 capability and post fabrication calibration for gain, center frequency, and quality factor. The design details,
Accepted 20 June 2013 and performance assessment that facilitate selecting an offline calibration mode to measure and tune post
fabrication BPF performance are discussed. A specific design example for a L1/L2 channel GPS receiver is
Keywords: included with a BPF that is required to pass the L2 signal centered at 1.227 GHz with a gain of approx-
Active inductor
imately16 dB at the center frequency, have a 3 dB bandwidth of 30 MHz (Q = 41) and rejection of the L1
Bandpass filter
signal at 1.575 GHz by at least 60 dB relative to the center frequency. A multistage active inductor BPF
Corner analysis
90 nm CMOS design is presented that meets these specifications with typical process parameters. It is
demonstrated that the post fabrication design based on typical corner analysis can be re-tuned to the
desired performance for process variations across the slow and fast corners using the offline measuring
and tuning control inputs.
© 2013 Elsevier GmbH. All rights reserved.

1. Introduction figures and linearity. Simplifying the tunable active inductor for
low power applications is also reported in [14]. However, the issue
State of the art wireless communication solutions demand an of post fabrication measurement and tuning to the desired perfor-
integrated multi-standard transceiver which provides access to mance of a BPF embedded in an on-chip RF signal chain has not
various services. This demand is a driving force for the develop- been adequately addressed. If the active inductor BPF is designed
ment of flexible radio frequency (RF) CMOS transceiver building based on typical model parameters, the center frequency, Q fac-
blocks [1–3]. A key component that continues to be a challenge tor, and gain can deviate widely from the desired values as the
is a tunable RF BPF with the required Q factor for desired opera- process parameters vary across the slow to fast corners (espe-
tion. The stringent requirements for the RF BPFs have traditionally cially for CMOS processes of 90 nm and below). Although some
been met with off-chip surface acoustic wave (SAW) based filters applications may require a continuous automatic tuning feature to
[4,5]. Passive spiral inductors provide a potential mechanism for account for temperature variations and other environmental fac-
on-chip RF filters; however, their application is limited due to low Q tors, an offline measurement capability for tuning to the desired
factor, relatively large form factor, and lack of tunability. Fully inte- operating requirements may be sufficient for many applications
grated RF BPFs based on active CMOS transistor inductors provide and may be necessary as a preliminary step for automatic contin-
an attractive alternative for many applications. Advantages of the uous tuning if required. The contributions presented in this article
active CMOS inductor based filter include wide tuning range for are (1) a practical design of CMOS active inductor BPF with an
center frequencies, potential high Q values, adjustable gain, and offline measurement and tuning capability; (2) a modified CMOS
small size. There have been a number of designs reported for active active inductor circuit that includes selectable multiple stages
inductor based BPFs that include various ranges of tunability, Q fac- for improved capability to adjust filter center frequency, Q fac-
tors, noise figures, and linearity [6–13]. A serious concern that has tor, gain and stop band attenuation; (3) wide band RF input and
limited the implementation of CMOS active inductors in wireless output buffers facilitate insertion of the BPF into various on-chip
products is the sensitivity to fabrication process parameter varia- applications without affecting signal chain or filter operation; (4)
tions. Most of the previous work has focused on center frequency potential operation in the 800 MHz to 6 GHz range with specific
and Q factor tuning with some work aimed at improving noise design center frequency tuning over a 1.0 GHz range and Q fac-
tors ranging from 17.5 to 175 with stop band attenuation of more
than 60 dB, and variable center frequency gain. The paper is orga-
∗ Corresponding author. Tel.: +1 9377755051.
nized as follows. Section 2 discusses the active inductor BPF circuit,
E-mail address: (S. Ren).
including the active inductor CMOS circuit and transfer function

1434-8411/$ – see front matter © 2013 Elsevier GmbH. All rights reserved.
S. Ren, C. Benedik / Int. J. Electron. Commun. (AEÜ) 67 (2013) 1058–1067 1059

development. Section 3 presents the one stage BPF, transfer func-

tion, and selectable calibration/tuning. Section 4 includes the
three/five stage BPF with performance analysis, and Section 5 has
the conclusion.

2. Active conductor BPF circuit implementation

The active inductor circuit implementation is based on the well

known gyrator/capacitor combination as depicted in Fig. 1. From
Fig. 1, the equivalent inductance, Leq is derived as follows:

gm1 gm2 1
Iin = −gm2 Vc = Vin = V (1)
jωC jωLeq in

From (1), the equivalent inductance for this idealized circuit is

Leq = (2)
gm1 gm2
Fig. 1. Gyrator based active inductor.
where C is a varactor capacitor that the capacitance can be adjusted
by varying the voltage Vc ; gm1 and gm2 are trans-conductance of
transistors m1 and m2, respectively.

Fig. 2. Active inductor, (a) basic circuit, (b) small signal equivalent circuit.
1060 S. Ren, C. Benedik / Int. J. Electron. Commun. (AEÜ) 67 (2013) 1058–1067

tors, and gain. A critical feature incorporated in this design which

has not been adequately addressed in previous designs is the capa-
bility to perform offline calibration to determine post fabrication
performance and tune to the desired specifications.

2.1. Active inductor CMOS circuit and transfer function

The basic CMOS circuit for implementing a gyrator based active

inductor for this work is shown in Fig. 2(a).
The transistors m1 and m2 serve as the gyrators and C1 is a
varactor capacitor. The small signal equivalent circuit is shown in
Fig. 3. One stage BPF with active inductor. Fig. 2(b).
ic1 = gm2 (Vin − Vc1 ) − gm3 Vc1 − gd5 Vc1 − gd2 Vc1 + gd3 (Vg1 − Vc1 ) (3)
There are many proposed CMOS circuit implementations of the
The voltage on the varactor capacitor C1 is
gyrator-based inductor. The circuit implementation used in this
work incorporates the required degrees of freedom to facilitate ic1
Vc1 = (4)
tuning to the desired combination of center frequency, Q factor, sC1
bandwidth, center frequency gain and stop band attenuation. A Define
key feature is the capability to selectively cascade filter stages as
a mechanism to improve the tuning ranges of bandwidth, Q fac- G = gm2 + gm3 + gd5 + gd2 + gd3 (5)

Fig. 4. Complete schematic of one stage BPF with blocks for buffers and VGA.

Fig. 5. Bode plots for TT, SS, and FF of one stage active BPF with offline calibration capability.
S. Ren, C. Benedik / Int. J. Electron. Commun. (AEÜ) 67 (2013) 1058–1067 1061

Fig. 6. Three/five stage BPF with offline calibration.

then As seen in Fig. 3, the one stage active filter is a parallel active
LC circuit together with input/output buffers and a variable gain
gm2 Vin + gd3 Vg1
Vc1 = (6) amplifier (VGA). The transfer function for the parallel LC circuit is
G + sC1
ω0 2 (rL + sL)
The voltage Vg1 that is fed back to the gate of transistor m1 is Z=  ω0
s2 + s Q
+ ω0 2
Vg1 = BVc1 (7)
where 1 1
gm3 + gd3
ω0 =  and Q = (14)
LC2 ω0 rL C2
B= (8)
gd4 + gd3
Substituting (11) and (12) to (14) yields
Solving (6) and (7) for Vg1 as a function of Vin yields
Bgm2 Vin Bgm1 gm2 gm1 gm2 C1
Vg1 = (9) ω0 = and Q = √ (15)
C1 C2 √G − Bgd3 C2
G − Bgd3 + sC1 B

Then where G and B are given by (5) and (8), respectively.

As discussed previously, the values of gm1 , gm2 , and gm3 may vary
Vin Vin G − Bgd3 + sC1
Zin = = = = rL + sL (10) considerably across the process corners, so post fabrication control
iin gm1 Vg1 Bgm1 gm2
of the center frequency (ω0 ) is obtained through the varactor prod-
where uct C1 C2 and the gain factor B. The gain factor B given by (8) can be
varied after fabrication via control of the bias voltage to m4 result-
G − Bgd3 ing in a change of the drain current and finally the conductance
rL = (11)
Bgm1 gm2 gd4 . 
The Q factor in (15) is controllable by C1 /C2 and the gain factor
C1 B. Increasing B increases Q and also ω0 . As will be seen later, the
L= (12) ability to control the magnitudes of C1 , C2 , gain factor B, and the
Bgm1 gm2
gain of VGA together with the capability to select multiple stage
It is noted that this topology for the active inductor has a series filters provides the required degrees of freedom for post fabrication
resistor (rL ) in addition to the inductor that can affect the inductor calibration and tuning over a wide range of center frequencies and
Q factor. The value of the active inductor (L) is proportional to the Q factors.
capacitor C1 , which will be realized as a varactor and is inversely
proportional to the product of B · gm1 · gm2 . The n-channel process
3. Proposed one stage BPF with offline calibration
gains (and the corresponding value of the product gm1 ·gm2 ) may
have considerable variation across the process corners. The effect of
A complete circuit schematic for the one stage BPF is shown in
this process variation on L can be offset by adjusting C1 and B via bias
Fig. 4 which includes coupling capacitors, bias circuits, and offline
(VC1 and VB4 ) adjustments to the varactor (C1 ) and to the p-channel
calibration input and output buffers. The calibration buffers have
transistor m4 to control the drain current of m4 and the corre-
an off-chip selection option that turns off the on-chip buffers while
sponding value of gd4 . The gain factor B comes into play because
turning on the off-chip buffers. The output buffer for the calibration
the feedback voltage (Vg1 ) taken from the drain of m4 rather than
option includes a second stage buffer that is capable of driving off-
directly from the varactor C1 , so that Vg1 = BVc1 . The gain factor B is
chip 50  measuring circuit loads over a wide RF frequency range
adjustable by the bias voltage to m4 (VB4 ) providing more flexibility
[15]. The off-chip calibration buffers draw no power when on-chip
for tuning of the center frequency and Q factor as will be discussed
operation is selected. To demonstrate the calibration procedure
in more detail below.
tunability and performance, a potential application is selected for a
GPS L1/L2 channel receiver. A BPF is required to pass the L2 signal
2.2. One stage BPF with transfer function centered at 1.227 GHz with a gain at the center frequency of approx-
imately 16 dB, have a 3 dB bandwidth of 30 MHz (Q = (f0 /BW) = 41)
A one stage BPF implemented with the active inductor described and the L1 signal at 1.575 GHz should be rejected by at least 60 dB
above is shown in Fig. 3. relative to the center frequency of L2.
1062 S. Ren, C. Benedik / Int. J. Electron. Commun. (AEÜ) 67 (2013) 1058–1067

Fig. 7. Bode plots of three stage BPF before offline calibration with 30 MHz bandwidth for TT.

The one stage BPF was designed using the typical-typical fixed, the circuit is simulated with slow–slow (SS) and fast–fast
(TT) 90 nm model parameters in an attempt to meet the above (FF) corners with the results shown in left and right black (solid)
requirements. The simulation result is shown as the middle black waveforms, respectively in Fig. 5 indicating a significant change in
waveform (solid) in Fig. 5. The center frequency is at 1.227 GHz and center frequency and Q factor at these process corners. The actual
the bandwidth is 29 MHz resulting in a Q of 42. With the design post fabrication response will fall somewhere between the SS and

Table 1
Calibration control inputs changes following offline calibration procedure of Fig. 9 for FF corner analysis.

# of Iteration Calibration control inputs Outputs Comments

VC1 (V) VC2 (V) VB4 (V) Gain control (V) f0 (GHz) BW (MHz) Gain (dB) L1 rejection (dB)

Three stage BPF

TT −0.09 0.125 0.657 0.55 1.227 30 16.5 68
FF0 (starting point) −0.09 0.125 0.657 0.55 2 116 −6.96 N/A Path1 case of Fig. 9
FF1 0.2 0.125 0.657 0.55 1.669 79 3.87 N/A Increase C1
FF2 0.5 0.125 0.657 0.55 1.624 79 3.87 N/A Increase C1
FF3 0.5 0.125 0.7 0.55 1.453 65 10.02 N/A Increase VB4
FF4 0.5 0.125 0.72 0.55 1.36 64 10.59 N/A Increase VB4
FF5 0.5 0.125 0.74 0.55 1.224 71 9.31 N/A Increase VB4 is no longer helpful
FF6 1 0.125 0.72 0.55 1.345 64 10.92 N/A Adjust C2
FF7 1 0.5 0.72 0.55 1.289 62 9.84 N/A Adjust C2
FF8 1 0.59 0.72 0.55 1.227 62 7.47 N/A Adjust gain control
FF9 1 0.59 0.72 0.6 1.227 62 15.1 N/A Adjust gain control
FF10 1 0.59 0.72 0.62 1.227 62 16.55 42.5 Not be able to reach 60 dB L1
rejection and BW of 30 MHz
Five stage BPF
TT −0.12 0.2 0.666 0.56 1.227 31 16.66 106
FF0 (starting point) −0.12 0.2 0.666 0.56 2.02 97 −13.69 N/A Path 1 case of Fig. 9
FF1 0.6 0.2 0.666 0.56 1.57 50 19.92 N/A Increase C1
FF2 0.8 0.2 0.666 0.56 1.562 50 19.87 N/A Increase C1
FF3 0.6 0.2 0.72 0.56 1.348 42 29.89 N/A Increase VB4
FF4 0.6 0.2 0.73 0.56 1.298 43 29.07 N/A Increase VB4 is no longer helpful
FF5 0.6 0.5 0.72 0.56 1.295 42 27.45 N/A Increase C1
FF6 0.6 0.6 0.72 0.56 1.227 42 21.26 N/A Adjust C2
FF7 0.6 0.6 0.72 0.55 1.227 42 17.15 N/A Adjust gain control
FF8 0.6 0.6 0.72 0.548 1.227 42 16.27 87 Meet the desired performance of
60 dB rejection and BW close to
be 30 MHz
S. Ren, C. Benedik / Int. J. Electron. Commun. (AEÜ) 67 (2013) 1058–1067 1063

Fig. 8. Before and after calibration results for three stage (top) and five (bottom) stage active BPF for FF corner analysis.

FF results making it very difficult (if not impossible) to tune the The single stage BPF facilitates a wide range of center fre-
center frequency to the desired value without an offline calibration quencies and Q factors which may be suitable for a number of
capability. The offline calibration mode is also selected for these applications; however, it is noted that the L1 rejection is only 26 dB
three sets of corner analysis. The 50  buffer output when driv- for the TT parameter design which does not meet the desired L1
ing a 50  load are shown in Fig. 5 in the red (dotted) lines as rejection requirement of at least 60 dB for the GPS receiver appli-
well. This illustrates that the measured off-chip calibration results cation. A multistage BPF is needed to get the center frequency of
closely match the on-chip results. 1.227 GHz, 30 MHz bandwidth, a Q of 41, and 60 dB rejection at

Table 2
Performance comparison of active inductor BPF.

Specifications Ref. [6] Ref. [11] Ref. [13] Ref. [14] Ref. [16] Ref. [17] This work

CMOS technology 0.20 ␮m 0.35 ␮m 90 nm 0.13 ␮m 0.35 ␮m 0.35 ␮m 90 nm

Filter order 2 2 2 2 2 2 2
Gain (dB) 20–30 −15 30 0 0 0 16
Center frequency fc 5.4 GHz 900 MHz 3.46 GHz 5.13 kHz 2.19 GHz 2.14 GHz 1.227 GHz
fc tuning range 3.34–5.72 GHz 400–1100 MHz 300–7320 MHz 1 kHz–25 kHz 1.94–2.21 GHz N/A 800–6000 MHz
Q tuning range 2–665 2–80 3900@5.75 GHz 3.2@5.13 kHz 20–80 35.6@2.14 GHz 17.5–175
Power supply (V) 1.8 2.7 1.2 1.5 1.3 2.5 1.2
Power dissipation (mW) 4.4 45.9 18.6/68 (2 modes) 2.3 5.2 17.5 77.5 (5 stages)
Driving 50  load No No No No No No Yes
Post fab process variation No No No No No No Yes
SFDR (dB) N/A N/A N/A N/A 31 55 37
FOM (dB) N/A N/A N/A N/A 136 159 147
1064 S. Ren, C. Benedik / Int. J. Electron. Commun. (AEÜ) 67 (2013) 1058–1067

Fig. 9. Calibration procedure flow diagram.

1.575 GHz. A three stage BPF filter with an option to select five stage corner result back to TT center frequency with the desired band-
is discussed in the next section, which provide additional flexibil- width and L1 rejection by using the offline calibration measurement
ity in obtaining the desired combination of center frequency, Q and capability, as will be seen below. Further analysis shows that a
rejection considering process variations. five stage BPF is needed to meet the GPS specifications at the pro-
cess corners. The details of post fabrication calibration procedure
are discussed below for the three and five stage BPF assum-
4. Three/five stage BPF with offline calibration
ing the post fabrication parameters are at the FF corner, which
is the most difficult case for obtaining the desired performance
Fig. 6 shows a multistage BPF with capability to select either a
three stage filter or a five stage filter. The stages are identical and the
tuning inputs (VB4 , VC1 , VC2 , and Gain Control) are the same for all
stages to simplify tuning. With the three stage option selected, the 4.1. Offline calibration procedure
third stage buffer is activated (and the fifth stage buffer is turned
off) to permit both the on-chip and calibration output to be taken Fig. 8 shows bode plots of the three stage BPF (top) and five
from the three stage filter. If the five stage option is selected, the stage BPF (bottom) for FF corner analysis. The red (dotted) trace on
fifth stage buffer is activated (and the third stage buffer is turned the right side is the output obtained assuming the design with TT
off) to permit both the on-chip and calibration output to be taken parameters and post fabrication parameters at the FF corner. This
from the five stage filter. is the starting point for calibration, where it is seen that both cases
With the three stage BPF selected, the identical stages are have center frequencies, bandwidths, and gain that are far from
designed to obtain the desired response using TT parameters with the desired values. The calibration procedure outlined in Fig. 9 is
the frequency response shown in Fig. 7 (middle waveform). The used for both three and five stage designs in an attempt of meet
three stage option facilitates a design that has the required cen- the required specifications for the GPS example with the final best
ter frequency (f0 = 1.227 GHz), bandwidth (BW = 30 MHz), Q factor result shown in Fig. 8 with the black (solid) traces. As seen in Fig. 8,
(Q = 41) and rejection at 1.575 GHz of 68 dB. With the design fixed for FF corner analysis the three stage design is able to meet the cen-
based on TT parameters, the results for SS and FF corner analysis are ter frequency and gain requirements, but the L1 rejection is only
also shown in Fig. 7, labeled as SS and FF, respectively. The center 42.7 dB and band width is 62 MHz, which do not meet the speci-
frequency, bandwidth, and voltage gain for the SS and FF corners fications of L1 rejection at least 60 dB and bandwidth of 30 MHz.
have changed significantly from the desired values for the TT design The five stage design is able to meet all four of the performance
case. requirements.
The results in Figs. 5 and 7 show the potential process variation The calibration (tuning) procedure is based on the capability to
effect of the 90 nm is very large, so including the capability for post measure the filter response with external signal input and off-chip
fabrication calibration is very important. output using the calibration selection option shown in Fig. 6. The
The three stage option would allow a wide range of tuning for calibration control inputs (VB4 , VC1 , VC2 , and Gain Control) are exter-
post fabrication process parameter deviation from the TT values; nal analog DC voltages and are adjusted in an iterative manner as
however, for the GPS example, it is impossible to adjust the FF indicated in the flow diagram of Fig. 9 until the post fabrication
S. Ren, C. Benedik / Int. J. Electron. Commun. (AEÜ) 67 (2013) 1058–1067 1065

L1 frequency; however, the five stage design is able to meet all


4.2. Offline calibration results

Fig. 11 summarizes the five stage performance showing the

original TT process parameter design result and the post fabrica-
tion calibrated result that is obtained for the SS and FF corners.
The results shown in Fig. 11 demonstrate the robust tuning capa-
bility provided by the multistage BPF together with the control
inputs for adjusting the values of C1 , C2 , feedback gain B, and cen-
ter frequency, VGA gain. The performance requirements for the
GPS example are obtained for both the SS and FF corners. The
actual post fabrication parameters should fall somewhere between
these corners, so post fabrication calibration will be able to adjust
to the desired performance for all cases. This makes the offline
calibration an essential feature for successful post fabrication
The multistage BPF architecture facilitates a wide range of
post fabrication tuning options which should apply to many
different applications. The wide tuning range of potential Q fac-
tors with a three stage BPF filter is shown in Fig. 12 with
TT analysis, where it is seen that Q can be varied from 17.5
to 175 with a center frequency of 1.227 GHz by only adjus-
ting the calibration control inputs. The power dissipation for
the three and five stage operation at 1.227 GHz with the offline
calibration circuit turned off is 46.6 mW and 77.5 mW, respec-
tively. The above performance is evaluated with TT model
The performance of this multi-stage BPF in this work is com-
pared to previously published active inductor based filter designs
in Table 2. Previous work includes various tuning ranges for center
frequencies and Q values; however, this work is unique in provid-
ing a post fabrication offline measurement and tuning capability.
This requires a selectable on-chip buffer to drive the 50  off-chip
measurement instruments or for some applications driving off-chip
signal chain components. The calibration capability permits adjus-
ting the filter center frequency, Q value, and gain to the desired
levels as required due to process variation and component mis-
match. This work includes a modified CMOS active inductor circuit
that facilitates selectable multiple stages for improved capability to
adjust filter center frequency, Q factor, gain and stop band attenua-
tion. The wide band RF input and output buffers facilitate insertion
of the BPF into various on-chip applications without affecting sig-
nal chain or filter operation. These features increase chip area and
power requirements compared to some of the previous work, but
provide a needed capability for many applications considering the
increased effect of process variations and component mismatch for
submicron CMOS feature size.
A Figure-of-Merit for active filter is included in [16] as defined
Fig. 10. Calibration control inputs as a function of iteration no.

N · SFDR · f0 · Q
FOM = (16)
measured response matches the desired response. The capacitance
of varactors C1 and C2 are controlled by VC1 and VC2 , respectively. where N is the number of poles in the filter, SFDR is Spurious Free
The details of the calibration procedure for FF corner parameters Dynamic Range, f0 is center frequency, Q is the quality factor, and
are shown in Table 1 for both three stage and five stage designs PD is the power consumption. For the five stage BFP in this work,
as a function of iteration number. As seen in Table 1, the cali- substitute N of 10, SFDR of 70.8 (37 dB), f0 of 1.227 × 109 , Q of 41
bration control inputs start with the values that were set by the and PD of 0.0775 to (16). The FOM has a value of 147 dB compared
design using the TT process parameters and the iteration paths to136 dB in [16] and 159 dB in [17]. This shows that the active fil-
provided by Fig. 9 permit adjusting the calibration control inputs ter in this work which includes the capability for post fabrication
on each iteration to converge on the desired performance values. calibration compares favorably to previous works in terms of filter
The values of the calibration control inputs as a function of iter- performance and power dissipation without this critical calibration
ation number is shown in Fig. 10. As seen in Table 1, the three feature. The other works cited in Table 2 do not include SFDR, so a
stage design is not able to meet the 60 dB rejection criteria at the FOM comparison is not possible.
1066 S. Ren, C. Benedik / Int. J. Electron. Commun. (AEÜ) 67 (2013) 1058–1067

Fig. 11. Offline calibration results of five Stage BPF for TT, SS FF respectively.

Fig. 12. Wide Q tuning capability of three stage BPF with TT analysis (17.5–175).
S. Ren, C. Benedik / Int. J. Electron. Commun. (AEÜ) 67 (2013) 1058–1067 1067

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