A Fully Synthesized All-Digital VCO-Based

Analog-to-Digital Converter

Vishnu Unnikrishnan, Srinivasa Rao Pathapati and Mark Vesterbacka

Division of Integrated Circuits and Systems
Dept. of Electrical Engineering
Linköping University
Linköping, Sweden 581 83
Email: {visun26@isy, sripa601@student, markv@isy}.liu.se

Abstract—Synthesis of all-digital ADCs leads to significant
reduction in design cost and design time, besides improving
cross-technology portability. In this work, an ADC which is fully
described in digital HDL is synthesized, placed and routed using
standard digital design tools. A VCO-based architecture is chosen
for its synthesizability. The design flow employed is discussed.
The circuit is synthesized using the standard cell library in a
65 nm CMOS process, delivering a resolution of 9 ENOB over
10 MHz bandwidth according to post layout parasitic extracted
simulations using the Spectre simulator. Post synthesis and post
place-and-route performances are provided.
I. I NTRODUCTION
The ongoing trend of CMOS technology scaling and
System-on-Chip integration demands high performance inte-
grated data converters portable to fine-feature processes. How-
ever, the analog intensive nature of conventional data converter
architectures makes their design and cross-technology porting
difficult, expensive and time consuming. It is possible to
implement data converters entirely using digital circuits by
representing signals using time instead of using voltage or
current, which is a technique referred to as time-mode or
time-domain signal processing. This enables automated design
and porting of the circuit using commercial digital design
tools. Furthermore, an all-digital implementation is expected to
improve its performance as well as area and energy efficiency
as the feature size scales down.
Several analog-to-digital converter (ADC) architectures
employing time-mode techniques have been demonstrated re-
cently, achieving high performance and low power consump-
tion [1]–[6]. However, they use custom circuits or analog
circuits limiting the possibility of synthesis and automatic
place-and-route using a standard digital design flow. A time-
mode ADC built exclusively using standard cells is presented
in [7] and a stochastic flash ADC that is fully synthesized
is reported in [8]. In this work, an all-digital ADC circuit
is fully described and synthesized from a digital hardware
description language (HDL) using the standard cell library in
a 65 nm CMOS process. A VCO-based ADC architecture [2],
[4] is chosen to demonstrate the synthesis of ADCs. The idea
can, however, be easily extended to a variety of possible all-
digital architectures. The design flow employed to synthesize
and place-and-route the circuit is discussed. The circuit de-
livers an ENOB of around 9 bits over a 10 MHz bandwidth
according to post layout parasitic extracted simulations using
the Spectre simulator. Performance from the post synthesis
simulation as well as from the post place-and-route parasitic
extracted simulation are provided to aid estimation of the
drop in resolution due to automatic place-and-route. Section II
provides an overview of the ADC circuit. Section III discusses
the design flow employed. Section IV presents the simulation
results and Section V concludes the discussion.
II. ADC CIRCUIT
VCO-based ADC architecture is an attractive candidate
for high performance synthesizable all-digital ADCs due to
inherent noise shaping and anti-aliasing properties. A converter
circuit similar to the one used in [7] is used in this work to
investigate the feasibility of synthesis of ADCs. The circuit
is shown in Fig. 1 and can be modeled as shown in Fig. 2.
ψ(v(t)) is the instantaneous frequency of the oscillator, and,
φ(t), its instantaneous phase. φq (t) is the quantized phase
which is sampled using frequency Fs (= 1/Ts ). A backward
difference operation on the resulting sequence generate the
converter output y(k), where k is the sample index. It can
be shown that the quantization noise transfer function (NTF)
of the converter is
Nφ
NTF = − (1 − z −1 ) (1)
2π
where Nφ is the number of inverter stages in the ring oscillator,
indicating first order shaping of the quantization error. Further,
the model has an inherent sinc anti-aliasing filtering due to
continuous-time sampling.
A supply controlled multi-phase ring oscillator with Nφ
static CMOS inverters is used as the VCO where Nφ is an
odd number. The phase taps of the oscillator are connected
to an array of counters which performs accumulation of the
phase progression. Output of the counter array is sampled by
a register. The counters are encoded in Gray-code in order to
eliminate spurious error samples arising from partial sampling
of the counter output [7]. The sampled counter output from
each phase tap is binary converted and first order differentiated.
The results are added together to generate the converter output.
The use of supply controlled oscillator implies non-linear
voltage frequency conversion necessitating digital post pro-

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Fig. 2. Model of the ADC.
cessing to retrieve performance. A correction block employ-
ing polynomial-fit estimation of static non-linearity from the
converter ramp response is used to correct for VCO non-
linearity. Further details about the correction scheme employed
and the associated hardware cost in terms of polynomial
order, wordlength requirements, power consumption etc. can
be found in [7]. The digital correction block is modeled and
verified using MATLAB.
III. S YNTHESIS FLOW
A design flow which can be used for circuit and lay-
out synthesis of all-digital mixed-signal circuits is shown in
Fig. 3. Since the target circuit is expected to consist of basic
digital components, a digital hardware description language
like Verilog or VHDL may be used to describe the circuit.
Verilog is used in this work. The HDL described hardware
is synthesized using the standard digital cell library provided
by the process vendor. The resulting netlist is simulated at
transistor level using the Spectre simulator to verify functional
correctness and to estimate resolution and power consumption.
If the results are satisfactory, the netlist is placed and routed
using Cadence SoC Encounter. The layout is then verified
by simulating the parasitic extracted netlist using Spectre.
If the results are satisfactory, the layout can be optimized
for production. Otherwise, the HDL circuit description, the
synthesis constraints and/or the place-and-route constraints are
revisited in order to resolve the detected issues or to improve
the performance. The flow is iterated until required results are
achieved.
A. Synthesis and initial verification
In order to synthesize the circuit, the HDL description is
input to the synthesis software together with the synthesis
constraints. Synopsys Design Compiler is used in this work
to perform logic synthesis. The standard digital cell library
*
Fig. 3. Design flow for automatic synthesis and place-and-route of the ADC.
provided by the technology vendor is used as the target library.
A 65 nm CMOS process is used. The synthesis constraints
are set to force the synthesizer to make desired choices
regarding the drive strength of the cells in the performance
critical parts of the circuit, thereby fine adjusting performance.
For example, the load, the delay and the transition time at
the output of the ring oscillator are constrained in order to
make the synthesizer pick the desired drive strength for the
inverters. Adjusting the drive strength of the delay elements
scales the tuning curve of the oscillator, and hence, the
performance of the converter. Furthermore, a multi-threshold-
voltage flow is adopted in order to optimize performance and
power consumption. For example, the ring oscillator and the
Gray-counters are synthesized using cell libraries with standard
threshold voltage since those modules should operate at a high
speed to achieve good performance. The remaining parts which
are not crucial for performance are synthesized using high
threshold voltage libraries to reduce power consumption. The
netlist generated during synthesis is evaluated using accurate
transistor level simulation with the Spectre simulator to verify
the functional correctness of the circuit as well as to estimate
the converter resolution. After necessary iterations required to
meet the performance requirements, the synthesized netlist as
well as the constraints file generated during synthesis are used
to perform place-and-route.
B. Place-and-route
The synthesized netlist consisting of standard cells needs
to be place and routed. SoC Encounter Digital Implementation
System from Cadence is used for this purpose in this work.
Prior works that attempt automatic place-and-route of mixed-
signal circuits like all-digital phase locked loops (PLLs) [9],
[10] use custom cells at the leaf level as well as pre-placed
macros at higher hierarchical levels, in order to eliminate the
uncertainty due to place-and-route in performance critical parts
of the circuit. In this work, we limit the uncertainty using
constraints instead of eliminating it, thereby retaining good
cross-technology portability by avoiding the use of custom
 Before correction
0 NBW = 73.1 kHz

−20

−40

PSD (dBFS/NBW)
−60

−80

−100

−120 5 6 7
10 10 10
Frequency (Hz)

After correction
0 NBW = 73.1 kHz

−20
Fig. 4. Layout of the ADC generated after automatic place-and-route.
−40

PSD (dBFS/NBW)
cells. Besides placing the standard cells and routing the nets, −60
place-and-route involves multitude of other tasks including
floor planning, power planning, placement of well straps, −80
clock tree synthesis (CTS) etc. Place-and-route constraints are
utilized to exercise control over these tasks in order to limit −100

performance degradation resulting from automatic place-and-

route. For example, the pre-sampling circuits of the converter −120 5
10
6
10 10
7

Frequency (Hz)
process time-continuous information and any delay mismatch
between the parallel signal paths in this block contributes to
Fig. 5. Spectrum from the single tone test of the post synthesis circuit before
the error in the phase signal. In order to limit the wire load and after digital correction.
imbalance in this block, the cell placement of the block is
restricted to a small area. Further, the ring oscillator needs TABLE I. S IMULATED DYNAMIC PERFORMANCE AFTER SYNTHESIS
to be connected to the signal input pin of the converter. This
is achieved by assigning the oscillator to a separate power Performance Metric Correction OFF Correction ON
domain. The placement area for this power domain should be Sample rate (MHz) 150
restricted as well, in order to limit the wire load imbalance due OSR 7.5 7.5
to automatic place-and-route. The place-and-route tasks and
Bandwidth (MHz) 10 10
the constraints are managed using scripts, enabling automated
repetitions and script based tuning of circuit parameters and ENOB 4.0 9.4
SNDR (dB) 26.0 58.4
constraints. Important outputs from place-and-route include SNR (dB) 70.1 67.4
the GDSII file describing the geometry of the layout and the SFDR (dB) 28.9 65.8
modified netlist, in addition to the reports summarizing timing, THD (dB) −26.0 −59.7

power consumption and area consumption. Figure 4 shows the

layout of the converter circuit generated by SoC Encounter. It
can be seen that the VCO, placed towards the left, is included the performance reduction resulting from automatic place-and-
in a different voltage island than the rest of the circuit. route. The results are summarized below.

C. Post layout verification A. Post synthesis evaluation

Design rule check (DRC) is run on the layout to verify its
conformance to the design rules. Layout vs. schematic (LVS)
check is performed to verify that the layout matches the post
place-and-route netlist. Parasitic extraction is performed on
the layout in order to extract the parasitic circuit elements
that result from placement and routing. The DRC, the LVS
as well as the parasitic extraction are performed using Mentor
Graphics Calibre in this work. The extracted netlist is subject to
post layout function and performance evaluation using Spectre.
The post synthesis netlist is simulated using Spectre at a
sample rate of 150 MHz. The spectra from a single tone test,
before and after digital correction, are shown in Fig. 5. The
spectra shows the functional correctness and the noise-shaping
property of the converter. The simulated dynamic performance
of the synthesized circuit over a signal bandwidth of 10 MHz,
while sampling at 150 MHz and converting a 1 MHz tone, is
summarized in Table I. An ENOB of 9.4 and an SFDR of 65.8
is obtained after digital correction.

IV. S IMULATION B. Post place-and-route evaluation

The netlist generated after logic synthesis as well as after The post place-and-route parasitic extracted netlist is sim-
place-and-route and parasitic extraction are simulated in order ulated using Spectre. The spectra of the converter output from
to verify the performance of the converter and to estimate a single tone test, before and after correction, are shown
 Before correction
0 NBW = 73.1 kHz in accuracy due to place-and-route amounts roughly to 0.5 bit
in ENOB (3 dB SNDR) and around 3 dB in SNR over a
−20
bandwidth of 10 MHz.
−40
PSD (dBFS/NBW)

V. C ONCLUSION
−60
Automated circuit and layout generation of all-digital
−80
mixed signal circuits is of interest due to reduction in design
cost and design time as well as due to better cross-technology
−100 portability. A time-mode all-digital analog-to-digital converter
is fully described in a digital HDL, and, is synthesized, placed
−120
10
5 6
10 10
7 and routed using a standard digital design flow in this work.
Frequency (Hz) A VCO-based ADC architecture is chosen for its inherent
After correction
noise shaping and anti-aliasing properties. A digital correction
0 NBW = 73.1 kHz block employing polynomial-fit estimation corrects for the
static VCO non-linearity, which is verified using a MATLAB
−20
model. The design flow employed to synthesize the ADC
−40
circuit is discussed. The circuit, when implemented using the
PSD (dBFS/NBW)

standard cell library in a 65 nm CMOS process, occupies an

−60 area of 0.009 mm2 . Parasitic extracted simulation of the post
place-and-route netlist shows that the converter delivers an
−80 ENOB of around 9 bits over a signal bandwidth of 10 MHz
while sampling at 150 MHz and consuming 1.2 mW of power
−100 from a 1.2 V supply. The performance drop due to automatic
placement and routing is around 0.5 bit of ENOB (3 dB
−120
10
5 6
10 10
7
SNDR) and around 3 dB of SNR. The result demonstrates the
Frequency (Hz)
feasibility of implementing scaling friendly, high performance
Fig. 6. Spectrum from the single tone test of the post place-and-route parasitic and low power ADCs using a digital design flow and standard
extracted circuit before and after digital correction. cells, by leveraging on time-mode techniques.

TABLE II. S IMULATED DYNAMIC PERFORMANCE AFTER R EFERENCES

PLACE - AND - ROUTE AND PARASITIC EXTRACTION
[1] M. Z. Straayer and M. H. Perrott, “A 12-Bit, 10-MHz Bandwidth,
Continuous-Time ΣΔ ADC With a 5-Bit, 950-MS/s VCO-Based Quan-
Performance Metric Correction OFF Correction ON
tizer,” IEEE J. Solid-State Circuits, vol. 43, no. 4, pp. 805–814, 2008.
Sample rate (MHz) 150 [2] J. Kim and S. Cho, “A Time-Based Analog-to-Digital Converter Using
OSR 7.5 7.5 a Multi-Phase Voltage Controlled Oscillator,” in Proc. IEEE Int. Symp.
Circuits and Systems ISCAS, 2006.
Bandwidth (MHz) 10 10
[3] C. S. Taillefer and G. W. Roberts, “Delta–Sigma A/D Conversion Via
ENOB 4.3 8.9 Time-Mode Signal Processing,” IEEE Trans. Circuits Syst. I, vol. 56,
SNDR (dB) 27.6 55.6 no. 9, pp. 1908–1920, 2009.
SNR (dB) 65.2 64.8
SFDR (dB) 30.5 60.9 [4] J. Daniels, W. Dehaene, and M. Steyaert, “All-Digital Differential
THD (dB) −27.6 −57.0 VCO-Based A/D Conversion,” in Proc. IEEE Int Circuits and Systems
(ISCAS) Symp, 2010, pp. 1085–1088.
Power (mW) 1.2
[5] G. Taylor and I. Galton, “A Mostly-Digital Variable-Rate Continuous-
Time Delta-Sigma Modulator ADC,” IEEE J. Solid-State Circuits,
vol. 45, no. 12, pp. 2634–2646, 2010.
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J. Silva-Martinez, C. Mishra, L. Chen, and E. J. Pankratz, “A Con-
same as those used in post synthesis simulation. The parasitic tinuous Time Multi-Bit ΔΣ ADC Using Time Domain Quantizer and
elements introduced due to place-and-route lead to a reduced Feedback Element,” IEEE J. Solid-State Circuits, vol. 46, no. 3, pp.
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The layout occupies an area of around 0.009 mm2 . The drop