Acer Extensa 2540 B5W11 LA-E061P LA-E061P 1.0-LA-D671P

A B C D E
1 1
Compal Confidential 2
B5W11 MB Schematic Document

LA-E061P
3 3
Rev: 1.0
2016.07.18
4 4
Security Classification
2016/07/18
Compal Secret Data
2016/11/10 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Sheet
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. B5W11 M/B LA-E061P
D at e : Monday, July 18, 2016 S h eet 1 of 44
I'm from VIETNAM

A B
- SuaLaptop365 C D E
A B C D E
HDMI Conn. eDP Fan Control

page 31
Interleaved Memory
page 19
page 22 page 21 Memory BUS
1
Dual Channel 1
260pin DDR4-SO-DIMM X2
eDP Intel Kabylake U 1.2V DDR4 1866/2133 page 20
DDI2
HDMI x 4 lanes DDI Kabylake U USB 2.0
Kabylake PCH-LP(MCP) USB 3.0 conn x2 CMOS Card Reader
(KBL-U_2+2) conn x1 USB port2,3 Camera RTS5170
USB port 1 Port3 on Sub/B USB port 7
SD only
USB port 8
page 24
Processor on Sub/B
NGFF
PCIe 1.0
WLAN 2.5G T/s Dual Core + GT2
2
USB port 5 LAN(GbE) 2
port 6 Flexible IO
page 28 page 28 page 21 page 28
SATA3.0 SATA3.0 48M H z

PCIe 1.0 USBx8
6.0 Gb/s 6.0 Gb/s
2.5G T/s port 7 port 8
port 5 (SATA0) (SATA1) 3.3V 24MHz
HD Audio
Touch
LAN(GbE) SATA HDD SATA CDROM 15W Screen
Realtek 8111H Conn. Conn. HDA Codec I2C (PORT1)
1356pin BGA USB port 6
page 23
page 07~18 SPI ALC233page 25 page 21
RJ45 conn. LPC/eSPI BUS

3
SPI ROM 3
page 26 page 26
CLK = 24M H z 64Mb page 9
Int. Speaker Int. AMIC UAJ
on Sub/B
page 23
ENE page 25 page 25 page 28
KB9022
page 29
RTC CKT. Sub Board

page 15 Touch Pad
LS-D671 Int.KBD PS2 (from EC) / I2C (from SOC)
IO/B
Power On/Of f CKT. page 28
page 30
page 30 page 30
4 DC/DC Interface CKT. 4
page 32
Security Classification Compal Secret Data Compal Electronics, Inc.

2016/07/18 2016/11/10 Title
Power Circuit DC/DC Issued Date Deciphered Date Block Diagrams
page 33~43 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
I'm from VIETNAM

A B
A B C D E
Board ID Table for AD channel

Vcc 3.3V +/- 5%
Ra 100K +/- 1% Power State
Board ID Rb V BI D min V BI D typ V BI D max EC AD3 PCB Revision SIGNAL
STATE SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
0 0 0 V 0 V 0.300 V 0x00 - 0x13 0.1
1 12K +/- 1% 0.347 V 0.345 V 0.360 V 0x14 - 0x1E 0.1 S0 (Full ON) HIGH HIGH HIGH ON ON ON ON
2 15K +/- 1% 0.423 V 0.430 V 0.438 V 0x1F - 0x25 S3 (Suspend to RAM) LOW HIGH HIGH ON ON OFF OFF
1
3 20K +/- 1% 0.541 V 0.550 V 0.559 V 0x26 - 0x30 1
4 27K +/- 1% 0.691 V 0.702 V 0.713 V 0x31 - 0x3A S4 (Suspend to Disk) LOW LOW HIGH ON OFF OFF OFF
5 33K +/- 1% 0.807 V 0.819 V 0.831 V 0x3B - 0x45 S5 (Soft OFF) LOW LOW LOW ON OFF OFF OFF
6 43K +/- 1% 0.978 V 0.992 V 1.006 V 0x46 - 0x54
7 56K +/- 1% 1.169 V 1.185 V 1.200 V 0x55 - 0x64
Voltage Rails
Power Plane Descrip t i o n S0 S3 S4/S5
+19V_VIN Adapter power supply N/A N/A N/A
+17.4V_BATT Battery power supply N/A N/A N/A
+19VB AC or battery power rail for power circuit. N/A N/A N/A
+VCC_COR E Processor IA Cores Power Rail ON O FF O FF
+VCC_G T Processor Graphics Power Rails ON O FF O FF
+VCC _ S A System Agent power rail ON O FF O FF
+0.6VS_VTT DDR +0.6VS power rail for DDR terminator . ON O FF O FF
+1.0VALW_PRIM +1.0V Always power rail ON ON ON*1

+1.0V_VCC S T U Sustain voltage for processor in Standby modes ON ON O FF
+VC C IO CPU IO power rail ON O FF O FF

2
BOM Structure Table +1.0VS_VCCS T G +1.0VALW_PRIM Gated version of VCCST ON O FF O FF
2
+1.2V_ V D D Q DDR4 +1.2V Power Rail ON ON O FF
BOM Option Table BOM Option Table +1.8VALW_PRIM +1.8V Always power rail ON ON ON*1
Item BOM Structure Item BOM Structure +1.8VS System +1.8V power rail ON O FF O FF
Unpop @ +3VLP +19VB to +3VLP power rail for suspend power ON ON ON
Connector CONN@ +3VALW System +3VALW always on power rail ON ON ON*1
For Acer BYOC BYO C@ SkyLake plat f or m SKL@ +3VS System +3V power rail ON O FF O FF
No Acer BYOC NBYOC@ KabyLake plat f or m KBL@ +5VALW +5V Always power rail ON ON ON
CODEC(ALC255) 255@ +5VS System +5V power rail ON O FF O FF
CODEC(ALC233) 233@ +RTCVC C RTC Battery Power ON ON ON
LPC MODE for EC LPC@

ESPI MODE for EC ESPI@
For Intel CMC CMC@
EMI requirement EMI@

EMI requirement depop @EMI@
ESD requirement ESD@
3 3
ESD requirement depop @ESD@ CPU Code QKJW@
LAN(8111GUS) 8111GUS@
LAN(8111H) 8111H@ Note : ON*1 means power plane is ON only when WOL enable and RTC wake at BIOS setting, otherwise it is OFF.
RF requirement RF@
43 level BOM table

43 Level Description BOM Structure
431A3EBOL01 SMT MB AE061 B5W11 QKJW HDMI
4 4
Security Classification Compal Secret Data

2016/07/18 2016/11/10 Tit le
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
Dat e : Monday, July 18, 2016 S heet 3 of 44
I'm from VIETNAM

A B
A B C D E
D RVO N
NCP81253MNTBG
+VCC_CORE
(PU9001)
NCP81151MNTBG
+VCC_GT R-Short
(PU9003) +TS_PWR
(RX8)
NCP81253MNTBG R-Short
(PU9004) +VCC_SA (RC208) +1.2V_VDDQC AP2330W
(UY1) +HDMI_5V_OUT
1
SYSO N JUMP JUMP R-Short
1
+1.2VP (PJ501) +1.2V_VDDQ (JPC1,JPC2) +1.2V_VDDQ_CPU (RC141) +1.2V_VCCSFR_OC R-Short

(RO3) +5VS_HDD
RT8207KGQW
SM_PG_CTR L (PU501) JUMP
ADAPTER +0.6VSP +0.6VS_VTT 0 ohm
(PJ502) +5VS_ODD
(RO2)
5V_ EN SUSP#
SY8286CRAC JUMP EM5209VF JUMP JUMP
(PU402) +5VALWP (PJ402) +5VALW (UQ1) +5VS_OUT (JPQ2) +5VS (JPA1) +VDDA
USB_EN
+19VB SY6288C20AAC R-Short
BATTERY (US21) +USB3_VCCA (RF1) +VCC_FAN1
SYSO N APL5336KAI R-Short

(PU502) +2.5VP (RC197) +3VALW_1.8VALW_PGPPA
3V_ EN SY8286BRAC JUMP R-Short R-Short
(PU401) +3VALWP (PJ401) +3VALW (RC173) +3VALW_DSW (RC161) +3VALW_PGPPB
CHARGER
JUMP R-Short
(JPC7) +3VALW_PRIM (RC163) +3VALW_PGPPC
LD O SYSO N APL5336KAI R-Short R-Short
2
(PU502) +2.5VP (RC172) +3VALW_1.8VALW_PGPPD (RC178) +1.8VS_3VS_PGPPA 2
+3VLP
LAN_PWR _ EN SY6288C20AAC R-Short 0 ohm
(UL1) +3V_LAN (RC167) +3VALW_PGPPE (RM1) +3VS_WLAN
TP_PWR_E N SY6288C20AAC R-Short R-Short
(UK1) +3V_PTP (RC187) +3VALW_PGPPG (RA2) +3VS_DVDDIO
W LAN _O N
SY6288C20AAC R-Short R-Short
(UM1) +3VS_WLAN (RC171) +3VALW_RTC (RA5) +3VS_DVDD
SUSP# SOC_ENVD D
EM5209VF JUMP SY6288C20AAC
(UQ1) +3VS_OUT (JPQ1) +3VS (UX1) +LCDVDD
SPO K SUSP#
G971ADJF11U JUMP EM5209VF R-Short
(PU702) +1.8VALWP (PJ702) +1.8VALW_PRIM (UC5) +1.8VS (RA6) +1.8VS_VDDA
EN_1VA LW SY8288RAC JUMP R-Short R-Short

(PU601) +1.0VALWP (PJ601) +1.0VALW_PRIM (RC148) +1.0VALW_APLL (RC209) +1.0VALW_MPHYGT
JUMP R-Short
3
(JPC9) +1.0VALW_MPHYPLL (RC149) +1.0VALW_AMPHYPLL 3
R-Short R-Short
(RC162) +1.0VALW_DTS (RC176) +1.0VALW_SRAM
R-Short R-Short
(RC169) +1.0VALW_CLK6_24TBT (RC156) +1.0VALW_APLLEBB
R-Short
(RC164) +1.0VALW_VCCCLK2
R-Short
+1.0VALW_CLK4_F100OC
(RC190)
R-Short
(RC152) +1.0VALW_CLK5_F24NS
R-Short R-Short
(RC175) +1.0VALW_MPHYAON (RC143) +1.0V_VCCSFR
SYSO N EM5209VF R-Short
(UC5) +1.0V_VCCSTU (RC140) +1.0V_VCCST
SUSP#
4
AOZ1336 R-Short 4
+1.0VS_VCCSTG_IO +1.0VS_VCCSTG
(UC8) (RC188)
JUMP
+VCCIO
(JPC5)

2016/07/18 2014/04/12 Title
Issued Date Deciphered Date Power Rail
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Docu ment Number Rev
I'm from VIETNAM - SuaLaptop365
Da te : Monday, July 18, 2016 Sh e e t 4 of 44
A B C D E
A B C D E
2. 2K 2. 2K
2. 2K
+3VALW_PRIM 2. 2K
+3VS
BH 10 SOC_SMB C LK
BG 12 SOC_SMBDATA 2N7002DW
1
Skylake SO-DIMM 2 1
SO C
SOC _S ML0C LK 4 99
4 99
+3VALW_PRIM
SOC_SML0DATA
2. 2K
2. 2K
+3VALW_PRIM
SOC _S ML1C LK
SOC_SML1DATA
2 2
2. 2K
2. 2K
+3VLP_EC
77 EC_SMB_C K 1 100 ohm 7

SCL1 BATTE RY
78 EC_SMB _D A1 100 ohm
SDA1 6
CONN
0 ohm EC_SMB_CK1_CHGR
12
0 ohm EC_SMB_DA1_CHGR
11 Charge r
KBC SCL2 79 SOC _S ML1C LK
SDA2 80 SOC_SML1DATA
3
KB9022 Need check
3
I2C Address Table

Address(8bit)
BUS Device Address(7 bit)
Write Read
I2C_0 (+3VS) Reserved (Touch Panel)
TM-P2969-001 (TP) 0x2C
I2C_1 (+3VS)
SB8787-1200 (TP-ELAN) 0x15
DIMM2 0xA4
SOC_SMBCLK +3VS
PCH-LP (SOC) 0x90
SOC_SML1CLK
+3VALW_PRIM
BQ24780 (Charger IC) 0x12

EC_SMB_CK1 +3VLP
4 BATTERY PACK 0x16 4
2016/07/18
Compal Secret Data
2016/11/10 Title
SMBUS_Routing_Table
I'm from VIETNAM

A B
A B C D E
PWR Sequence_SKL-U2+2_DDR3L_Value_NON CS
+RTCVCC
tPCH01_Min : 9 ms
SOC_RTCRST#
1 1
+19VB
+3V LP
EC_ON
tPCH04_Min : 9 ms
+5VALW /+3VALW (+3VALW _DS W...)
tPCH34_Max : 20 ms
SPOK tPCH06_Min : 200 us (+3VALW stable (@95% of full value) to +1.0VALW_PRIM starting to ramp)
+1.8VALW _P RIM
+1.8VALW _P G
+VCCPRIM_CORE/+1 .0VALW _P RIM

tPCH03_Min : 10 ms
EC_RSMRST#
ON/OFF
2
PBTN_OUT# tPCH43_Min : 95 ms 2
Minimum duration of PWRBTN# assertion = 16mS. PWRBTN# can assert before or after RSMRST#
PM_SLP_S 5 #
tPCH18_Min : 90 us
ESPI_RST#
PM_SLP_S 4 #
SYSO N
+1.0V_VCCST U
+1.2V_VDDQ
PM_SLP_S 3 #
SUSP #
tCPU04 Min : 100 ns
+1.0VS_VCCS T G
tCPU10 Min : 1 ms
+VCC IO
3 3
+5VS/+3V S /+1.8V S /+1.5V S
tCPU00 Min : 1 ms
EC_VCCST_P G
VR_ON
tCPU19 Max : 100 ns
SM_PG_CT RL
tCPU18 Max : 35 us
+0.6VS _ V T T
tCPU09 Min : 1 ms
+VCC_SA
VR_PW RGD
tCPU16 Min : 0 ns
PCH_PWROK (SYS_PWROK) tPLT05 Min : Platform dependent
H_CPUPW RG D
PLT_RST#
+VCC_CORE / +VCC_GT
4 4

Issued Date 2016/07/18 Deciphered Date 2016/11/10 Title
Power Sequence
Date: Monday, July 18, 2016 Sheet 6 of 44
A B C D E

A B C D E
1 1
UC1A SKL - U
Rev_0.53
E55 C47
F55 DDI1_TXN[0] EDP_TXN[0] C46 EDP_TXN0 <21>
E58 DDI1_TXP[0] EDP_TXP[0] D46 EDP_TXP0 <21>
F58 DDI1_TXN[1] EDP_TXN[1] C45 EDP_TXN1 <21>
DDI1_TXP[1] EDP_TXP[1] EDP_TXP1 <21>
F53 A45
G53 DDI1_TXN[2] EDP_TXN[2] B45 eDP
Funct i onal Str ap Def ini t i o
n
s F56 DDI1_TXP[2]
DDI1_TXN[3]
EDP_TXP[2]
EDP_TXN[3]
A47
G56 B47
DDI1_TXP[3] EDP_TXP[3]
#543016 PDG2.0 P.844 C50 E45
EDP_AUXN <21>
<22> SOC_DP2_N0 D50 DDI2_TXN[0] D DI E DP EDP_AUXN F45
DDPB_CTRLDATA <22> SOC_DP2_P0 C52 DDI2_TXP[0] EDP_AUXP EDP_AUXP <21>
<22> SOC_DP2_N1 DDI2_TXN[1]
DDPC_CTRLDATA <22> SOC_DP2_P1
D52
A50 DDI2_TXP[1] EDP_DISP_UTIL
B52
Display Port B/C Detected HDMI <22> SOC_DP2_N2 B50 DDI2_TXN[2] G50
<22> SOC_DP2_P2 D51 DDI2_TXP[2] DDI1_AUXN F50
NC =Port is not detected. <22> SOC_DP2_N3 C51 DDI2_TXN[3] DDI1_AUXP E48
<22> SOC_DP2_P3
PU =Port is detected. DDI2_TXP[3] DDI2_AUXN
DDI2_AUXP
F48
G46
DISPLAY SIDEBANDS DDI3_AUXN F46
L13 DDI3_AUXP +3VS
RC212
L12 GPP_E18/DDPB_CTRLCLK L9 10K_0402_5%
2
HDMI DDC (Port C) GPP_E19/DDPB_CTRLDATA GPP_E13/DDPB_HPD0 L7 SOC_DP2_HPD EC_SCI# 1 @ 2 2
SOC_DP2_CTRL_CLK N7 GPP_E14/DDPC_HPD1 L6
SOC_DP2_HPD <22> From HDMI
<22> SOC_DP2_CTRL_CLK SOC_DP2_CTRL_DATA N8 GPP_E20/DDPC_CTRLCLK GPP_E15/DDPD_HPD2 N9 EC_SCI#
<22> SOC_DP2_CTRL_DATA GPP_E21/DDPC_CTRLDATA GPP_E16/DDPE_HPD3 L10 CPU_EDP_HPD EC_SCI# <29>
CPU_EDP_HPD <21> From eDP EC_SCI# SOC internal PU
+VCCIO N11 GPP_E17/EDP_HPD
N12 GPP_E22/DDPD_CTRLCLK R12 ENBKL
GPP_E23/DDPD_CTRLDATA EDP_BKLTEN SOC_BKL_PWM ENBKL <29>
R11
RC1 1 2 24.9_0402_1% EDP_COMP EDP_COMP E52 1 OF 20 EDP_BKLTCTL U13 SOC_ENVDD SOC_BKL_PWM <21> #545659 PCH EDS1.51 P.131
EDP_RCOMP EDP_VDDEN SOC_ENVDD <21> SCI capability is available on all GPIOs, while
SKL-U_BGA1356 NMI and SMI capability is available on only
#543016 PDG2.0 P.225 @ select GPIOs.
COMPENSATION PU for eDP Below are the PCH GPIOs that can be
Trace width=5 mils,Spacing=25mil,Max length=600mils routed to generate SMI# or NMI:
‧ GPP_B14, GPP_B20, GPP_B23
‧ GPP_C [ 23 : 22 ]
+1.0V_VCCST #543016 PDG2.0 P.857 ‧ GPP_ D [ 4 : 0 ]
PU 1K to VCCST +1.0VS_VCCSTG ‧ GPP_E [ 8 : 0 ] , GPP_E [ 16 : 13 ]
1
RC2 1 2 1K_0402_5% H_THERMTRIP#

Reserved CATERR# for
RC3 UC1D SKL - U
1K_0402_5%
sight i ngs i ss ue c heck Rev_0.53 @ESD@ CC81
RC4 H_CATERR# D63 .1U_0402_16V7K
@ T166 H_PECI CATERR# SOC_XDP_TRST#
+3VS 499_0402_1% A54 1 2
<29> H_PECI
2
1 2 H_PROCHOT#_R C65 PECI

<29> H_PROCHOT# H_THERMTRIP# C63 PROCHOT# J TA G
1 2 100K_0402_5% TP_INT# A65 THERMTRIP# B61 CPU_XDP_TCK0

RC157 @
SKTOCC# PROC_TCK D60 SOC_XDP_TDI
CPU MISC PROC_TDI
XDP_BPM#0 C55 A61 SOC_XDP_TDO
@ T160 XDP_BPM#1 BPM#[0] PROC_TDO SOC_XDP_TMS
@ T161 D55 C60
3 B54 BPM#[1] PROC_TMS B59 SOC_XDP_TRST# 3
BPM#[2] PROC_TRST# T194 @
RC9 1 2 100K_0402_5% C56
+3VS BPM#[3] PCH_JTAG_TCK1
B56 T195 @
CC52 @ESD@ I2C_TS_INT# A6 PCH_JTAG_TCK D59 SOC_XDP_TDI
SPI touch INT follow CRB <21> I2C_TS_INT#
A7 GPP_E3/CPU_GP0 PCH_JTAG_TDI A56 SOC_XDP_TDO
.1U_0402_16V7K @
2 1 H_PECI RB751V-40_SOD323-2 1 2 DC2 TP_INT# BA5 GPP_E7/CPU_GP1 PCH_JTAG_TDO C59 SOC_XDP_TMS
<29,30> EC_TP_INT# AY5 GPP_B3/CPU_GP2 PCH_JTAG_TMS C61 SOC_XDP_TRST#
CC53 @ESD@ RC137 2 1 0_0402_5% GPP_B4/CPU_GP3 PCH_TRST# A59 CPU_XDP_TCK0
JTAGX
.1U_0402_16V7K RC5 2 1 49.9_0402_1% CPU_POPIRCOMP AT16
H_PROCHOT#_R PROC_POPIRCOMP
2 1 RC6 2 1 49.9_0402_1% PCH_OPIRCOMP AU16
RC7 2 1 49.9_0402_1% EDRAM_OPIO_RCOMP H66 PCH_OPIRCOMP
2 1 EOPIO_RCOMP H65 OPCE_RCOMP
RC8 49.9_0402_1%
OPC_RCOMP
4 OF 20
SKL-U_BGA1356
#543016 PDG2.0 P.873 @
PROC_POPIRCOM P/PCH_OPIRCOMP
For Intel debug, place to CPU side. PD 50ohm
+1.0VS_VCCSTG
#543016 PDG2.0 P.629
#544669 CRB1.1 P.52
RC11 2 CMC@ 1 51_0402_5% SOC_XDP_TMS EDRAM_OPIO_RCOMP/EOPIO_RCOM P
PD 50ohm
RC13 2 CMC@ 1 51_0402_5% SOC_XDP_TDI
RC15 2 CMC@ 1 100_0402_5% SOC_XDP_TDO

CPU side
RC17 2 CMC@ 1 100_0402_5% SOC_XDP_TDO
CMC side
RC35 2 CMC@ 1 51_0402_5% CPU_XDP_TCK0
4 4

SKL-U(1/12)DDI,MSIC,XDP,EDP
A B C D E

A B C D E
Interleaved Memory
SKL - U
UC1B SKL - U UC1C
Rev_0.53 Rev_0.53
AU53 DDR_A_CLK#0
<19> DDR_A_D[0..15] DDR_A_D0 DDR0_CKN[0] DDR_A_CLK0 DDR_A_CLK#0 <19> <20> DDR_B_D[0..15] DDR_B_D0 DDR_B_CLK#0
AL71 AT53 AF65 AN45
1 DDR_A_D1 DDR0_DQ[0] DDR0_CKP[0] DDR_A_CLK#1 DDR_A_CLK0 <19> DDR_B_D1 DDR1_DQ[0]/DDR0_DQ[16] DDR1_CKN[0] DDR_B_CLK#1 DDR_B_CLK#0 <20> 1
AL68 AU55 AF64 AN46
DDR_A_D2 DDR0_DQ[1] DDR0_CKN[1] DDR_A_CLK1 DDR_A_CLK#1 <19> DDR_B_D2 DDR1_DQ[1]/DDR0_DQ[17] DDR1_CKN[1] DDR_B_CLK0 DDR_B_CLK#1 <20>
AN68 AT55 AK65 AP45
DDR_A_D3 DDR0_DQ[2] DDR0_CKP[1] DDR_A_CLK1 <19> DDR_B_D3 DDR1_DQ[2]/DDR0_DQ[18] DDR1_CKP[0] DDR_B_CLK1 DDR_B_CLK0 <20>
AN69 AK64 AP46
DDR_A_D4 DDR0_DQ[3] DDR_A_CKE0 DDR_B_D4 DDR1_DQ[3]/DDR0_DQ[19] DDR1_CKP[1] DDR_B_CLK1 <20>
AL70 BA56 AF66
DDR_A_D5 DDR0_DQ[4] DDR0_CKE[0] DDR_A_CKE1 DDR_A_CKE0 <19> DDR_B_D5 DDR1_DQ[4]/DDR0_DQ[20] DDR_B_CKE0
AL69 BB56 AF67 AN56
DDR_A_D6 DDR0_DQ[5] DDR0_CKE[1] DDR_A_CKE1 <19> DDR_B_D6 DDR1_DQ[5]/DDR0_DQ[21] DDR1_CKE[0] DDR_B_CKE1 DDR_B_CKE0 <20>
AN70 AW56 AK67 AP55
DDR_A_D7 DDR0_DQ[6] DDR0_CKE[2] @ T14 DDR_B_D7 DDR1_DQ[6]/DDR0_DQ[22] DDR1_CKE[1] DDR_B_CKE1 <20>
AN71 AY56 AK66 AN55
DDR_A_D8 DDR0_DQ[7] DDR0_CKE[3] @ T15 DDR_B_D8 DDR1_DQ[7]/DDR0_DQ[23] DDR1_CKE[2] @ T17
AR70 AF70 AP53
DDR_A_D9 DDR0_DQ[8] DDR_A_CS#0 DDR_B_D9 DDR1_DQ[8]/DDR0_DQ[24] DDR1_CKE[3] @ T18
AR68 AU45 AF68
DDR_A_D10 DDR0_DQ[9] DDR0_CS#[0] DDR_A_CS#1 DDR_A_CS#0 <19> DDR_B_D10 DDR1_DQ[9]/DDR0_DQ[25] DDR_B_CS#0
AU71 AU43 AH71 BB42
DDR_A_D11 DDR0_DQ[10] DDR0_CS#[1] DDR_A_ODT0 DDR_A_CS#1 <19> DDR_B_D11 DDR1_DQ[10]/DDR0_DQ[26] DDR1_CS#[0] DDR_B_CS#1 DDR_B_CS#0 <20>
AU68 AT45 AH68 AY42
DDR_A_D12 DDR0_DQ[11] DDR0_ODT[0] DDR_A_ODT1 DDR_A_ODT0 <19> DDR_B_D12 DDR1_DQ[11]/DDR0_DQ[27] DDR1_CS#[1] DDR_B_ODT0 DDR_B_CS#1 <20>
AR71 AT43 AF71 BA42
DDR_A_D13 DDR0_DQ[12] DDR0_ODT[1] DDR_A_ODT1 <19> DDR_B_D13 DDR1_DQ[12]/DDR0_DQ[28] DDR1_ODT[0] DDR_B_ODT1 DDR_B_ODT0 <20>
AR69 AF69 AW42
DDR_A_D14 DDR0_DQ[13] DDR_A_MA5 DDR_B_D14 DDR1_DQ[13]/DDR0_DQ[29] DDR1_ODT[1] DDR_B_ODT1 <20>
AU70 BA51 AH70
DDR_A_D15 DDR0_DQ[14] DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] DDR_A_MA9 DDR_A_MA5 <19> DDR_B_D15 DDR1_DQ[14]/DDR0_DQ[30] DDR_B_MA5
AU69 BB54 AH69 AY48
<19> DDR_A_D[16..31] DDR_A_D16 DDR0_DQ[15] DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] DDR_A_MA6 DDR_A_MA9 <19> <20> DDR_B_D[16..31] DDR_B_D16 DDR1_DQ[15]/DDR0_DQ[31] DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] DDR_B_MA9 DDR_B_MA5 <20>
BB65 BA52 AT66 AP50
DDR_A_D17 DDR0_DQ[16]/DDR0_DQ[32] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] DDR_A_MA8 DDR_A_MA6 <19> DDR_B_D17 DDR1_DQ[16]/DDR0_DQ[48] DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9] DDR_B_MA6 DDR_B_MA9 <20>
AW65 AY52 AU66 BA48
DDR_A_D18 DDR0_DQ[17]/DDR0_DQ[33] DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8] DDR_A_MA7 DDR_A_MA8 <19> DDR_B_D18 DDR1_DQ[17]/DDR0_DQ[49] DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6] DDR_B_MA8 DDR_B_MA6 <20>
AW63 AW52 AP65 BB48
DDR_A_D19 DDR0_DQ[18]/DDR0_DQ[34] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7] DDR_A_BG0 DDR_A_MA7 <19> DDR_B_D19 DDR1_DQ[18]/DDR0_DQ[50] DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8] DDR_B_MA7 DDR_B_MA8 <20>
AY63 AY55 AN65 AP48
DDR_A_D20 DDR0_DQ[19]/DDR0_DQ[35] DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0] DDR_A_MA12 DDR_A_BG0 <19> DDR_B_D20 DDR1_DQ[19]/DDR0_DQ[51] DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7] DDR_B_BG0 DDR_B_MA7 <20>
BA65 AW54 AN66 AP52
DDR_A_D21 DDR0_DQ[20]/DDR0_DQ[36] DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] DDR_A_MA11 DDR_A_MA12 <19> DDR_B_D21 DDR1_DQ[20]/DDR0_DQ[52] DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0] DDR_B_MA12 DDR_B_BG0 <20>
AY65 BA54 AP66 AN50
DDR_A_D22 DDR0_DQ[21]/DDR0_DQ[37] DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11] DDR_A_ACT# DDR_A_MA11 <19> DDR_B_D22 DDR1_DQ[21]/DDR0_DQ[53] DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12] DDR_B_MA11 DDR_B_MA12 <20>
BA63 BA55 AT65 AN48
DDR_A_D23 DDR0_DQ[22]/DDR0_DQ[38] DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# DDR_A_BG1 DDR_A_ACT# <19> DDR_B_D23 DDR1_DQ[22]/DDR0_DQ[54] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11] DDR_B_ACT# DDR_B_MA11 <20>
BB63 AY54 AU65 AN53
DDR_A_D24 DDR0_DQ[23]/DDR0_DQ[39] DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1] DDR_A_BG1 <19> DDR_B_D24 DDR1_DQ[23]/DDR0_DQ[55] DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT# DDR_B_BG1 DDR_B_ACT# <20>
BA61 AT61 AN52
DDR_A_D25 DDR0_DQ[24]/DDR0_DQ[40] DDR_A_MA13 DDR_B_D25 DDR1_DQ[24]/DDR0_DQ[56] DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1] DDR_B_BG1 <20>
AW61 AU46 AU61
DDR_A_D26 DDR0_DQ[25]/DDR0_DQ[41] DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13] DDR_A_MA15 DDR_A_MA13 <19> DDR_B_D26 DDR1_DQ[25]/DDR0_DQ[57] DDR_B_MA13
BB59 AU48 AP60 BA43
DDR_A_D27 DDR0_DQ[26]/DDR0_DQ[42] DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15] DDR_A_MA14 DDR_A_MA15 <19> DDR_B_D27 DDR1_DQ[26]/DDR0_DQ[58] DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13] DDR_B_MA15 DDR_B_MA13 <20>
AW59 AT46 AN60 AY43
DDR_A_D28 DDR0_DQ[27]/DDR0_DQ[43] DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14] DDR_A_MA16 DDR_A_MA14 <19> DDR_B_D28 DDR1_DQ[27]/DDR0_DQ[59] DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15] DDR_B_MA14 DDR_B_MA15 <20>
BB61 AU50 AN61 AY44
DDR_A_D29 DDR0_DQ[28]/DDR0_DQ[44] DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16] DDR_A_BA0 DDR_A_MA16 <19> DDR_B_D29 DDR1_DQ[28]/DDR0_DQ[60] DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14] DDR_B_MA16 DDR_B_MA14 <20>
AY61 AU52 AP61 AW44
DDR_A_D30 DDR0_DQ[29]/DDR0_DQ[45] DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0] DDR_A_MA2 DDR_A_BA0 <19> DDR_B_D30 DDR1_DQ[29]/DDR0_DQ[61] DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16] DDR_B_BA0 DDR_B_MA16 <20>
BA59 AY51 AT60 BB44
DDR_A_D31 DDR0_DQ[30]/DDR0_DQ[46] DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2] DDR_A_BA1 DDR_A_MA2 <19> DDR_B_D31 DDR1_DQ[30]/DDR0_DQ[62] DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0] DDR_B_MA2 DDR_B_BA0 <20>
AY59 AT48 AU60 AY47
<19> DDR_A_D[32..47] DDR_A_D32 DDR0_DQ[31]/DDR0_DQ[47] DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1] DDR_A_MA10 DDR_A_BA1 <19> <20> DDR_B_D[32..47] DDR_B_D32 DDR1_DQ[31]/DDR0_DQ[63] DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2] DDR_B_BA1 DDR_B_MA2 <20>
AY39 AT50 AU40 BA44
2 DDR_A_D33 DDR0_DQ[32]/DDR1_DQ[0] DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10] DDR_A_MA1 DDR_A_MA10 <19> DDR_B_D33 DDR1_DQ[32]/DDR1_DQ[16] DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1] DDR_B_MA10 DDR_B_BA1 <20> 2
AW39 BB50 AT40 AW46
DDR_A_D34 DDR0_DQ[33]/DDR1_DQ[1] DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] DDR_A_MA0 DDR_A_MA1 <19> DDR_B_D34 DDR1_DQ[33]/DDR1_DQ[17] DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10] DDR_B_MA1 DDR_B_MA10 <20>
AY37 AY50 AT37 AY46
DDR_A_D35 DDR0_DQ[34]/DDR1_DQ[2] DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0] DDR_A_MA3 DDR_A_MA0 <19> DDR_B_D35 DDR1_DQ[34]/DDR1_DQ[18] DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] DDR_B_MA0 DDR_B_MA1 <20>
AW37 BA50 AU37 BA46
DDR_A_D36 DDR0_DQ[35]/DDR1_DQ[3] DDR0_MA[3] DDR_A_MA4 DDR_A_MA3 <19> DDR_B_D36 DDR1_DQ[35]/DDR1_DQ[19] DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0] DDR_B_MA3 DDR_B_MA0 <20>
BB39 BB52 AR40 BB46
DDR_A_D37 DDR0_DQ[36]/DDR1_DQ[4] DDR0_MA[4] DDR_A_MA4 <19> DDR_B_D37 DDR1_DQ[36]/DDR1_DQ[20] DDR1_MA[3] DDR_B_MA4 DDR_B_MA3 <20>
BA39 AP40 BA47
DDR_A_D38 DDR0_DQ[37]/DDR1_DQ[5] DDR_A_DQS#0 DDR_B_D38 DDR1_DQ[37]/DDR1_DQ[21] DDR1_MA[4] DDR_B_MA4 <20>
BA37 AM70 AP37
DDR_A_D39 DDR0_DQ[38]/DDR1_DQ[6] DDR0_DQSN[0] DDR_A_DQS0 DDR_A_DQS#0 <19> DDR_B_D39 DDR1_DQ[38]/DDR1_DQ[22] DDR_B_DQS#0
BB37 AM69 AR37 AH66
DDR_A_D40 DDR0_DQ[39]/DDR1_DQ[7] DDR0_DQSP[0] DDR_A_DQS#1 DDR_A_DQS0 <19> DDR_B_D40 DDR1_DQ[39]/DDR1_DQ[23] DDR1_DQSN[0]/DDR0_DQSN[2] DDR_B_DQS0 DDR_B_DQS#0 <20>
AY35 AT69 AT33 AH65
DDR_A_D41 DDR0_DQ[40]/DDR1_DQ[8] DDR0_DQSN[1] DDR_A_DQS1 DDR_A_DQS#1 <19> DDR_B_D41 DDR1_DQ[40]/DDR1_DQ[24] DDR1_DQSP[0]/DDR0_DQSP[2] DDR_B_DQS#1 DDR_B_DQS0 <20>
AW35 AT70 AU33 AG69
DDR_A_D42 DDR0_DQ[41]/DDR1_DQ[9] DDR0_DQSP[1] DDR_A_DQS#2 DDR_A_DQS1 <19> DDR_B_D42 DDR1_DQ[41]/DDR1_DQ[25] DDR1_DQSN[1]/DDR0_DQSN[3] DDR_B_DQS1 DDR_B_DQS#1 <20>
AY33 BA64 AU30 AG70
DDR_A_D43 DDR0_DQ[42]/DDR1_DQ[10] DDR0_DQSN[2]/DDR0_DQSN[4] DDR_A_DQS2 DDR_A_DQS#2 <19> DDR_B_D43 DDR1_DQ[42]/DDR1_DQ[26] DDR1_DQSP[1]/DDR0_DQSP[3] DDR_B_DQS#2 DDR_B_DQS1 <20>
AW33 AY64 AT30 AR66
DDR_A_D44 DDR0_DQ[43]/DDR1_DQ[11] DDR0_DQSP[2]/DDR0_DQSP[4] DDR_A_DQS#3 DDR_A_DQS2 <19> DDR_B_D44 DDR1_DQ[43]/DDR1_DQ[27] DDR1_DQSN[2]/DDR0_DQSN[6] DDR_B_DQS2 DDR_B_DQS#2 <20>
BB35 AY60 AR33 AR65
BA35 BA60 AP33 AR61
DDR_A_D46 DDR0_DQ[45]/DDR1_DQ[13] DDR0_DQSP[3]/DDR0_DQSP[5] DDR_A_DQS#4 DDR_A_DQS3 <19> DDR_B_D46 DDR1_DQ[45]/DDR1_DQ[29] DDR1_DQSN[3]/DDR0_DQSN[7] DDR_B_DQS3 DDR_B_DQS#3 <20>
BA33 BA38 AR30 AR60
BB33 AY38 AP30 AT38
<19> DDR_A_D[48..63] DDR_A_D48 DDR0_DQ[47]/DDR1_DQ[15] DDR0_DQSP[4]/DDR1_DQSP[0] DDR_A_DQS#5 DDR_A_DQS4 <19> <20> DDR_B_D[48..63] DDR_B_D48 DDR1_DQ[47]/DDR1_DQ[31] DDR1_DQSN[4]/DDR1_DQSN[2] DDR_B_DQS4 DDR_B_DQS#4 <20>
AY31 AY34 AU27 AR38
DDR_A_D49 DDR0_DQ[48]/DDR1_DQ[32] DDR0_DQSN[5]/DDR1_DQSN[1] DDR_A_DQS5 DDR_A_DQS#5 <19> DDR_B_D49 DDR1_DQ[48] DDR1_DQSP[4]/DDR1_DQSP[2] DDR_B_DQS#5 DDR_B_DQS4 <20>
AW31 BA34 AT27 AT32
DDR_A_D50 DDR0_DQ[49]/DDR1_DQ[33] DDR0_DQSP[5]/DDR1_DQSP[1] DDR_A_DQS#6 DDR_A_DQS5 <19> DDR_B_D50 DDR1_DQ[49] DDR1_DQSN[5]/DDR1_DQSN[3] DDR_B_DQS5 DDR_B_DQS#5 <20>
AY29 BA30 AT25 AR32
DDR_A_D51 DDR0_DQ[50]/DDR1_DQ[34] DDR0_DQSN[6]/DDR1_DQSN[4] DDR_A_DQS6 DDR_A_DQS#6 <19> DDR_B_D51 DDR1_DQ[50] DDR1_DQSP[5]/DDR1_DQSP[3] DDR_B_DQS#6 DDR_B_DQS5 <20>
AW29 AY30 AU25 AR25
DDR_A_D52 DDR0_DQ[51]/DDR1_DQ[35] DDR0_DQSP[6]/DDR1_DQSP[4] DDR_A_DQS#7 DDR_A_DQS6 <19> DDR_B_D52 DDR1_DQ[51] DDR1_DQSN[6] DDR_B_DQS6 DDR_B_DQS#6 <20>
BB31 AY26 AP27 AR27
DDR_A_D53 DDR0_DQ[52]/DDR1_DQ[36] DDR0_DQSN[7]/DDR1_DQSN[5] DDR_A_DQS7 DDR_A_DQS#7 <19> DDR_B_D53 DDR1_DQ[52] DDR1_DQSP[6] DDR_B_DQS#7 DDR_B_DQS6 <20>
BA31 BA26 AN27 AR22
DDR_A_D54 DDR0_DQ[53]/DDR1_DQ[37] DDR0_DQSP[7]/DDR1_DQSP[5] DDR_A_DQS7 <19> DDR_B_D54 DDR1_DQ[53] DDR1_DQSN[7] DDR_B_DQS7 DDR_B_DQS#7 <20>
BA29 AN25 AR21
DDR_A_D55 DDR0_DQ[54]/DDR1_DQ[38] DDR_A_ALERT# DDR_B_D55 DDR1_DQ[54] DDR1_DQSP[7] DDR_B_DQS7 <20>
BB29 AW50 AP25
DDR_A_D56 DDR0_DQ[55]/DDR1_DQ[39] DDR0_ALERT# DDR_A_PAR DDR_A_ALERT# <19> DDR_B_D56 DDR1_DQ[55] DDR_B_ALERT#
AY27 AT52 AT22 AN43
DDR_A_D57 DDR0_DQ[56]/DDR1_DQ[40] DDR0_PAR DDR_A_PAR <19> DDR_B_D57 DDR1_DQ[56] DDR1_ALERT# DDR_B_PAR DDR_B_ALERT# <20>
AW27 AU22 AP43
DDR_A_D58 DDR0_DQ[57]/DDR1_DQ[41] +0.6V_A_VREFCA DDR_B_D58 DDR1_DQ[57] DDR1_PAR DDR_B_PAR <20>
AY25 AY67 AU21 AT13
DDR_A_D59 DDR0_DQ[58]/DDR1_DQ[42] DDR_VREF_CA +0.6V_A_VREFCA DDR_B_D59 DDR1_DQ[58] DRAM_RESET# DDR_DRAMRST# <19,20>
AW25 AY68 AT21 AR18
DDR_A_D60 BB27 DDR0_DQ[59]/DDR1_DQ[43] DDR CH - A
DDR0_VREF_DQ BA67 +0.6V_B_VREFCA DDR_B_D60 AN22 DDR1_DQ[59] DDR_RCOMP[0] AT18 SM_RCOMP0
DDR_A_D61 DDR0_DQ[60]/DDR1_DQ[44] DDR1_VREF_DQ +0.6V_B_VREFCA DDR_B_D61 DDR1_DQ[60] DDR CH - B DDR_RCOMP[1] SM_RCOMP1
BA27 AP22 AU18
DDR_A_D62 BA25 DDR0_DQ[61]/DDR1_DQ[45] AW67 DDR_PG_CTRL DDR_B_D62 AP21 DDR1_DQ[61] DDR_RCOMP[2] SM_RCOMP2
DDR_A_D63 BB25 DDR0_DQ[62]/DDR1_DQ[46] DDR_VTT_CNTL #543016 PDG2.0 P.190 DDR_B_D63 AN21 DDR1_DQ[62]
DDR0_DQ[63]/DDR1_DQ[47] 2 OF 20 Trace width/Spacing >= 20mils DDR1_DQ[63] 3 OF 20
3 Place componment near SODIMM 3
SKL-U_BGA1356 SKL-U_BGA1356
@ @
ZZZ
+1.2V_VDDQ
SM_RCOMP0 RC38 1 2 121_0402_1%
+3VS SM_RCOMP1 RC39 1 2 80.6_0402_1%
PCB B5W11 LA-E061P LS-D671P SM_RCOMP2 RC40 1 2 100_0402_1%
DAZ1P500100
.1U_0402_16V7K 2 1 CC57
1
UC7 RC10
#543016 PDG2.0 P.139
ES Sample 1 5 100K_0402_5%
W=12-15 Space= 20/25 L=500mil
NC VCC
UC1 DDR_PG_CTRL 2 @ESD@
2
A 4 DDR_DRAMRST# CC70 1 2 .1U_0402_16V7K

3 Y SM_PG_CTRL <37>
GND
2
74AUP1G07GW_TSSOP5 DDR_VTT_CNTL to DDR

RC16 2015MOW02, Can't install Cap on DRAMRST
CPU_G0 2.6G @ 1M_0402_5% VTT supplied ramped
QKJW@
Change PN to SA00007UR00. <35uS
SA00009UR10 (tCPU18)
1
4 4

SKL-U(2/12)DDR4
A B C D E

A B C D E
+3VS
SOC_SMBCLK_1 RC222 1 2 2.2K_0402_5%
SOC_SMBDATA_1RC223 1 2 2.2K_0402_5%
+3VALW_PRIM
SOC_SML0CLK RC49 1 2 499_0402_1%
SOC_SML0DATA RC50 1 2 499_0402_1%
1 1
RPC7
SOC_SML1CLK 1 8
SOC_SML1DATA 2 7
SOC_SMBCLK 3 6
SOC_SMBDATA 4 5
SKL - U
UC1E 2.2K_0804_8P4R_5%
SPI - FLASH +3VS
SMBUS, SMLINK
SOC_SPI_CLK AV2
SOC_SPI_SO AW3 SPI0_CLK R7 SOC_SMBCLK
SOC_SPI_SI AV3 SPI0_MISO GPP_C0/SMBCLK R8 SOC_SMBDATA
SPI0_MOSI GPP_C1/SMBDATA SMB (to DDR, G sensor)
5
SOC_SPI_IO2 AW2 R10 SOC_SMBALERT#
SPI ROM
G
SOC_SPI_IO3 SPI0_IO2 GPP_C2/SMBALERT# @ T239
AU4 QC2B
SOC_SPI_CS#0 AU3 SPI0_IO3 R9 SOC_SML0CLK +3VALW_PRIM
Strap Pin 2N7002KDW_SOT363-6
AU2 SPI0_CS0# GPP_C3/SML0CLK W2 SOC_SML0DATA
AU1 SPI0_CS1# GPP_C4/SML0DATA W1 SOC_SML0ALERT# 4.7K_0402_5% 2 ESPI@ 1 RC202 SOC_SMBCLK 3 4 SOC_SMBCLK_1
S
SPI0_CS2# GPP_C5/SML0ALERT# SOC_SMBCLK_1 <19,20>
2
W3 SOC_SML1CLK
G
SPI - TOUCH GPP_C6/SML1CLK SOC_SML1DATA SOC_SML1CLK <29>
V3 QC2A
M2 GPP_C7/SML1DATA AM7 SOC_SML1ALERT# SOC_SML1DATA <29> SML 1 ( to EC, Thermal sensor)
@ T234 2N7002KDW_SOT363-6
M3 GPP_D1/SPI1_CLK GPP_B23/SML1ALERT#/PCHHOT#
J4 GPP_D2/SPI1_MISO SOC_SMBDATA 6 1 SOC_SMBDATA_1
SOC_SMBDATA_1 <19,20>
S
V1 GPP_D3/SPI1_MOSI
D
SPI Touch V2 GPP_D21/SPI1_IO2
Change RC144~RC147, RC45 to 15ohm when use ESPI
M1 GPP_D22/SPI1_IO3
GPP_D0/SPI1_CS#
LP C
AY13 LPC_AD0 RC144 1 @ 2 0_0402_5%
ESPI / LPC Bus
GPP_A1/LAD0/ESPI_IO0 BA13 LPC_AD1 1 2 LPC_AD0_R <29>
RC145 @ 0_0402_5% ESPI : +1.8V
C LINK GPP_A2/LAD1/ESPI_IO1 LPC_AD2 LPC_AD1_R <29>
BB13 RC146 1 @ 2 0_0402_5%
G3
G2 CL_CLK
GPP_A3/LAD2/ESPI_IO2
GPP_A4/LAD3/ESPI_IO3
AY12
BA12
LPC_AD3
LPC_FRAME#
RC147 1 @ 2 0_0402_5%
LPC_AD2_R
LPC_AD3_R
<29>
<29> * LPC : +3.3V +1.8VS_3VS_PGPPA
2 G1 CL_DATA GPP_A5/LFRAME#/ESPI_CS# BA11 ESPI_RST# LPC_FRAME# <29> 2
CL_RST# GPP_A14/SUS_STAT#/ESPI_RESET# ESPI_RST# <29>
PM_CLKRUN# RC107 1 2 10K_0402_5%
EC_KBRST#_R AW13 AW9 CLKOUT_LPC0 RC45 2 LPC@ 1 22_0402_5%
<29> EC_KBRST#_R GPP_A0/RCIN# GPP_A9/CLKOUT_LPC0/ESPI_CLK CLK_LPC_EC <29> To EC TPM_SERIRQ
AY9 RC112 1 2 10K_0402_5%
TPM_SERIRQ AY11 GPP_A10/CLKOUT_LPC1 AW11 PM_CLKRUN#
<29> TPM_SERIRQ GPP_A6/SERIRQ GPP_A8/CLKRUN#
5 OF 20
LPC Mode
SKL-U_BGA1356
@
SML0ALERT# / GPP_C5 (Internal Pull Down):
(Sampled: Rising edge of RSMRST# )
eSPI or LPC
*0 = LPC is selected for EC --> For KB9022/9032 Use
1 = eSPI is selected for EC --> For KB9032 Only.
SMBALERT# / GPP_C2 (Internal Pull Down):
(Sampled: Rising edge of RSMRST# )
+3VALW_SPI
SPI ROM ( 8MByte ) CC8
.1U_0402_16V7K
TLS Conf i dent ial i ty
SOC_SPI_CS#0 1
UC2
8
1 2 * 0 = Disable Intel ME Crypto Transport Layer Security
SOC_SPI_SO_0_R 2 /CS VCC 7 SOC_SPI_IO3_0_R (TLS) cipher suite (no conf i dent ial i ty).
SOC_SPI_IO2_0_R DO(IO1) /HOLD(IO3) SOC_SPI_CLK_0_R
3
4 /WP(IO2) CLK
6
5 SOC_SPI_SI_0_R
1 = Enable Intel ME Crypto (TLS) (with conf i dent ial i ty).
3
RPC5 and RC52 are close UC2 GND DI(IO0) Must be pulled up to support Intel AMT with TLS and Intel 3
RPC5
SOC_SPI_IO3 8 1 SOC_SPI_IO3_0_R
W25Q64FVSSIQ_SO8 2015MOW06 no need PU1K on SPI_IO2/IO3 SBA (Small Business Advantage) with TLS.
SOC_SPI_SI 7 2 SOC_SPI_SI_0_R +3VALW_SPI
SOC_SPI_CLK 6 3 SOC_SPI_CLK_0_R
SOC_SPI_SO 5 4 SOC_SPI_SO_0_R SOC_SPI_CLK_0_R 1 @EMI@ 2 1 2
RC24 0_0402_5% CC9 @EMI@ SOC_SPI_IO2 RC47 1 @ 2 1K_0402_1%
15_0804_8P4R_5% 10P_0402_50V8J
SOC_SPI_IO3 RC48 1 @ 2 1K_0402_1%
SOC_SPI_IO2 2 1 SOC_SPI_IO2_0_R
RC52 15_0402_5%
+3VALW_SPI
ROM Socket, co-lay with UC2.
JC1
SOC_SPI_CS#0 1 8
SOC_SPI_IO2_0_R 3 CS# VCC 6 SOC_SPI_CLK_0_R
SOC_SPI_IO3_0_R 7 WP# SCLK 5 SOC_SPI_SI_0_R
4 HOLD# SI/SIO0 2 SOC_SPI_SO_0_R
GND SO/SIO1
ACES_91960-0084N_MX25L3206EM2I
CONN@
4 4

SKL-U(3/12)SPI,ESPI,SMB,LPC
A B C D E

A B C D E
1 1
UC1G SKL - U
Rev_0.53
AUD IO
HDA for AUDIO HDA_SYNC

HDA_BIT_CLK
BA22
HDA_SYNC/I2S0_SFRM
AY22
HDA_SDOUT BB22 HDA_BLK/I2S0_SCLK
SDIO/SDX C
HDA_SDIN0 HDA_SDIN0 BA21 HDA_SDO/I2S0_TXD
<25> HDA_SDIN0
AY21 HDA_SDI0/I2S0_RXD AB11
#543016 PDG2.0 P.403
RPC9 HDA_RST# AW22 HDA_SDI1/I2S1_RXD GPP_G0/SD_CMD AB13 SDIO signals are mult i pl exed wit h GPI Os and def aul t
1 8 HDA_SYNC J5 HDA_RST#/I2S1_SCLK GPP_G1/SD_DATA0 AB12 to GPIO funct i onali t y ( as i nput). If S DI Oi nt erf ac e i s
<25> HDA_SYNC_R HDA_SDOUT GPP_D23/I2S_MCLK GPP_G2/SD_DATA1
2 7 AY20 W12 not used, the signals can be used as GPIOs instead.
<25> HDA_SDOUT_R HDA_BIT_CLK I2S1_SFRM GPP_G3/SD_DATA2
3 6 AW20 W11
<25> HDA_BIT_CLK_R
4 5 HDA_RST# I2S1_TXD GPP_G4/SD_DATA3 W10 If the GPIO funct i onali t y i s al s o not us ed, t he si gnal s
<25> HDA_RST#_R GPP_G5/SD_CD# can be lef t as no- c onnect.
AK7 W8
AK6 GPP_F1/I2S2_SFRM GPP_G6/SD_CLK W7
33_0804_8P4R_5%
AK9 GPP_F0/I2S2_SCLK GPP_G7/SD_WP
1 2 AK10 GPP_F2/I2S2_TXD BA9
<29> ME_EN @
RC77 0_0402_5% GPP_F3/I2S2_RXD GPP_A17/SD_PWR_EN#/ISH_GP7 BB9 RC76
GPP_A16/SD_1P8_SEL 200_0402_1%
H5 AB7 SD_RCOMP 2 1
HDA_SDO / I2S_TXD0 (Internal Pull Down): D7 GPP_D19/DMIC_CLK0 SD_RCOMP
(Sampled: Rising edge of PCH_PWROK ) GPP_D20/DMIC_DATA0
Flash Descriptor Security Override D8 AF13
#543016 PDG2.0 P.879
C8 GPP_D17/DMIC_CLK1 GPP_F23
0 = Enable security measures def i ned i n t he Fl as h GPP_D18/DMIC_DATA1
2 Descriptor. PCH_SPKR AW5 2
<25> PCH_SPKR GPP_B14/SPKR
1 = Disable Flash Descriptor Security (override). This
strap should only be asserted high using external 7 OF 20
SKL-U_BGA1356
pull-up in manufacturing/debug environments ONLY. @
SPKR / GPP_B14 (Internal Pull Down):

SKL _ U LT
(Sampled:Rising edge of PCH_PWROK) UC1I
Rev_0.53
CSI-2
TOP Swap Override A36 C37 +3VALW_1.8VALW_PGPPD

* 0 = Disable TOP Swap mode. B36
C38
CSI2_DN0
CSI2_DP0
CSI2_CLKN0
CSI2_CLKP0
D37
C32
1 = Enable TOP Swap Mode. CSI2_DN1 CSI2_CLKN1
1
D38 D32
C36 CSI2_DP1 CSI2_CLKP1 C29 RC133
D36 CSI2_DN2 CSI2_CLKN2 D29
CSI2_DP2 CSI2_CLKP2 10K_0402_5%
A38 B26
B38 CSI2_DN3 CSI2_CLKN3 A26
Intel HD Audio link capabilit i es #543016 PDG2.0 P.551
2
CSI2_DP3 CSI2_CLKP3
> Two SDI signals to support two external codecs. C31 E13 CSI2_COMP RC80 2 1 100_0402_1% DGPU_PRSNT#
> Drivers variable requency (5MHz to 24MHz) BCLK to support: D31 CSI2_DN4 CSI2_COMP B7 DGPU_PRSNT#
C33 CSI2_DP4 GPP_D4/FLASHTRIG
-- SDO double pumped up to 48 Mb/s CSI2_DN5
D33
-- SDI's single pumped up to 24 Mb/s A31 CSI2_DP5 EMM C
> Provides cadence for 44.1 kHz based sample rate output. B31 CSI2_DN6 AP2
> Support 1.5V, 1.8V, and 3.3V modes. A33 CSI2_DP6 GPP_F13/EMMC_DATA0 AP1
B33 CSI2_DN7 GPP_F14/EMMC_DATA1 AP3
3 CSI2_DP7 GPP_F15/EMMC_DATA2 AN3 3
A29 GPP_F16/EMMC_DATA3 AN1
B29 CSI2_DN8 GPP_F17/EMMC_DATA4 AN2
C28 CSI2_DP8 GPP_F18/EMMC_DATA5 AM4
D28 CSI2_DN9 GPP_F19/EMMC_DATA6 AM1
A27 CSI2_DP9 GPP_F20/EMMC_DATA7
B27 CSI2_DN10 AM2
C27 CSI2_DP10 GPP_F21/EMMC_RCLK AM3
D27 CSI2_DN11 GPP_F22/EMMC_CLK AP4
CSI2_DP11 GPP_F12/EMMC_CMD
9 OF 20 AT1 EMMC_RCOMP 2 1
EMMC_RCOMP
RC89 200_0402_1%
SKL-U_BGA1356
@ #543016 PDG2.0 P.393
4 4

SKL-U(4/12)HDA,EMMC,SDIO,CSI2
A B C D E

A B C D E
SOC_XTAL24_IN
+RTCVCC
RC91 1 2 20K_0402_5% SOC_SRTCRST# SOC_XTAL24_OUT 1 2

RC92 1M_0402_5%
CC10 1 2 1U_0402_6.3V6K
1 YC1 1
UC1J SKL _ U LT 24MHZ_12PF_7V24000020
RC93 1 2 20K_0402_5% SOC_RTCRST# Rev_0.53
CLOCK SIGNALS 3 1
CC11 1 2 1U_0402_6.3V6K 3 1
1
GND GND
15P_0402_50V8J
CC12
15P_0402_50V8J
CC13
D42
CLKOUT_PCIE_N0
JCMOS1 1 @ 2 0_0603_5% CLR CMOS C42
CLKREQ_PCIE#0 AR10 CLKOUT_PCIE_P0 4 2
2
GPP_B5/SRCCLKREQ0#
Place at RAM DOOR CLK_PCIE_N1 B42
<23> CLK_PCIE_N1 CLK_PCIE_P1 A42 CLKOUT_PCIE_N1 F43 CLK_CPU_ITP#
SM_INTRUDER#
GLAN <23> CLK_PCIE_P1 CLKREQ_PCIE#1 CLKOUT_PCIE_P1 CLKOUT_ITPXDP_N CLK_CPU_ITP T164 @
RC941 2 1M_0402_5%
<23> CLKREQ_PCIE#1
AT7 E43 T165 @
GPP_B6/SRCCLKREQ1# CLKOUT_ITPXDP_P
CLK_PCIE_N2 D41 BA17 SUSCLK
<24> CLK_PCIE_N2 CLK_PCIE_P2 CLKOUT_PCIE_N2 GPD8/SUSCLK T185 @
NGFF C41
+3VS <24> CLK_PCIE_P2 CLKREQ_PCIE#2 CLKOUT_PCIE_P2 SOC_XTAL24_IN
AT8 E37
<24> CLKREQ_PCIE#2 GPP_B7/SRCCLKREQ2# XTAL24_IN SOC_XTAL24_OUT
E35
RC121 1 2 10K_0402_5% CLKREQ_PCIE#1 D40 XTAL24_OUT
C40 CLKOUT_PCIE_N3 E42 XCLK_BIASREF Follow 2014MOW48
RC123 1 2 10K_0402_5% CLKREQ_PCIE#2 CLKREQ_PCIE#3 AT10 CLKOUT_PCIE_P3 XCLK_BIASREF Skylake U PU 2.7k ohm to 1V
GPP_B8/SRCCLKREQ3# AM18 SOC_RTCX1 Cannonlake U PD 60.4 ohm
B40 RTCX1 AM20 SOC_RTCX2 +1.0VALW_CLK5_F24NS
RPC12 A40 CLKOUT_PCIE_N4 RTCX2
8 1 CLKREQ_PCIE#5 CLKREQ_PCIE#4 AU8 CLKOUT_PCIE_P4 AN18 SOC_SRTCRST# XCLK_BIASREF 1 2 2.7K_0402_1%
RC96
7 2 CLKREQ_PCIE#4 GPP_B9/SRCCLKREQ4# SRTCRST# AM16 SOC_RTCRST#
6 3 CLKREQ_PCIE#3 E40 RTCRST#
5 4 CLKREQ_PCIE#0 E38 CLKOUT_PCIE_N5 RC136 1 @ 2 60.4_0402_1%
CLKREQ_PCIE#5 AU7 CLKOUT_PCIE_P5
GPP_B10/SRCCLKREQ5#
10K_0804_8P4R_5%
XCLK_BIASREF
10 OF 20
+1.0V_VCCST T:50ohm S:12/15 L:1000 Via:2
2 SKL-U_BGA1356 2
@
From EC(open-drain)
1
RC113
1K_0402_5%
RC116
2014M OW4 8:
60.4_0402_1% UC1K SKL - U Skylake-U use 24M 50 ohm ESR
2
1 2 EC_VCCST_PG Rev_0.53 Cannonlake U use 38.4M 30 ohm ESR

<29,32> EC_VCCST_PG_R SYSTEM POWER MANAGEMENT
AT11 PM_SLP_S0#
GPP_B12/SLP_S0# AP15 PM_SLP_S3# PM_SLP_S0# <29> SOC_RTCX2
Note for VCCST_PWRGD PLT_RST# AN10 GPD4/SLP_S3# BA16 PM_SLP_S4# PM_SLP_S3# <29,32>
1. 1.0V tolerance <29> PLT_RST# SYS_RESET# B5 GPP_B13/PLTRST# GPD5/SLP_S4# AY16 PM_SLP_S5# PM_SLP_S4# <29,32>
EC_RSMRST# SYS_RESET# GPD10/SLP_S5# @ T84 SOC_RTCX1
2. PDG2.0 P.598 Figure43-5 note17: when failure events, <29> EC_RSMRST#
AY17
RSMRST#
1 2
AN15 SLP_SUS# RC98 10M_0402_5%
VCCST_PWRGD and PCH_PWROK de-assert at the same t i me H_CPUPWRGD SLP_SUS# SLP_LAN# @ T90
A68 AW15
T95 @ EC_VCCST_PG PROCPWRGD SLP_LAN# SLP_WLAN# @ T87
B65 BB17
VCCST_PWRGD GPD9/SLP_WLAN# PM_SLP_A# @ T88
AN16
T89 @ SYS_PWROK GPD6/SLP_A# @ T94
B6 YC2
+3VALW_PRIM <29,32> SYS_PWROK PCH_PWROK SYS_PWROK PBTN_OUT#_R
BA20 BA15 1 2
<29,32> PCH_PWROK PCH_DPWROK PCH_PWROK GPD3/PWRBTN# AC_PRESENT
BB20 AY15
+3VALW_DSW RPC11 DSW_PWROK GPD1/ACPRESENT PM_BATLOW# AC_PRESENT <29>
AU13 32.768KHZ_9PF_X1A000141000200
8 1 PCH_PWROK SUSPWRDNACK AR13 GPD0/BATLOW# Change PN to SJ10000Q400
7 2 EC_RSMRST# <29> SUSPWRDNACK AP11 GPP_A13/SUSWARN#/SUSPWRDNACK
SUSACK# 1 1
6 3 SYS_RESET# T92 @ GPP_A15/SUSACK# AU11 CC15 CC16
LAN_WAKE# GPP_A11/PME# SM_INTRUDER# @ T91
5 4 WAKE# BB15 AP16 6.8P_0402_50V8C 8.2P_0402_50V8D
LAN_WAKE# AM15 WAKE# INTRUDER#
AW17 GPD2/LAN_WAKE# AM10 EXT_PWR_GATE# 2 2
10K_0804_8P4R_5% @ T93
AT15 GPD11/LANPHYPC GPP_B11/EXT_PWR_GATE# AM11 SOC_VRALERT#
GPD7/RSVD GPP_B2/VRALERT#
11 OF 20
RC110 2 1 10K_0402_5% SYS_PWROK
SKL-U_BGA1356
3 @ 3
2 @ 1 PBTN_OUT#_R +3VALW_DSW
<29> PBTN_OUT#
RC109 0_0402_5% PCH internal PU
PBTN_OUT#_R RC111 1 @ 2 100K_0402_5%
EC_RSMRST# 2 @ 1 PCH_DPWROK
+3VALW_DSW RC114 0_0402_5%
AC_PRESENT RC106
EC1 internal
@
PU
2 10K_0402_5%
RC104 1 2 1K_0402_5% WAKE# SYS_PWROK 2 @ 1 PCH_PWROK
RC122 0_0402_5%
PM_BATLOW# RC103 1 2 10K_0402_5%
WAKE# (DSX wake event)
10 KΩ pull- up t o Vcc DS W3_3.
The pull-up is required even if PCIe* interface
+3VALW_PRIM
is not used on the plat f or m
.
PCH PLTRST Buf f er
+3VS SOC_VRALERT# Default : GPI
RC115 2 1@ 10K_0402_5%
@ESD@
CC51 2 1 .1U_0402_16V7K SYS_RESET#
5
@ESD@ PLT_RST# 2
P
CC50 2 1 .1U_0402_16V7KH_CPUPWRGD B 4 PLT_RST_BUF#

1 Y PLT_RST_BUF# <23,24>
G
A
1
@ESD@ @
CC66 2 1 .1U_0402_16V7K SYS_PWROK UC3 RC118
3
MC74VHC1G08DFT2G_SC70-5 100K_0402_5%
@ESD@
CC65 2 1 .1U_0402_16V7K PCH_PWROK
2
2 1
@ESD@ @ RC125 0_0402_5%
CC69 2 1 .1U_0402_16V7K EC_RSMRST#
4 4
#543016 PDG2.0 P.599

PROCPWRGD is used only for power sequence
debug and is not required to be connected to
anything on the plat f or m.
SKL-U(5/12)CLK,GPIO
A B C D E

A B C D E
1 +3VALW_1.8VALW_PGPPD 1
1
RC215
10K_0402_5%
KBL@
2
CPU_ID
CPU_ID
1
RC214
UC1F SKL - U SkyLake 0 10K_0402_5%
Rev_0.53
L P SS IS H KabyLake 1 SKL@
2
TS_EN AN8
<21,29> TS_EN AP7 GPP_B15/GSPI0_CS# P2
AP8 GPP_B16/GSPI0_CLK GPP_D9 P3 CPU_ID
GSPI0_MOSI AR7 GPP_B17/GSPI0_MISO GPP_D10 P4 PROJECT_ID0 +3VALW_1.8VALW_PGPPD
@ T111 GPP_B18/GSPI0_MOSI GPP_D11 PROJECT_ID1
P1
AM5 GPP_D12
AN7 GPP_B19/GSPI1_CS# M4 ISH_I2C0_SDA PROJECT_ID0 2 1 10K_0402_5%
RC207 @
+3VS AP5 GPP_B20/GSPI1_CLK GPP_D5/ISH_I2C0_SDA N3 ISH_I2C0_SCL RC210 1 2 10K_0402_5%
GSPI1_MOSI AN5 GPP_B21/GSPI1_MISO GPP_D6/ISH_I2C0_SCL ISH sensor HUB
@ T112 GPP_B22/GSPI1_MOSI (Reserve for Verify)
1 2 UART_2_CRXD_DTXD N1 ISH_I2C1_SDA
RC62 49.9K_0402_1% AB1 GPP_D7/ISH_I2C1_SDA N2 ISH_I2C1_SCL PROJECT_ID1 RC211 2 @ 1 10K_0402_5%
1 2 UART_2_CTXD_DRXD AB2 GPP_C8/UART0_RXD GPP_D8/ISH_I2C1_SCL 1 2 10K_0402_5%
RC213
W4 GPP_C9/UART0_TXD AD11 I2C_5_SDA
RC63 49.9K_0402_1% T105 @
1 2 UART_2_CRTS_DCTS AB3 GPP_C10/UART0_RTS# GPP_F10/I2C5_SDA/ISH_I2C2_SDA AD12 I2C_5_SCL
@ T106 @ no use
RC64 49.9K_0402_1% GPP_C11/UART0_CTS# GPP_F11/I2C5_SCL/ISH_I2C2_SCL
2 1 @ 2 UART_2_CCTS_DRTS UART_2_CRXD_DTXD AD1 2
<24> UART_2_CRXD_DTXD UART_2_CTXD_DRXD AD2 GPP_C20/UART2_RXD U1
RC65 49.9K_0402_1%
<24> UART_2_CTXD_DRXD UART_2_CRTS_DCTS AD3 GPP_C21/UART2_TXD GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA U2
UART_2_CCTS_DRTS AD4 GPP_C22/UART2_RTS# GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL U3
GPP_C23/UART2_CTS# GPP_D15/ISH_UART0_RTS# U4 Project_ID1 Project_ID0
<Reserved for Touch PNL>
GPP_D16/ISH_UART0_CTS#/SML0BALERT# Project ID
I2C_0_SDA U7 AC1 GPP_D12 GPP_D11
<21> I2C_0_SDA I2C_0_SCL GPP_C16/I2C0_SDA GPP_C12/UART1_RXD/ISH_UART1_RXD
U6 AC2
+3VALW_PGPPC <21> I2C_0_SCL GPP_C17/I2C0_SCL GPP_C13/UART1_TXD/ISH_UART1_TXD AC3
* B5W1S 0 0
I2C_1_SDA U8 GPP_C14/UART1_RTS#/ISH_UART1_RTS# AB4
<30> I2C_1_SDA I2C_1_SCL U9 GPP_C18/I2C1_SDA GPP_C15/UART1_CTS#/ISH_UART1_CTS# Reserved 0 1
+3VS <Touch PAD/PNL> <30> I2C_1_SCL GPP_C19/I2C1_SCL AY8
no use
I2C_2_SDA AH9 GPP_A18/ISH_GP0 BA8 Reserved 1 0
I2C_0_SDA T135 @ I2C_2_SCL GPP_F4/I2C2_SDA GPP_A19/ISH_GP1
RC126 1 2 1K_0402_5% AH10 BB7
RC127 1 2 1K_0402_5% I2C_0_SCL T134 @ GPP_F5/I2C2_SCL GPP_A20/ISH_GP2 BA7 Reserved 1 1
I2C_3_SDA AH11 GPP_A21/ISH_GP3 AY7
1 2 2.2K_0402_5% I2C_1_SDA no use T131 @ I2C_3_SCL AH12 GPP_F6/I2C3_SDA GPP_A22/ISH_GP4 AW7
RC128 T130 @
RC129 1 2 2.2K_0402_5% I2C_1_SCL GPP_F7/I2C3_SCL GPP_A23/ISH_GP5 AP13
I2C_4_SDA AF11 GPP_A12/BM_BUSY#/ISH_GP6
no use T128 @ I2C_4_SCL AF12 GPP_F8/I2C4_SDA +3VALW_1.8VALW_PGPPD
T129 @ GPP_F9/I2C4_SCL
6 OF 20 RPC19
ISH_I2C1_SCL 1 8
SKL-U_BGA1356 ISH_I2C1_SDA 2 7
@ ISH_I2C0_SCL 3 6
ISH_I2C0_SDA 4 5
@
1K_0804_8P4R_5%
3
Funct i onal Str ap Def ini t i o +3VS
3
GSPI0_MOSI /GPP_B18 (Internal Pull Down): +1.8VS_3VS_PGPPA +1.8VS
(Rising edge of PCH_PWROK) RC177
No Reboot 0_0402_5%2 ESPI@ 1
RC178
* 0 = Disable No Reboot mode. --> AAX05 Use 0_0402_5%2 @ 1
1 = Enable No Reboot Mode. (PCH will disable the TCO
Timer system reboot feature). This funct i on i s us ef ul
when running ITP/XDP.
GSPI1_MOSI / GPP_B22 (Internal Pull Down):
(Rising edge of PCH_PWROK)
Boot BIOS Strap Bit

* 0 = SPI Mode --> AAX05 Use
1 = LPC Mode
4 4

SKL-U(6/12)GPIO
A B C D E

A B C D E
UC1H SKL - U
Rev_0.53
SSIC / USB3
P CIE/ US B 3 / SATA
H8
USB3_1_RXN USB3_CRX_DTX_N1 <28>
G8
USB3_1_RXP USB3_CRX_DTX_P1 <28>
H13 C13
G13 PCIE1_RXN/USB3_5_RXN USB3_1_TXN D13
USB3_CTX_DRX_N1 <28> USB3 MB
1 PCIE1_RXP/USB3_5_RXP USB3_1_TXP USB3_CTX_DRX_P1 <28> 1
B17
A17 PCIE1_TXN/USB3_5_TXN J6
PCIE1_TXP/USB3_5_TXP USB3_2_RXN/SSIC_1_RXN H6
G11 USB3_2_RXP/SSIC_1_RXP B13
F11 PCIE2_RXN/USB3_6_RXN USB3_2_TXN/SSIC_1_TXN A13
D16 PCIE2_RXP/USB3_6_RXP USB3_2_TXP/SSIC_1_TXP
C16 PCIE2_TXN/USB3_6_TXN J10
PCIE2_TXP/USB3_6_TXP USB3_3_RXN/SSIC_2_RXN H10
H16 USB3_3_RXP/SSIC_2_RXP B15
G16 PCIE3_RXN USB3_3_TXN/SSIC_2_TXN A15
D17 PCIE3_RXP USB3_3_TXP/SSIC_2_TXP
C17 PCIE3_TXN E10
PCIE3_TXP USB3_4_RXN F10
G15 USB3_4_RXP C15
F15 PCIE4_RXN USB3_4_TXN D15
B19 PCIE4_RXP USB3_4_TXP
A19 PCIE4_TXN AB9 USB20_N1
PCIE4_TXP USB2N_1 AB10 USB20_P1 USB20_N1 <28>
PCIE_CRX_DTX_N5 F16 USB2P_1 USB20_P1 <28> USB3 MB
<23> PCIE_CRX_DTX_N5 PCIE_CRX_DTX_P5 E16 PCIE5_RXN AD6 USB20_N2
<23> PCIE_CRX_DTX_P5 PCIE_CTX_DRX_N5 PCIE5_RXP USB2N_2 USB20_P2 USB20_N2 <28>
GLAN CC25 2 1 .1U_0402_16V7K C19 AD7 USB2 MB
<23> PCIE_CTX_C_DRX_N5 PCIE_CTX_DRX_P5 PCIE5_TXN USB2P_2 USB20_P2 <28>
CC26 2 1 .1U_0402_16V7K D19
<23> PCIE_CTX_C_DRX_P5 PCIE5_TXP AH3 USB20_N3
PCIE_CRX_DTX_N6 USB2N_3 USB20_P3 USB20_N3 <28>
G18 AJ3 TO D/B USB2
<24> PCIE_CRX_DTX_N6 PCIE_CRX_DTX_P6 F18 PCIE6_RXN USB2P_3 USB20_P3 <28>
<24> PCIE_CRX_DTX_P6 CC60 1 2 .1U_0402_16V7K PCIE_CTX_DRX_N6 D20 PCIE6_RXP AD9
NGFF WLAN+BT(Key E) <24> PCIE_CTX_C_DRX_N6 PCIE_CTX_DRX_P6 PCIE6_TXN USB2N_4
CC62 1 2 .1U_0402_16V7K C20 AD10
<24> PCIE_CTX_C_DRX_P6 PCIE6_TXP USB2P_4
F20 AJ1 USB20_N5
<26> SATA_CRX_DTX_N0 PCIE7_RXN/SATA0_RXN USB2N_5 USB20_P5 USB20_N5 <24>
E20 AJ2 BT
<26> SATA_CRX_DTX_P0 B21 PCIE7_RXP/SATA0_RXP USB2P_5 USB20_P5 <24>
HDD <26> SATA_CTX_DRX_N0 PCIE7_TXN/SATA0_TXN
US B 2
USB20_N6
A21 AF6
2 <26> SATA_CTX_DRX_P0 PCIE7_TXP/SATA0_TXP USB2N_6 AF7 USB20_P6 USB20_N6 <21> 2
G21 USB2P_6 USB20_P6 <21> TS
<26> SATA_CRX_DTX_N1 F21 PCIE8_RXN/SATA1A_RXN AH1 USB20_N7
<26> SATA_CRX_DTX_P1 D21 PCIE8_RXP/SATA1A_RXP USB2N_7 AH2 USB20_P7 USB20_N7 <21>
ODD <26> SATA_CTX_DRX_N1 PCIE8_TXN/SATA1A_TXN USB2P_7 USB20_P7 <21> Ca m er a
C21
<26> SATA_CTX_DRX_P1 PCIE8_TXP/SATA1A_TXP AF8 USB20_N8
USB2N_8 USB20_P8 USB20_N8 <28>
E22 AF9 TO D/B CR
PCIE9_RXN USB2P_8 USB20_P8 <28>
E23
B23 PCIE9_RXP AG1
A23 PCIE9_TXN USB2N_9 AG2
PCIE9_TXP USB2P_9
F25 AH7
#543016 PDG2.0 P.285 E25 PCIE10_RXN USB2N_10 AH8
PCIE_RCOMPN/PCIE_RCOM PP D23 PCIE10_RXP USB2P_10 2015MOW10, USB2_ID Connected to GND Directly
BO=4 W=12 S=12 R=100ohm C23 PCIE10_TXN AB6 USB2_COMP RC119 1 2 113_0402_1%
PCIE10_TXP USB2_COMP AG3 USB2_ID RC130 1 2 0_0402_5%
RC1201 2 100_0402_1% PCIE_RCOMPN F5 USB2_ID AG4 USB2_VBUSSENSE RC131 1 2 0_0402_5%
PCIE_RCOMPP E5 PCIE_RCOMPN USB2_VBUSSENSE
PCIE_RCOMPP A9 USB_OC0#
+3VALW_PRIM XDP_PRDY# GPP_E9/USB2_OC0# USB_OC0# <28>
@ T196 D56 C9
XDP_PREQ# D61 PROC_PRDY# GPP_E10/USB2_OC1# D9
2
@ T197
1 10K_0402_5% PIRQA# BB11 PROC_PREQ# GPP_E11/USB2_OC2# B9
Unused OC pin need set to GPI.
RC135 @
GPP_A7/PIRQA# GPP_E12/USB2_OC3# +3VALW_PRIM
E28 J1
E27 PCIE11_RXN/SATA1B_RXN GPP_E4/DEVSLP0 J2
D24 PCIE11_RXP/SATA1B_RXP GPP_E5/DEVSLP1 J3 USB_OC0# RC132 1 2 10K_0402_5%
When PCIE8/SATA1A is used C24 PCIE11_TXN/SATA1B_TXN GPP_E6/DEVSLP2
as SATA Port 1 (ODD), then E30 PCIE11_TXP/SATA1B_TXP H2
PCIE11/SATA1B (M.2 SSD) F30 PCIE12_RXN/SATA2_RXN GPP_E0/SATAXPCIE0/SATAGP0 H3
A25 PCIE12_RXP/SATA2_RXP GPP_E1/SATAXPCIE1/SATAGP1 G4
cannot be used as SATA Port PCIE12_TXN/SATA2_TXN GPP_E2/SATAXPCIE2/SATAGP2
B25
1. PCIE12_TXP/SATA2_TXP H1
3 GPP_E8/SATALED# 3
8 OF 20
SKL-U_BGA1356
@
GPIO DEVICE CONTROL
US B_ O C 0 # USB2 Port 1 DEVSLP[2:0] Implementat i on

DEVSLP is a host-controlled hardware signal which enables a SATA host and device to
US B_ O C 1 # NA
enter an ultra-low interface power state, including the possibility to completely power
down host and device PHYs.
US B_ O C 2 # NA The processor provides three SATA DEVSLP signals, DEVSLP[2:0] for SKL U.
‧When hi gh, DE VSL P r equests t he SAT A devi c e t o ent er i nt o t he DE VSL P po wer st at e.
US B_ O C 3 # NA
‧When l o w, DE VSL P r equests t he SAT A devi c e t o exi t fr o mt he DE VSL P po wer st at e
D EV S L P 0 NA and transit i on t o ac t i ve s tate.
D EV S L P 1 NA
D EV S L P 2 NA SATA General Purpose (SATAGP[2:0]) Signals

‧The pr oc ess or pr ovi des t hr ee SAT A gener al pur pos e i nput si gnal s, SAT AGP[ 2: 0] f or S KL U.
SA TA _ G P 0 NA These signals can be conf i gur ed as i nt erl oc k s wit c h i nputs c orr es pondi ng t o a gi ven SAT A port.
NA
‧When us ed as an i nt erl oc k s wit c h st at us i ndi c a t i on, thi s s i gnal s houl d be dr i ven to 0
SA TA _ G P 1 to indicate that the switch is closed and to a 1 to indicate that the switch is open.
4
SA TA _ G P 2
‧If mec hani c al pr es enc e s wit c hes will not be us ed on t he pl a t fo rm, SAT AGP[2:0] 4
NA
signals can be conf i gur ed as GPP_E[ 2: 0] GPI Os si gnal s.

SKL-U(7/12)PCIE,USB,SATA
A B C D E

A B C D E
+1.0VALW_PRIM TO +1.0V_VCCSTU / +1.0VCCST

+5VALW +1.0VALW_PRIM +1.0V_VCCSTU +1.2V_VDDQ +1.2V_VDDQ_CPU +VCCIO
UC1N SKL - U
Rev_0.53
CPU POWER 3 OF 4
JPC1
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 2 AU23 AK28
VDDQ_AU23 VCCIO
CC98
CC97
1 @ AU28 AK30
JUMP_43X118 AU35 VDDQ_AU28 VCCIO AL30
2.73A
@ CC96 AU42 VDDQ_AU35 VCCIO AL42
2 2 JPC2 BB23 VDDQ_AU42 VCCIO AM28
.1U_0402_16V7K VDDQ_BB23
6.35A VCCIO
2 1 2 BB32 AM30
@ BB41 VDDQ_BB32 VCCIO AM42
1 UC5 JUMP_43X118 BB47 VDDQ_BB41 VCCIO 1
2 1 .1U_0402_16V7K 1 14 BB51 VDDQ_BB47 AK23
CC105 +VCC_SA
2 VIN1 VOUT1 13 VDDQ_BB51 VCCSA AK25
VIN1 VOUT1 VCCSA G23
RC142 1 2 20K_0402_5% EN_1.0V_VCCSTU 3 12 1 2 AM40 VCCSA G25
+1.2V_VDDQC 0.09A
<29,32,37> SYSON ON1 CT1 CC95 VDDQC VCCSA G27
4 11 1000P_0402_50V7K A18 VCCSA G28
VBIAS GND +1.0V_VCCST VCCST
0.04A VCCSA
6A J22
RC168 1 @ 2 0_0402_5% EN_1.8VS 5 10 1 2 A22 VCCSA J23
+1.0VS_VCCSTG 0.04A
<29,32,35,37> SUSP# ON2 CT2 VCCSTG_A22 VCCSA J27
CC94
2 1 CC104 6 9 1000P_0402_50V7K AL23 VCCSA K23
+1.2V_VCCSFR_OC 0.26A
@ 1U_0402_6.3V6K +1.8VALW_VS 7 VIN2 VOUT2 8 VCCPLL_OC VCCSA K25
VIN2 VOUT2 +1.8VS K20 VCCSA K27
+1.0V_VCCSFR 0.12A
15 K21 VCCPLL_K20 VCCSA K28
1 2 GPAD VCCPLL_K21 VCCSA K30
+1.8VALW_PRIM 1 2 VCCSA
EM5209VF_DFN14_2X3
VCCIO_SENSE
1U_0402_6.3V6K
JPC8 1 1 AM23 T124 @
VCCIO_SENSE VSSIO_SENSE
CC99
JUMP_43X39 AM22 T125 @
@ CC100 VSSIO_SENSE
@ H21 VSSSA_SENSE
.1U_0402_16V7K
2
+1.8VALW_PRIM TO +1.8VS 2 VSSSA_SENSE
14 OF 20VCCSA_SENSE
H20 VCCSA_SENSE VSSSA_SENSE <40>
VCCSA_SENSE <40>
SKL-U_BGA1356
@
+1.0VALW_PRIM TO +1.0VS_VCCSTG
+1.0VALW_PRIM
+1.0VALW_PRIM_JP
2
VCCSTG,VCCIO SLEW RATE <=10ms 2
JPC4
1 2 +1.2V_VDDQ_CPU +1.2V_VDDQC
1 2 +1.0VS_VCCSTG PSC Side
#543016 PDG2.0 P.750
1U_0402_6.3V6K
Imax : 3.44 AJUMP_43X79 1

+1.35V_VDDQC : 1x 10uF
CC117
@ RC188 1 @ 2 0_0402_5% RC208 1 @ 2 0_0402_5% CC47 1 2 10U_0603_6.3V6M

For Power consumption UC6
Measurement 1
2 2 VIN1 +VCCIO
+5VALW VIN2 @ JPC5 +1.0V_VCCSTU +1.0V_VCCST
CC107 7 6 +1.0VS_VCCSTG_IO 1 2 PSC Side
.1U_0402_16V7K VIN thermal VOUT 1 2 #543016 PDG2.0 P.750
2
@
1 3
VBIAS 1 JUMP_43X79 Imax : 3.4 A RC140 1 @ 2 0_0402_5% CC48 1 2 1U_0402_6.3V6K +1.0V_VCCST : 1x 1uF
SUSP# 1 @ 2 SUSP#_R1 4 5 CC127
RC186 ON GND +1.0V_VCCSFR
.1U_0402_16V7K PSC Side
2
1U_0402_6.3V6K
0_0402_5% 1 #543016 PDG2.0 P.750

CC106
TPS22961DNYR_WSON8
RC143 1 @ 2 0_0402_5% CC55 1 2 1U_0402_6.3V6K +1.0V_VCCSFR : 1x 1uF Reference GND as possible.
@
2
+1.2V_VDDQ_CPU +1.2V_VCCSFR_OC BSC Side

#543016 PDG2.0 P.750
+1.0VALW_PRIM_JP UC8
RC141 1 @ 2 0_0402_5% CC49 1 2 1U_0402_6.3V6K +1.35V_VCCSFR_OC : 1x 1uF
@
1 7 +1.0VS_VCCSTG_IO BSC Side

2 VIN VOUT 8
VIN VOUT @ +1.0VS_VCCSTG CC56 1 2 1U_0402_6.3V6K #543016 PDG2.0 P.750
SUSP#_R1 3
ON CT
6 CC126 1 2 1000P_0402_50V7K @ +1.0V_VCCSTG : 1x 1uF (Placeholder)
3 +5VALW 3
4
VBIAS 5
GND 9
GND
AOZ1336_DFN8_2X2
+VCCIO +1.2V_VDDQ_CPU
BSC Side PSC Side PSC Side BSC Side
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CC58
CC59
CC37
CC41
CC54
CC27
CC28
CC33
CC34
CC35
CC36
CC38
CC39
CC40
CC42
CC43
CC44
CC45
CC46
@ @ @ @ @ @ @ @
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
4 #543016 PDG2.0 P.750 #543016 PDG2.0 P.750 4
+VCCIO : 4x 1uF 0402 +1.35V_VDDQ_CPU :

4x 10uF 0402
3x 22uF 0603

SKL-U(8/12)Power
A B C D E

A B C D E
+3VALW_PRIM
+1.0VALW_PRIM UC1O SKL - U +3VALW_1.8VALW_PGPPA +1.8VALW_PRIM

CC91 Rev_0.53
CPU POWER 4 OF 4
2 1 1U_0402_6.3V6K
+1.0VALW_MPHYAON @ AB19 0_0402_5% 2 ESPI@ 1 RC196
+1.0VALW_PRIM AB20 VCCPRIM_1P0 AK15 0_0402_5% 2 @ 1 RC197
Near AB19 (<10 mm) 0.89A +3VALW_1.8VALW_PGPPA SPI Touch
P18 VCCPRIM_1P0 VCCPGPPA AG15
VCCPRIM_1P0 VCCPGPPB +3VALW_PGPPB
RC175 1 @ 2 0_0402_5% 1 2 CC87 Y16
+1.0VALW_PRIM VCCPGPPC +3VALW_PGPPC
1U_0402_6.3V6K AF18 Y15
VCCPRIM_CORE VCCPGPPD +3VALW_1.8VALW_PGPPD +3VALW_PRIM
2 1 CC76 AF19 2.57A T16 +3VALW_PGPPB
CC87 near K17 (<3 mm) @ 1U_0402_6.3V6K V20 VCCPRIM_CORE VCCPGPPE AF16
+3VALW_PGPPE
VCCPRIM_CORE VCCPGPPF +1.8VALW_PRIM
V21 AD15
1 +1.0VALW_PRIM +1.0VALW_APLL near AF18 (<10 mm) VCCPRIM_CORE VCCPGPPG +3VALW_PGPPG No use 2 1 1
CC102 0_0402_5% 2 @ 1 RC161
CC85 2 1 DCPDSW_1P0 AL1 V19 1U_0402_6.3V6K @
DCPDSW_1P0 VCCPRIM_3P3_V19 +3VALW_PRIM
1U_0402_6.3V6K CC102 near AG15 (<3 mm)
RC148 1 @ 2 0_0603_5% 1 2 CC123 K17 T1
+1.0VALW_MPHYAON VCCMPHYAON_1P0 VCCPRIM_1P0_T1 +1.0VALW_DTS +3VALW_PRIM
@ 22U_0603_6.3V6M L1 +3VALW_PGPPC
VCCMPHYAON_1P0 AA1
VCCATS_1P8 +1.8VALW_PRIM
N15
+1.0VALW_MPHYGT VCCMPHYGT_1P0_N15
N16 AK17 CC73 2 1 0_0402_5% 2 @ 1 RC163
+3VALW VCCMPHYGT_1P0_N16 HSIO VCCRTCPRIM_3P3 +3VALW_RTC
+3VALW_DSW N17 1U_0402_6.3V6K @
P15 VCCMPHYGT_1P0_N17 AK19
2.1A +RTCVCC CC73 near Y16 (<10 mm)
P16 VCCMPHYGT_1P0_P15 VCCRTC_AK19 BB14
RC173 1 @ 2 0_0402_5% VCCMPHYGT_1P0_P16 VCCRTC_BB14 +3VALW_1.8VALW_PGPPD +3VALW_PRIM
K15 BB10 CC71 1 2 .1U_0402_16V7K +1.8VALW_PRIM
+1.0VALW_AMPHYPLL VCCAMPHYPLL_1P0 HSIO DCPRTC
L15
VCCAMPHYPLL_1P0 A14
+1.0VALW_CLK6_24TBT 0_0402_5% 1 @ 2 RC206
+3VALW_PRIM +3VALW_HDA V15 VCCCLK1 2 1
+1.0VALW_APLL CC103 0_0402_5% 2 @ 1 RC172
VCCAPLL_1P0 K19 1U_0402_6.3V6K
VCCCLK2 +1.0VALW_VCCCLK2
RC198 1 @ 2 0_0402_5% 1 2 CC63 AB17
+1.0VALW_PRIM VCCPRIM_1P0_AB17 +3VALW_PRIM
@ 1U_0402_6.3V6K Y18 L21 +3VALW_PGPPE
VCCPRIM_1P0_Y18 VCCCLK3 +1.0VALW_APLL
CC63 near AJ19 (<10 mm) AD17 N20
+3VALW_DSW VCCDSW_3P3_AD17 VCCCLK4 +1.0VALW_CLK4_F100OC
+3VALW_SPI AD18 CC74 2 1 0_0402_5% 2 @ 1 RC167
AJ17 VCCDSW_3P3_AD18 L19 1U_0402_6.3V6K
+1.0VALW_CLK5_F24NS @
1 2 0_0402_5% VCCDSW_3P3_AJ17 VCCCLK5
RC154 @ CC74 near T16 (<10 mm)
AJ19 A10
+3VALW_HDA VCCHDA VCCCLK6 +1.0VALW_CLK6_24TBT
+3VALW_PRIM
AJ16 AN11 PRIMCORE_VID0 +3VALW_PGPPG
+3VALW_SPI VCCSPI GPP_B0/CORE_VID0 PRIMCORE_VID1 T136 @
AN13 T138 @
AF20 GPP_B1/CORE_VID1 2 1
+1.0VALW_SRAM CC83 0_0402_5% 2 @ 1 RC187
+3VALW +3VALW_PRIM AF21 VCCSRAM_1P0 HSIO 1U_0402_6.3V6K @
T19 VCCSRAM_1P0
JPC7
1 2 T20 VCCSRAM_1P0
2 1 2 VCCSRAM_1P0 CC67 2 1 2
+3VALW_PRIM
JUMP_43X39 AJ21 1U_0402_6.3V6K @
+3VALW_PRIM VCCPRIM_3P3_AJ21
@ CC67 near V19 (<3 mm)
AK20
+1.0VALW_PRIM VCCPRIM_1P0_AK20
N18 +1.0VALW_DTS +1.0VALW_PRIM
+1.0VALW_APLLEBB VCCAPLLEBB HSIO 15 OF 20
0_0402_5% 2 @ 1 RC162
SKL-U_BGA1356
@
#543016 PDG2.0 P.764 CC72 2 1
+1.8VALW_PRIM
1U_0402_6.3V6K
HSIO +1.0VALW_MPHYPLL CC72 near AA1 (<10 mm)
+1.0VALW_PRIM +1.0VALW_MPHYGT
Imax : 3.5 A +3VALW_RTC +3VALW_PRIM
JPC9
1 2 RC209 1 @ 2 0_0603_5% CC82 1 2 22U_0603_6.3V6M CC78 2 1 0_0402_5% 2 @ 1 RC171
1 2 @ .1U_0402_16V7K
JUMP_43X79 CC77 2 1
@ CC80 1 2 1U_0402_6.3V6K #543016 PDG2.0 P.758 1U_0402_6.3V6K
+1.0VALW_PRIM +3VALW_PRIM +1.8VALW_PRIM CC77,CC78 near AK17 (<3 mm)
CC80 near N15 (<3mm)
CC82 near N15 (<10mm) +1.0VALW_CLK6_24TBT +1.0VALW_PRIM
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
+1.0VALW_AMPHYPLL 1 1 1 1 1 1 CC86 2 1 0_0402_5% 2 @ 1 RC169
CC111
CC112
CC113
CC114
CC116
CC115
1U_0402_6.3V6K @
CC61 near K15 (<3 mm) CC86 near A10 (<3 mm)
@ @ @ @ @ @
RC149 1 @ 2 0_0603_5% CC61 1 2 1U_0402_6.3V6K 2 2 2 2 2 2
@ +1.0VALW_VCCCLK2 +1.0VALW_PRIM
+1.0VALW_SRAM
3 CC75 2 1 0_0603_5% 2 @ 1 RC164 3
CC122 near AF20 (<10mm)
1U_0402_6.3V6K @
RC176 1 @ 2 0_0603_5% CC1221 2 1U_0402_6.3V6K CC124 2 1
@ 22U_0603_6.3V6M @
+1.0VALW_APLLEBB
+1.0VALW_CLK4_F100OC +1.0VALW_PRIM
CC68 near N18 (<3mm)
RC156 1 @ 2 0_0402_5% CC68 1 2 1U_0402_6.3V6K CC125 2 1 0_0603_5% 2 @ 1 RC190
22U_0603_6.3V6M @
+1.0VALW_CLK5_F24NS +1.0VALW_PRIM
0_0603_5% 2 @ 1 RC152
#543016 PDG2.0 P.470

VCCRTC does not exceed 3.2 V. RTC Battery
+RTCBATT +CHGRTC
Power Rail Voltage DC1
W=20mils
2 +RTCVCC
+CHGRTC 3.383V(M A X) W=1 0 m il
1
3
BAT54C(VF) 240 mV W=20mils
1
BAS40-04_SOT23-3
+RTCVCC 3.143V CC84
cap place close AK19. .1U_0402_16V7K
2
4 4
Result : Pass

SKL-U(9/12)Power
A B C D E

A B C D E
#544924 SKL EDS1.2 P.136

VCCGT U(15W)-dual core GT2 31A(MAX)
0.55-1.5V
+VCC_GT +VCC_GT
UC1M SKL - U
Rev_0.53
CPU POWER 2 OF 4
N70
A48 VCCGT N71
A53 VCCGT VCCGT R63
1 A58 VCCGT VCCGT R64 1
#544924 SKL EDS1.2 P.134 A62 VCCGT VCCGT R65
VCC U(15W)-dual core GT2 29A(MAX) A66 VCCGT VCCGT R66
0.55-1.52V AA63 VCCGT VCCGT R67
+VCC_CORE +VCC_CORE AA64 VCCGT VCCGT R68
AA66 VCCGT VCCGT R69
AA67 VCCGT VCCGT R70
UC1L SKL - U
Rev_0.53 AA69 VCCGT VCCGT R71
CPU POWER 1 OF 4 VCCGT VCCGT
AA70 T62
+1.0V_VCCST A30 G32 AA71 VCCGT VCCGT U65
#543016 PDG2.0 P.273 A34 VCC_A30 VCC_G32 G33 AC64 VCCGT VCCGT U68
A39 VCC_A34 VCC_G33 G35 AC65 VCCGT VCCGT U71
A44 VCC_A39 VCC_G35 G37 AC66 VCCGT VCCGT W63
VCC_A44 VCC_G37 VCCGT VCCGT
1
RC179 RC181 AK33 G38 AC67 W64

AK35 VCC_AK33 VCC_G38 G40 AC68 VCCGT VCCGT W65
56_0402_5% 100_0402_1%
AK37 VCC_AK35 VCC_G40 G42 AC69 VCCGT VCCGT W66
AK38 VCC_AK37 VCC_G42 J30 AC70 VCCGT VCCGT W67
Place the PU AK40 VCC_AK38 VCC_J30 J33 AC71 VCCGT VCCGT W68
2
resistors close to CPU AL33 VCC_AK40 VCC_J33 J37 J43 VCCGT VCCGT W69
RC180 AL37 VCC_AL33 VCC_J37 J40 J45 VCCGT VCCGT W70
220_0402_5% AL40 VCC_AL37 VCC_J40 K33 J46 VCCGT VCCGT W71
SOC_SVID_ALERT# 1 2 AM32 VCC_AL40 VCC_K33 K35 J48 VCCGT VCCGT Y62
SOC_SVID_ALERT#_R <40> AM33 VCC_AM32 VCC_K35 K37 J50 VCCGT VCCGT
SOC_SVID_DAT To VR AM35 VCC_AM33 VCC_K37 K38 J52 VCCGT
SOC_SVID_DAT <40> AM37 VCC_AM35 VCC_K38 K40 J53 VCCGT AK42
AM38 VCC_AM37 VCC_K40 K42 J55 VCCGT VCCGTX_AK42 AK43
G30 VCC_AM38 VCC_K42 K43 J56 VCCGT VCCGTX_AK43 AK45
VCC_G30 VCC_K43 J58 VCCGT VCCGTX_AK45 AK46
K32 E32
Trace Length < 25 mils J60 VCCGT VCCGTX_AK46 AK48
RSVD_K32 VCC_SENSE VCCSENSE <40> VCCGT VCCGTX_AK48
E33 K48 AK50
AK32 VSS_SENSE VSSSENSE <40> K50 VCCGT VCCGTX_AK50 AK52
#544924 SKL EDS1.2 P.141 RSVD_AK32 SOC_SVID_ALERT# VCCGT VCCGTX_AK52
VCCOPC 1.0V 3.2A B63 K52 AK53
2 AB62 VIDALERT# A63 SOC_SVID_CLK K53 VCCGT VCCGTX_AK53 AK55 2
VCC_OPC_1P8 1.8V 50mA VCCOPC_AB62 VIDSCK SOC_SVID_DAT SOC_SVID_CLK <40> VCCGT VCCGTX_AK55
P62 D64 K55 AK56
VCCEOPIO 0.8V,1.0V 2A V62 VCCOPC_P62 VIDSOUT K56 VCCGT VCCGTX_AK56 AK58
VCCOPC_V62 G20 K58 VCCGT VCCGTX_AK58 AK60
+1.0VS_VCCSTG
H63 VCCSTG_G20 K60 VCCGT VCCGTX_AK60 AK70
VCC_OPC_1P8_H63 L62 VCCGT VCCGTX_AK70 AL43
For CPU2+3e SKU VCCGT VCCGTX_AL43 For CPU2+3e SKU
G61 L63 AL46
VCC_OPC_1P8_G61 L64 VCCGT VCCGTX_AL46 AL50
VCCOPC_SENSE AC63
+1.0VS(SUSP#) L65 VCCGT VCCGTX_AL50 AL53
T132 @ VSSOPC_SENSE VCCOPC_SENSE VCCGT VCCGTX_AL53
AE63 L66 AL56
T133 @ VSSOPC_SENSE VCCGT VCCGTX_AL56
L67 AL60
AE62 L68 VCCGT VCCGTX_AL60 AM48
AG62 VCCEOPIO L69 VCCGT VCCGTX_AM48 AM50
VCCEOPIO L70 VCCGT VCCGTX_AM50 AM52
VCCEOPIO_SENSE AL63 L71 VCCGT VCCGTX_AM52 AM53
T137 @ VSSEOPIO_SENSE AJ62 VCCEOPIO_SENSE VCCGT VCCGTX_AM53
M62 AM56
T139 @ VSSEOPIO_SENSE VCCGT VCCGTX_AM56
12 OF 20 N63 AM58
N64 VCCGT VCCGTX_AM58 AU58
N66 VCCGT VCCGTX_AU58 AU63
SKL-U_BGA1356
@ N67 VCCGT VCCGTX_AU63 BB57
N69 VCCGT VCCGTX_BB57 BB66
VCCGT VCCGTX_BB66
VCCGT_SENSE J70 AK62 VCCGTX_SENSE
<40> VCCGT_SENSE VSSGT_SENSE VCCGT_SENSE VCCGTX_SENSE T155 @
J69 AL61 VSSGTX_SENSE T219 @
<40> VSSGT_SENSE VSSGT_SENSE VSSGTX_SENSE
Trace Length < 25 mils 13 OF 20

SKL-U_BGA1356
@
3 3
4 4

SKL-U(10/12)Power,SVID
A B C D E

A B C D E
1 1
UC1P SKL - U UC1Q SKL - U
R ev _0 . 5 3 R ev _0 . 5 3 UC1R SKL - U
GND 1 OF 3 GND 2 OF 3
GND 3 OF 3
R ev _0 . 5 3
A5 AL65 AT63 BA49 F8 L18
A67 VSS VSS AL66 AT68 VSS VSS BA53 G10 VSS VSS L2
A70 VSS VSS AM13 AT71 VSS VSS BA57 G22 VSS VSS L20
AA2 VSS VSS AM21 AU10 VSS VSS BA6 G43 VSS VSS L4
AA4 VSS VSS AM25 AU15 VSS VSS BA62 G45 VSS VSS L8
AA65 VSS VSS AM27 AU20 VSS VSS BA66 G48 VSS VSS N10
AA68 VSS VSS AM43 AU32 VSS VSS BA71 G5 VSS VSS N13
AB15 VSS VSS AM45 AU38 VSS VSS BB18 G52 VSS VSS N19
AB16 VSS VSS AM46 AV1 VSS VSS BB26 G55 VSS VSS N21
AD13 VSS VSS AM68 AV71 VSS VSS BB43 G63 VSS VSS P17
AD16 VSS VSS AM71 AW10 VSS VSS BB55 G66 VSS VSS P19
AD19 VSS VSS AM8 AW12 VSS VSS BB6 H15 VSS VSS P20
AD20 VSS VSS AN20 AW14 VSS VSS BB60 H18 VSS VSS P21
AD21 VSS VSS AN23 AW16 VSS VSS BB64 H71 VSS VSS R13
AD62 VSS VSS AN28 AW18 VSS VSS BB67 J11 VSS VSS R6
AD8 VSS VSS AN30 AW21 VSS VSS BB70 J13 VSS VSS T15
AE64 VSS VSS AN32 AW23 VSS VSS C1 J25 VSS VSS T17
AE67 VSS VSS AN37 AW30 VSS VSS D10 J35 VSS VSS T21
AE68 VSS VSS AN38 AW32 VSS VSS D11 J38 VSS VSS T4
2 AE69 VSS VSS AN40 AW34 VSS VSS D14 J42 VSS VSS U10 2
AF1 VSS VSS AN42 AW36 VSS VSS D18 J8 VSS VSS U63
AF10 VSS VSS AN58 AW38 VSS VSS D22 K16 VSS VSS U64
AF15 VSS VSS AN63 AW41 VSS VSS D25 K18 VSS VSS U66
AF17 VSS VSS AP10 AW43 VSS VSS D26 K22 VSS VSS U67
AF63 VSS VSS AP23 AW49 VSS VSS D39 K64 VSS VSS V16
AG16 VSS VSS AP28 AW51 VSS VSS D44 K65 VSS VSS V17
AG17 VSS VSS AP32 AW53 VSS VSS D45 K66 VSS VSS V18
AG18 VSS VSS AP35 AW55 VSS VSS D47 K67 VSS VSS W13
AG21 VSS VSS AP58 AW60 VSS VSS D58 K71 VSS VSS Y17
AG71 VSS VSS AP63 AW62 VSS VSS D6 L11 VSS VSS Y19
AH13 VSS VSS AP68 AW64 VSS VSS D62 L16 VSS VSS Y20
AH6 VSS VSS AP70 AW66 VSS VSS D66 L17 VSS VSS Y21
AH63 VSS VSS AR11 AW8 VSS VSS D69 VSS VSS
AH64 VSS VSS AR15 AY66 VSS VSS E11
AH67 VSS VSS AR16 B10 VSS VSS E15 18 OF 20
AJ15 VSS VSS AR20 B14 VSS VSS E18
AJ18 VSS VSS AR23 B18 VSS VSS E21 SKL-U_BGA1356
AJ20 VSS VSS AR28 B22 VSS VSS E46 @
AJ4 VSS VSS AR35 B30 VSS VSS E50
AK11 VSS VSS AR42 B34 VSS VSS E53
3 AK27 VSS VSS AR5 B58 VSS VSS F1 3
AK63 VSS VSS AR50 B62 VSS VSS F13
AK8 VSS VSS AR55 BA1 VSS VSS F23
AL2 VSS VSS AR58 BA10 VSS VSS F27
AL35 VSS VSS AT2 BA2 VSS VSS F33
AL52 VSS VSS AT4 F68 VSS VSS F40
AL58 VSS VSS AT56 VSS VSS BA41
AL64 VSS VSS AT58 VSS
VSS VSS
16 OF 20 17 OF 20
SKL-U_BGA1356 SKL-U_BGA1356
@ @
4 4
2016/07/18
Compal Secret Data
2016/11/10 Title
SKL-U(11/12)GND
A B C D E

A B C D E
1 1
UC1S SKL - U
Rev_0.53
RESERVED SIGNALS-1
@ T167 CFG0 E68 BB68 T156 @

CFG1 B67 CFG[0] RSVD_TP_BB68 BB69
@ T168 CFG[1] RSVD_TP_BB69 T157 @
@ T169 CFG2 D65
CFG3 D67 CFG[2] AK13
@ T170 CFG[3] RSVD_TP_AK13 T158 @
@ T171 CFG4 E70 AK12 T159 @
CFG5 C68 CFG[4] RSVD_TP_AK12
@ T172 CFG[5]
@ T173 CFG6 D68 BB2
CFG7 C67 CFG[6] RSVD_BB2 BA3
@ T174 CFG[7] RSVD_BA3
@ T175 CFG8 F71
CFG9 G69 CFG[8]
@ T176 CFG[9]
@ T177 CFG10 F70 AU5 T162 @
CFG11 G68 CFG[10] TP5 AT5
@ T178 CFG[11] TP6 T163 @
CFG12 H70 +1.8VALW_PRIM
@ T179 CFG[12]
@ T180 CFG13 G71
CFG14 H69 CFG[13] D5
@ T181 CFG[14] RSVD_D5
@ T182 CFG15 G70 D4 UC1T SKL - U
CFG[15] RSVD_D4
2
B2
RSVD_B2 Rev_0.53
@ T183 CFG16 E63 C2 @ RC57 S PA R E
CFG17 F63 CFG[16] RSVD_C2
@ T184 CFG[17] 0_0402_5%
B3 AW69 F6
CFG18 E66 RSVD_B3 A3 AW68 RSVD_AW69 RSVD_F6 E3
@ T186
1
CFG19 F66 CFG[18] RSVD_A3 AU56 RSVD_AW68 RSVD_E3 C11
@ T188 CFG[19] RSVD_AU56 RSVD_C11
AW1 AW48 B11
CFG_RCOMP E60 RSVD_AW1 C7 RSVD_AW48 RSVD_B11 A11
CFG_RCOMP E1 U12 RSVD_C7 RSVD_A11 D12
XDP_ITP_PMODE E8 RSVD_E1 E2 U11 RSVD_U12 RSVD_D12 C12
@ T189 ITP_PMODE RSVD_E2 RSVD_U11 RSVD_C12
2 H11 F52 2
AY2 BA4 RSVD_H11 RSVD_F52
AY1 RSVD_AY2 RSVD_BA4 BB4 20 OF 20
RSVD_AY1 RSVD_BB4 1
D1 A4 CC79 SKL-U_BGA1356
D3 RSVD_D1 RSVD_A4 C4 1U_0402_6.3V6K @
RSVD_D3 RSVD_C4 2
@
K46 BB5 T199 @
K45 RSVD_K46 TP4
RSVD_K45 A69
CC79 near U11,U12 (<10 mm)
AL25 RSVD_A69 B69
AL27 RSVD_AL25 RSVD_B69
RSVD_AL27 AY3 1 2 0_0402_5%
14MOW52, Connect U11, U12 to 1.8V for
RC182 @
C71 RSVD_AY3 Cannonlake-U PCH compat i bili t y
B70 RSVD_C71 D71
RSVD_B70 RSVD_D71 C70
F60 RSVD_C70
RSVD_F60 C54
A52 RSVD_C54 D54
RSVD_A52 RSVD_D54
BA70 AY4
For 2+3e Solut i on
T213 @ RSVD_TP_BA70 TP1 T214 @
BA68 BB3 T216 @
T215 @ RSVD_TP_BA68 TP2 PM_ZVM#
J71 AY71 RC183 1 @ 2 0_0402_5% Zero Voltage Mode: Control Signal to OPC
2 1 CFG_RCOMP J68 RSVD_J71 VSS_AY71 AR56 PM_ZVM#
49.9_0402_1% RC185 RSVD_J68 ZVM# T225 @ VR, when low OPC VR output is 0V.
F65 AW71 T221 @
T220 @ VSS_F65 RSVD_TP_AW71
2 1 CFG4
T222 @
G65 AW70 T223 @ PM_MSM#
VSS_G65 RSVD_TP_AW70
1K_0402_1% RC193 Minimum Speed Mode: Control signal to
F61 AP56 PM_MSM# +1.0V_VCCST
E61 RSVD_F61 MSM# C64
T230 @ VccEOPIO VR (connected only in 2 VR
RSVD_E61 PROC_SELECT# solut i on f or OPC).
3 19 OF 20 SKL_CNL# 1 @ 2 3
RC184 100K_0402_5%
SKL-U_BGA1356
@ #544669 CRB1.1 P.54
#544924 SKL EDS1.2 P.125
PROC_SELECT#
Display Port Presence Strap This pin is for compat i bili t y wit h f ut ur e
plat f or ms. It s houl d be unc onnect ed f or
1 : Disabled; No Physical Display Port the processor.
CFG4 at t ac hed t o E mbedded Di s pl ay Port
0 : Enabled; An external Display Port device is
connected to the Embedded Display Port
4 4

SKL-U(12/12)RSVD
A B C D E

A B C D E
+1.2V_VDDQ +1.2V_VDDQ
<8> DDR_A_DQS#[0..7]
1
JDIMM1
VSS VSS
2
Reverse Type
DDR_A_D4 3 4 DDR_A_D1
<8> DDR_A_D[0..63] DQ5 DQ4
5 6
DDR_A_D0 7 VSS VSS 8 DDR_A_D5 2-3A to 1 DIMMs/channel
<8> DDR_A_DQS[0..7] DQ1 DQ0
9 10
DDR_A_DQS#0 11 VSS VSS 12
DDR_A_DQS0 13 DQS0_C DM0*/DBI0* 14
<8> DDR_A_MA[0..16] DQS0_T VSS DDR_A_D3
15 16
DDR_A_BA0 DDR_A_D7 17 VSS DQ6 18
<8> DDR_A_BA0 DDR_A_BA1 DQ7 VSS DDR_A_D2
19 20
<8> DDR_A_BA1 DDR_A_BG0 DDR_A_D6 VSS DQ2
21 22
<8> DDR_A_BG0 DDR_A_BG1 DQ3 VSS DDR_A_D8
23 24
<8> DDR_A_BG1 DDR_A_ACT# DDR_A_D12 VSS DQ12
25 26
<8> DDR_A_ACT# DDR_A_ALERT# DQ13 VSS DDR_A_D13
27 28
<8> DDR_A_ALERT# DDR_A_PAR DDR_A_D9 VSS DQ8
1 29 30 1
<8> DDR_A_PAR DQ9 VSS DDR_A_DQS#1
31 32
33 VSS DQS1_C 34 DDR_A_DQS1
35 DM1*/DBI1* DQS1_T 36
DDR_A_CLK0 DDR_A_D15 37 VSS VSS 38 DDR_A_D11
<8> DDR_A_CLK0 DDR_A_CLK#0 DQ15 DQ14
39 40
<8> DDR_A_CLK#0 DDR_A_CLK1 DDR_A_D14 VSS VSS DDR_A_D10
41 42
<8> DDR_A_CLK1 DDR_A_CLK#1 DQ10 DQ11
43 44
<8> DDR_A_CLK#1 DDR_A_D21 VSS VSS DDR_A_D17
45 46
47 DQ21 DQ20 48
DDR_A_CKE0 DDR_A_D20 49 VSS VSS 50 DDR_A_D19
<8> DDR_A_CKE0 DDR_A_CKE1 DQ17 DQ16
51 52
<8> DDR_A_CKE1 DDR_A_CS#0 DDR_A_DQS#2 VSS VSS
53 54
<8> DDR_A_CS#0 DDR_A_CS#1 DDR_A_DQS2 DQS2_C DM2*/DBI2*
55 56
<8> DDR_A_CS#1 DQS2_T VSS DDR_A_D16
57 58
DDR_A_D22 59 VSS DQ22 60
SOC_SMBDATA_1 61 DQ23 VSS 62 DDR_A_D23
<9,20> SOC_SMBDATA_1 SOC_SMBCLK_1 DDR_A_D18 VSS DQ18
63 64
<9,20> SOC_SMBCLK_1 DQ19 VSS DDR_A_D24
65 66
DDR_A_D28 67 VSS DQ28 68
DDR_A_ODT0 69 DQ29 VSS 70 DDR_A_D25
<8> DDR_A_ODT0 DDR_A_ODT1 DDR_A_D29 VSS DQ24
71 72
<8> DDR_A_ODT1 DQ25 VSS DDR_A_DQS#3
73 74
+1.2V_VDDQ 75 VSS DQS3_C 76 DDR_A_DQS3
77 DM3*/DBI3* DQS3_T 78
DDR_A_D26 79 VSS VSS 80 DDR_A_D27
Not e : DQ30 DQ31
Layout Note: 81 82
Check voltage tolerance of DDR_A_D30 83 VSS VSS 84 DDR_A_D31
Place near JDIMM1
2
VREF_DQ at the DIMM socket 85 DQ26 DQ27 86
RD58 RD59 87 VSS VSS 88 +1.2V_VDDQ
89 CB5_NC CB4_NC 90
240_0402_1% 240_0402_1%
91 VSS VSS 92
93 CB1_NC CB0_NC 94
1
DDR_A_DQS#8 95 VSS VSS 96
+1.2V_VDDQ DDR_A_DQS8 97 DQS8_C DM8*/DBI8* 98 RD1
99 DQS8_T VSS 100 470_0402_5%
101 VSS CB6_NC 102
103 CB2_NC VSS 104
2
VSS CB7_NC
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
105 106
2
107 CB3_NC VSS 108 DDR_DRAMRST# 2
1 1 1 1 1 1 1 1 DDR_A_CKE0 VSS RESET* DDR_A_CKE1 DDR_DRAMRST# <8,20>
109 110
CKE0 CKE1
CD4
CD5
CD6
CD7
CD8
CD9
CD57
CD56
111 112
DDR_A_BG1 113 VDD1 VDD2 114 DDR_A_ACT#
2 2 2 2 2 2 2 2 DDR_A_BG0 115 BG1 ACT* 116 DDR_A_ALERT#
117 BG0 ALERT* 118 +1.2V_VDDQ
DDR_A_MA12 119 VDD3 VDD4 120 DDR_A_MA11
DDR_A_MA9 121 A12 A11 122 DDR_A_MA7
2
123 A9 A7 124
DDR_A_MA8 125 VDD5 VDD6 126 DDR_A_MA5 RD60
DDR_A_MA6 127 A8 A5 128 DDR_A_MA4
240_0402_1%
129 A6 A4 130
+1.2V_VDDQ DDR_A_MA3 131 VDD7 VDD8 132 DDR_A_MA2
1
DDR_A_MA1 133 A3 A2 134 DDR_A_EVENT#
Follow MA51 135 A1 EVENT* 136
DDR_A_CLK0 137 VDD9 VDD10 138 DDR_A_CLK1
DDR_A_CLK#0 CK0_T CK1_T DDR_A_CLK#1
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1 139 140
141 CK0_C CK1_C 142
+ CD16 DDR_A_PAR 143 VDD11 VDD12 144 DDR_A_MA0
1 1 1 1 1 1 1 1 PARITY A0
CD10
CD11
CD12
CD13
CD14
CD19
CD15
CD20
330U_D2_2V_Y
@
2
2 2 2 2 2 2 2 2 SGA00009S00 DDR_A_BA1 DDR_A_MA10
145 146
330U 2V H1.9 147 BA1 A10_AP 148
9mohm POLY DDR_A_CS#0 149 VDD13 VDD14 150 DDR_A_BA0
DDR_A_MA14 151 S0* BA0 152 DDR_A_MA16
153 A14_WE* A16_RAS* 154
DDR_A_ODT0 155 VDD15 VDD16 156 DDR_A_MA15 +1.2V_VDDQ
DDR_A_CS#1 157 ODT0 A15_CAS* 158 DDR_A_MA13
159 S1* A13 160 +0.6V_DDRA_VREFCA +0.6V_A_VREFCA
1
DDR_A_ODT1 161 VDD17 VDD18 162
ODT1 S2*/C0 10mi l s
Layout Note: Layout Note: 163 164 RD9
165 VDD19 VREFCA 166 DDR_A_SA2 1K_0402_1%
Place near JDIMM1.257,259 Place near JDIMM1.255 167 S3*/C1 SA2 168
DDR_A_D33 169 VSS VSS 170 DDR_A_D32 RD10
1
2
171 DQ37 DQ36 172 2_0402_1%
DDR_A_D36 173 VSS VSS 174 DDR_A_D37 CD1 1 2
175 DQ33 DQ32 176 .1U_0402_16V7K 1
DDR_A_DQS#4 177 VSS VSS 178 2
3 3
+3VS DDR_A_DQS4 179 DQS4_C DM4*/DBI4* 180
+2.5V CD21
1
181 DQS4_T VSS 182 DDR_A_D38 0.022U_0402_16V7K
DDR_A_D35 183 VSS DQ39 184 2
RD11
185 DQ38 VSS 186 DDR_A_D39 1K_0402_1%
1
DDR_A_D34 VSS DQ35
10U_0603_6.3V6M
1U_0402_6.3V6K
187 188
189 DQ34 VSS 190 DDR_A_D44
1 1 1 RD12
2
DDR_A_D40 191 VSS DQ45 192 24.9_0402_1%
DQ44 VSS DDR_A_D45
CD61
CD60
CD27 193 194

DDR_A_D41 195 VSS DQ41 196
.1U_0402_16V7K
2
2 2 2 197 DQ40 VSS 198 DDR_A_DQS#5
199 VSS DQS5_C 200 DDR_A_DQS5
201 DM5*/DBI5* DQS5_T 202
DDR_A_D43
205 DQ46
VSS
DQ47
VSS
206
DDR_A_D47
Place near to SO-DIMM connector.
207 208
209 DQ42 DQ43 210
213 DQ52 DQ53 214
217 DQ49 DQ48 218
+3VS DDR_A_DQS#6 219 VSS VSS 220
DDR_A_DQS6 DQS6_C DM6*/DBI6* Layout Note:
221 222
223 DQS6_T VSS 224 DDR_A_D55 Place near JDIMM1.258
DDR_A_D50 225 VSS DQ54 226
1
227 DQ55 VSS 228 DDR_A_D54

DDR_A_D51 VSS DQ50
0_0402_5%
RD40
0_0402_5%
RD41
0_0402_5%
RD42
229 230
231 DQ51 VSS 232 DDR_A_D58
DDR_A_D56 233 VSS DQ60 234
235 DQ61 VSS 236 DDR_A_D59
@ @ @ +0.6VS_VTT
2
DDR_A_D57 237 VSS DQ57 238

239 DQ56 VSS 240 DDR_A_DQS#7
DDR_A_SA2 241 VSS DQS7_C 242 DDR_A_DQS7
DDR_A_SA1 DM7*/DBI7* DQS7_T
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
243 244
DDR_A_SA0 DDR_A_D63 245 VSS VSS 246 DDR_A_D61
DQ62 DQ63 1 1 1
247 248
1
DDR_A_D60 VSS VSS DDR_A_D62
CD58
CD24
CD25
249 250
DQ58 DQ59
0_0402_5%
RD43
0_0402_5%
RD44
0_0402_5%
RD45
+2.5V +3VS 251 252 +0.6VS_VTT

SOC_SMBCLK_1 253 VSS VSS 254 SOC_SMBDATA_1 2 2 2
4 SCL SDA DDR_A_SA0 4
255 256
@ @ @ 257 VDDSPD SA0 258
2
259 VPP1 VTT 260 DDR_A_SA1

VPP2 SA1
GND
GND
FOX_AS0A827-H2RB-7H
261
262
Interleaved Memory
CONN@
DDR4_DIMMA

A B C D E
A B C D E
+1.2V_VDDQ +1.2V_VDDQ
<8> DDR_B_DQS#[0..7]
1
JDIMM2
VSS VSS
2
Standard Type
DDR_B_D15 3 4 DDR_B_D11
5 DQ5 DQ4 6
<8> DDR_B_D[0..63] DDR_B_D14 7 VSS VSS 8 DDR_B_D10 2-3A to 1 DIMMs/channel
9 DQ1 DQ0 10
<8> DDR_B_DQS[0..7] DDR_B_DQS#1 VSS VSS
11 12
DDR_B_DQS1 13 DQS0_C DM0*/DBI0* 14
15 DQS0_T VSS 16 DDR_B_D13
<8> DDR_B_MA[0..16] DDR_B_D8 VSS DQ6
17 18
DDR_B_BA0 19 DQ7 VSS 20 DDR_B_D9
<8> DDR_B_BA0 DDR_B_BA1 DDR_B_D12 VSS DQ2
21 22
<8> DDR_B_BA1 DDR_B_BG0 DQ3 VSS DDR_B_D5
23 24
<8> DDR_B_BG0 DDR_B_BG1 DDR_B_D4 VSS DQ12
25 26
<8> DDR_B_BG1 DDR_B_ACT# DQ13 VSS DDR_B_D1
27 28
<8> DDR_B_ACT# DDR_B_ALERT# DDR_B_D0 VSS DQ8
1 29 30 1
<8> DDR_B_ALERT# DDR_B_PAR DQ9 VSS DDR_B_DQS#0
31 32
<8> DDR_B_PAR VSS DQS1_C DDR_B_DQS0
33 34
35 DM1*/DBI1* DQS1_T 36
DDR_B_D6 37 VSS VSS 38 DDR_B_D3
DDR_B_CLK0 39 DQ15 DQ14 40
<8> DDR_B_CLK0 DDR_B_CLK#0 DDR_B_D7 VSS VSS DDR_B_D2
41 42
<8> DDR_B_CLK#0 DDR_B_CLK1 DQ10 DQ11
43 44
<8> DDR_B_CLK1 DDR_B_CLK#1 DDR_B_D20 VSS VSS DDR_B_D16
45 46
<8> DDR_B_CLK#1 47 DQ21 DQ20 48
DDR_B_CKE0 51 DQ17 DQ16 52
<8> DDR_B_CKE0 DDR_B_CKE1 DDR_B_DQS#2 VSS VSS
53 54
<8> DDR_B_CKE1 DDR_B_CS#0 DDR_B_DQS2 DQS2_C DM2*/DBI2*
55 56
<8> DDR_B_CS#0 DDR_B_CS#1 DQS2_T VSS DDR_B_D18
57 58
<8> DDR_B_CS#1 DDR_B_D22 VSS DQ22
59 60
61 DQ23 VSS 62 DDR_B_D19
SOC_SMBDATA_1 DDR_B_D23 63 VSS DQ18 64
<9,19> SOC_SMBDATA_1 SOC_SMBCLK_1 DQ19 VSS DDR_B_D24
65 66
<9,19> SOC_SMBCLK_1 DDR_B_D29 VSS DQ28
67 68
69 DQ29 VSS 70 DDR_B_D25
DDR_B_ODT0 DDR_B_D28 71 VSS DQ24 72
<8> DDR_B_ODT0 DDR_B_ODT1 DQ25 VSS DDR_B_DQS#3
73 74
<8> DDR_B_ODT1 +1.2V_VDDQ VSS DQS3_C DDR_B_DQS3
75 76
77 DM3*/DBI3* DQS3_T 78
81 DQ30 DQ31 82
Layout Note: DDR_B_D31 VSS VSS DDR_B_D27
83 84
Place near JDIMM2
2
85 DQ26 DQ27 86
RD61 RD62 87 VSS VSS 88
89 CB5_NC CB4_NC 90
240_0402_1% 240_0402_1%
91 VSS VSS 92
93 CB1_NC CB0_NC 94
1
DDR_B_DQS#8 95 VSS VSS 96
+1.2V_VDDQ DDR_B_DQS8 97 DQS8_C DM8*/DBI8* 98
99 DQS8_T VSS 100
101 VSS CB6_NC 102
CB2_NC VSS
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
103 104
105 VSS CB7_NC 106
2 1 1 1 1 1 1 1 1 CB3_NC VSS DDR_DRAMRST# 2
107 108
DDR_B_CKE0 VSS RESET* DDR_B_CKE1 DDR_DRAMRST# <8,19>
CD32
CD33
CD34
CD35
CD36
CD37
CD69
CD70
109 110
111 CKE0 CKE1 112
2 2 2 2 2 2 2 2 DDR_B_BG1 VDD1 VDD2 DDR_B_ACT# 1
113 114 CD30
DDR_B_BG0 115 BG1 ACT* 116 DDR_B_ALERT# .1U_0402_16V7K
117 BG0 ALERT* 118 +1.2V_VDDQ @ESD@
DDR_B_MA12 119 VDD3 VDD4 120 DDR_B_MA11 2
DDR_B_MA9 121 A12 A11 122 DDR_B_MA7
2
123 A9 A7 124
DDR_B_MA8 125 VDD5 VDD6 126 DDR_B_MA5 RD63
DDR_B_MA6 127 A8 A5 128 DDR_B_MA4
240_0402_1%
+1.2V_VDDQ 129 A6 A4 130
DDR_B_MA3 131 VDD7 VDD8 132 DDR_B_MA2
1
DDR_B_MA1 133 A3 A2 134 DDR_B_EVENT#
135 A1 EVENT* 136
DDR_B_CLK0 137 VDD9 VDD10 138 DDR_B_CLK1
DDR_B_CLK#0 CK0_T CK1_T DDR_B_CLK#1
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
139 140
141 CK0_C CK1_C 142
1 1 1 1 1 1 1 1 VDD11 VDD12
DDR_B_PAR DDR_B_MA0
CD38
CD39
CD40
CD41
CD42
CD43
CD44
CD45
143 144
PARITY A0
2 2 2 2 2 2 2 2
DDR_B_BA1 145 146 DDR_B_MA10
147 BA1 A10_AP 148
DDR_B_CS#0 149 VDD13 VDD14 150 DDR_B_BA0
DDR_B_MA14 151 S0* BA0 152 DDR_B_MA16
153 A14_WE* A16_RAS* 154
DDR_B_ODT0 155 VDD15 VDD16 156 DDR_B_MA15 +1.2V_VDDQ
DDR_B_CS#1 157 ODT0 A15_CAS* 158 DDR_B_MA13
159 S1* A13 160 +0.6V_DDRB_VREFCA +0.6V_B_VREFCA
1
DDR_B_ODT1 161 VDD17 VDD18 162
ODT1 S2*/C0 10mi l s
Layout Note: Layout Note: 163 164 RD46
165 VDD19 VREFCA 166 DDR_B_SA2 1K_0402_1%
Place near JDIMM1.257,259 Place near JDIMM2.255 167 S3*/C1 SA2 168
DDR_B_D33 169 VSS VSS 170 DDR_B_D36 RD49
1
2
171 DQ37 DQ36 172 2_0402_1%
DDR_B_D32 173 VSS VSS 174 DDR_B_D37 CD65 1 2
175 DQ33 DQ32 176 .1U_0402_16V7K 1
DDR_B_DQS#4 177 VSS VSS 178 2
3 3
+3VS DDR_B_DQS4 179 DQS4_C DM4*/DBI4* 180
+2.5V CD66
1
181 DQS4_T VSS 182 DDR_B_D38 0.022U_0402_16V7K
DDR_B_D35 183 VSS DQ39 184 2
RD47
185 DQ38 VSS 186 DDR_B_D39 1K_0402_1%
1
DDR_B_D34 VSS DQ35
10U_0603_6.3V6M
1U_0402_6.3V6K
187 188
2.2U_0402_6.3V6M
189 DQ34 VSS 190 DDR_B_D44

1 1 RD50
2
1
DDR_B_D40 191 VSS DQ45 192 24.9_0402_1%

DQ44 VSS DDR_B_D45
CD68
CD67
CD55
193 194
DDR_B_D41 195 VSS DQ41 196
2
2
2 2 197 DQ40 VSS 198 DDR_B_DQS#5
199 VSS DQS5_C 200 DDR_B_DQS5
201 DM5*/DBI5* DQS5_T 202
DDR_B_D46
205 DQ46
VSS
DQ47
VSS
206
DDR_B_D42
Place near to SO-DIMM connector.
207 208
209 DQ42 DQ43 210
213 DQ52 DQ53 214
217 DQ49 DQ48 218
DDR_B_DQS#6 219 VSS VSS 220
DDR_B_DQS6 DQS6_C DM6*/DBI6* Layout Note:
221 222
223 DQS6_T VSS 224 DDR_B_D55 Place near JDIMM1.258
+3VS DDR_B_D50 225 VSS DQ54 226
227 DQ55 VSS 228 DDR_B_D54
DDR_B_D51 229 VSS DQ50 230
231 DQ51 VSS 232 DDR_B_D60
1
DDR_B_D56 233 VSS DQ60 234

DQ61 VSS DDR_B_D57
0_0402_5%
RD51
0_0402_5%
RD52
0_0402_5%
RD53
235 236 +0.6VS_VTT

DDR_B_D61 237 VSS DQ57 238
239 DQ56 VSS 240 DDR_B_DQS#7
241 VSS DQS7_C 242 DDR_B_DQS7
@ @ @
2
DM7*/DBI7* DQS7_T
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
243 244
DDR_B_SA2 DQ62 DQ63 1 1 1
247 248
DDR_B_SA1 DDR_B_D58 VSS VSS DDR_B_D63
CD64
CD62
CD63
249 250
DDR_B_SA0 +2.5V +3VS 251 DQ58 DQ59 252 +0.6VS_VTT
SOC_SMBCLK_1 253 VSS VSS 254 SOC_SMBDATA_1 2 2 2
1
4 SCL SDA DDR_B_SA0 4

0_0402_5%
RD54
0_0402_5%
RD55
0_0402_5%
RD56
255 256
257 VDDSPD SA0 258
259 VPP1 VTT 260 DDR_B_SA1
@ @ @ VPP2 SA1
2
261
Interleaved Memory
GND 262
GND
FOX_AS0A827-H2SB-7H
CONN@
DDR4_DIMMB

A B C D E
A B C D E
LCD POWER CIRCUIT

+3VS +LCDVDD +19VB +INVPWR_B+ Place closed to JEDP1
UX1
W=60mils
1U_0402_6.3V6K
CX1
5 1 +LCDVDD
1
IN OUT W=60mils LX1 W=60mils +3VS
2 1 1 HCB2012KF-221T30_0805
GND 1 2
1 1
4 3 CX4 EMI@ 1 1
2 EN OC
1000P_0402_50V7K
CX5
.1U_0402_16V7K SM01000EJ00 3000ma 1 1
SY6288C20AAC_SOT23-5 CX3 2 2 CX2 CX6 CX7
@ 220o hm @ 100 m h z
4.7U_0603_6.3V6K DCR 0.04 68P_0402_50V8J .1U_0402_16V7K .1U_0402_16V7K
2 2
@EMI@
@EMI@
<7> SOC_ENVDD 2 2 @
1
RX9
100K_0402_5%
@
2
JEDP1
<7> EDP_TXP0
CX8 1 2 .1U_0402_16V7K EDP_TXP0_C
+INVPWR_B+
W=60mils 1
CX9 1 2 .1U_0402_16V7K EDP_TXN0_C 2 1 41
<7> EDP_TXN0 EDP_TXP1_C 2 G1
CX10 1 2 .1U_0402_16V7K 3 42
<7> EDP_TXP1 EDP_TXN1_C 3 G2
CX11 1 2 .1U_0402_16V7K 4 43
<7> EDP_TXN1 4 G3
5 44
SOC_BKL_PWM RX1 1 @ 2 100K_0402_5% SOC_BKL_PWM 6 5 G4 45
<7> SOC_BKL_PWM 6 G5
BKOFF# 7 46
CX14 1 2 .1U_0402_16V7K EDP_AUXP_C @EMI@ EDP_HPD 8 7 G6
<7> EDP_A UXP EDP_AUXN_C 8
CX15 1 2 .1U_0402_16V7K CX12 1 2 220P_0402_50V7K 9
<7> EDP_A UXN +LCDVDD 9
@EMI@ 10
BKOFF# CX13 1 2 220P_0402_50V7K 11 10
<29> BKOFF# 11
2 12 2
RX2 1 @ 2 10K_0402_5% EDP_AUXN_C 13 12
+3VS EDP_AUXP_C 14 13
15 14
100K_0402_5% 1 @ 2 RX3 EDP_AUXN_C EDP_TXP0_C 16 15
100K_0402_5% 1 @ 2 RX4 EDP_AUXP_C EDP_TXN0_C 17 16
RX5 18 17
0_0402_5% EDP_TXP1_C 19 18
1 @ 2 EDP_HPD EDP_TXN1_C 20 19
<7> CPU_ED P_HPD 20
21
RX6 22 21
100K_0402_5% 23 22
2 1 24 23
25 24
26 25
Touch Screen +TS_PWR
27 26
27
28
+5VS +3VS +TS_PWR TS_EN 29 28
<12,29> TS_EN USB20_P6 29
30
<13> USB20_P6 USB20_N6 30
RX7 1 @ 2 0_0603_5% 31
<13> USB20_N6 I2C_0_SCL 31
RX8 1 @ 2 0_0603_5% Touch Screen 32
<12> I2C_0_SCL I2C_0_SDA 32
33
<12> I2C_0_SDA I2C_TS_RST# 33
34
<29> I2C_TS_RST# I2C_TS_INT# 34
35
<7> I2C_TS_INT# 35
36
37 36
+3VS USB20_P7_CAMERA 37
38
USB20_N7_CAMERA 39 38
For Camera 39
40
3 Camera 40 3
STARC_107K40-000001-G2
@EMI@ CONN@
USB20_N7 RX10 1 2 0_0402_5% USB20_N7_CAMERA
<13> USB20_N7 SP01000XE00
@EMI@
USB20_P7 RX11 1 2 0_0402_5% USB20_P7_CAMERA
<13> USB20_P7
4 4

eDP Connector
A B C D E

A B C D E
@EMI@
HDMI_C_CLK- RY1 1 2 0_0402_5% HDMI_R_CK-
+5VS
W=40m ils +HDMI_5V_OUT
@EMI@
HDMI_C_CLK+ RY2 1 2 0_0402_5% HDMI_R_CK+
UY1
RPY1
3 470_8P4R_5%
OUT CY4 2 1 .1U_0402_16V7K HDMI_C_TX1- 1 8
1 <7> SOC_DP2_N1
1 CY3 2 1 .1U_0402_16V7K HDMI_C_TX1+ 2 7
IN <7> SOC_DP2_P1
1 CY9 CY1 2 1 .1U_0402_16V7K HDMI_C_TX2+ 3 6 1
<7> SOC_DP2_P0
2 .1U_0402_16V7K <7> SOC_DP2_N0 CY2 2 1 .1U_0402_16V7K HDMI_C_TX2- 4 5
GND 2
HDMI_GND
CY5 2 1 .1U_0402_16V7K HDMI_C_TX0+ 1 8 @EMI@
<7> SOC_DP2_P2
AP2330W-7_SC59-3 CY6 2 1 .1U_0402_16V7K HDMI_C_TX0- 2 7 HDMI_C_TX0- RY3 1 2 0_0402_5% HDMI_R_D0-
<7> SOC_DP2_N2
CY8 2 1 .1U_0402_16V7K HDMI_C_CLK- 3 6
<7> SOC_DP2_N3
CY7 2 1 .1U_0402_16V7K HDMI_C_CLK+ 4 5 @EMI@
<7> SOC_DP2_P3 HDMI_C_TX0+ HDMI_R_D0+
RY4 1 2 0_0402_5%
RPY2
470_8P4R_5%
6
D
+3VS
2 QY1A
G 2N7002KDW_SOT363-6
1
@EMI@
HDMI_C_TX1- RY5 1 2 0_0402_5% HDMI_R_D1-
@EMI@
HDMI_C_TX1+ RY7 1 2 0_0402_5% HDMI_R_D1+
+3VS
+3VS
5
RY6
G
2 1M_0402_5% 2
@EMI@
2
4 3 HDMI_HPD HDMI_C_TX2- RY8 1 2 0_0402_5% HDMI_R_D2-
S
<7> SOC_DP2_HPD
1
@EMI@
QY1B HDMI_C_TX2+ HDMI_R_D2+
RY9 RY10 1 2 0_0402_5%
2N7002KDW_SOT363-6 100K_0402_5%
2
RPY3
HDMI connector
JHDMI1
1 8 HDMI_SDATA HDMI_HPD 19
+HDMI_5V_OUT HDMI_SCLK HP_DET
2 7 +HDMI_5V_OUT
18
3 6 SOC_DP2_CTRL_DATA 17 +5V
+3VS SOC_DP2_CTRL_CLK HDMI_SDATA DDC/CEC_GND
4 5 16
HDMI_SCLK 15 SDA
14 SCL
Utility
3
2.2K_0804_8P4R_5%
13
HDMI_R_CK- 12 CEC
11 CK-
3 HDMI_R_CK+ 10 CK_shield 3
+3VS DY1 HDMI_R_D0- 9 CK+
@ESD@ 8 D0-
YSLC05CH_SOT23-3 HDMI_R_D0+ 7 D0_shield
HDMI_R_D1- 6 D0+
5 D1-
1
HDMI_R_D1+ 4 D1_shield 20
D1+ GND
2
HDMI_R_D2- 3 21
2 D2- GND 22
G
1 6 HDMI_SDATA HDMI_R_D2+ 1 D2_shield GND 23

<7> SOC_DP2_CTRL_DATA D2+ GND
S
YUQIU_H050FD019M190BA
QY2B
CONN@
DMN66D0LDW-7_SOT363-6
DC232004800
5
G
4 3 HDMI_SCLK
<7> SOC_DP2_CTRL_CLK
S
QY2A
Intel spec Ron/Cout : 3ohm/10pF.

SB000016K00, S TR PJT138KA 2N SOT363-6
4 4

HDMI CONN.
A B C D E

A B C D E
+3VALW +3V_LAN
RL1 1 @ 2 0_0805_5%
Change to R-short at PVT if test ok.

60m il 60m il
UL1 @
5 1
IN OUT
2
( Should be place within 200 mils ) 0.1uF close to Pin 3,8,22,30
1 GND Close to U20 Pin23 Close to Pin 24 1uF reserved for Pin 22 0.1uF close to Pin 11,32 1
4 3
EN OC RL13 1 @ 2 0_0805_5%
2 W=6 0 m ils
SY6288C20AAC_SOT23-5 +3V_LAN
CL1 W=6 0 m ils W=6 0 m ils +LAN_VDD +3V_LAN
1U_0402_6.3V6K LAN_PWR_EN LL1
1 LAN_PWR_EN <29>
+REGOUT 1 2
2.2UH +-5%NLC252018T-2R2J-N
0.1U_0402_16V7K
4.7U_0603_6.3V6K
0.1U_0402_16V7K
CL6
1U_0402_6.3V6K
CL7
0.1U_0402_16V7K
CL8
0.1U_0402_16V7K
CL9
0.1U_0402_16V7K
CL10
0.1U_0402_16V7K
CL11
4.7U_0603_6.3V6K
CL12
4.7U_0603_6.3V6K
CL13
0.1U_0402_16V7K
CL14
0.1U_0402_16V7K
2 IDC=1200mA
CL21 8111H@
CL4
CL5
1 8111GUS@ 1 1 1 1 1 1
1
CL2 8111GUS@ CL3 8111GUS@
4.7U_0603_6.3V6K 0.1U_0402_16V7K
2
1
8111GUS@
8111GUS@
@ @ @
2
2 2 2 2 2 2 2
+3V_LAN Rising t i me r equest: 0. 5~100 mS
SA0 00 02 8 Y 1 0
High act i v e.
EN threshold voltage :1.2~2.0V
Current limit threshold :1.5~2.8A
Output turn-on rising t i me: 1. 3~2. 7 ms
UL2
2 2
close to Pin 17, 18
LAN_MIDI0+ 1 17 PCIE_CRX_C_DTX_P5 .1U_0402_16V7K 2 1 CL15 +3V_LAN
LAN_MIDI0- 2 MDIP0 HSOP 18 PCIE_CRX_C_DTX_N5 .1U_0402_16V7K 2 1 CL16 PCIE_CRX_DTX_P5 <13>
SJ10000E800
+LAN_VDD 3 MDIN0 HSON 19 PLT_RST_BUF# PCIE_CRX_DTX_N5 <13>
YL1
LAN_MIDI1+ 4 AVDD10 PERSTB 20 ISOLATEB PLT_RST_BUF# <11,24> 25MHZ_10PF_7V25000014
MDIP1 ISOLATEB
1
LAN_MIDI1- 5 21 LAN_PME# RL2 2 @ 1 0_0402_5%
LAN_MIDI2+ 6 MDIN1 LANWAKEB 22 +LAN_VDD EC_PME# <29> RL12 XTLI 1 3 XTLO
LAN_MIDI2- 7 MDIP2 DVDD10 23 +3V_LAN 10K_0402_5% 1 3
+LAN_VDD 8 MDIN2 VDDREG 24 +REGOUT GND GND
LAN_MIDI3+ AVDD10 REGOUT LAN_LED2 1 1
9 25 T7 @
2
LAN_MIDI3- 10 MDIP3 LED2 26 GPO LAN_PME# CL17 2 4 CL18
PU to +3VS at PCH side +3V_LAN 11 MDIN3 LED1/GPIO 27 LAN_LED0 +3V_LAN
T8 @ 10P_0402_50V8J 12P_0402_50V8J
12 AVDD33 LED0 28 XTLO 2 2
<11> CLKREQ_PCIE#1 13 CLKREQB CKXTAL1 29 XTLI
<13> PCIE_CTX_C_DRX_P5 HSIP CKXTAL2
1
14 30 +LAN_VDD RL3
<13> PCIE_CTX_C_DRX_N5 HSIN AVDD10 LAN_RST
15 31 1 2 RL4
<11> CLK_PCIE_P1 16 REFCLK_P RSET 32 +3V_LAN 2.49K_0402_1% 10K_0402_5%
<11> CLK_PCIE_N1 REFCLK_N AVDD33 33 @
GND
2
GPO RL5 2 @ 1 0_0402_5%
LAN_GPO <29>
Consider VCC33 may be connected to Main
Power or chipset/bios's GPO, the pull-low
resistor RL7 can be NC only when Main Power
UL2 S IC RTL8111H-CG QFN 32P E-LAN CTRL or chipset/bios's GPO can ensure to drive the
SA000080P00 8111H@ ISOLATEB pin to a voltage level < 0.8V at the
Use 8111GS symbol system state S3~S5.
LAN Connector +3VS
RTL8111GS-CG_QFN32_4X4
3 8111GUS@ JRJ45 3
SA00006ML00 RJ45_MIDI0+ 1
PR1+
2
RJ45_MIDI0- 2
PR1- RL6
RJ45_MIDI1+ 3 1K_0402_5%
PR2+
RJ45_MIDI2+ 4
1
PR3+
RJ45_MIDI2- 5 ISOLATEB
TL1 PR3-
1
RJ45_MIDI1- 6
LAN_TERMAL 1 24 PR2- RL7
LAN_MIDI0+ 2 TCT1 MCT1 23 RJ45_MIDI0+ RJ45_MIDI3+ 7 9 15K_0402_5%
LAN_MIDI0- 3 TD1+ MX1+ 22 RJ45_MIDI0- PR4+ GND 10
TD1- MX1- RJ45_MIDI3- 8 GND
2
4 21 PR4-
LAN_MIDI1+ 5 TCT2 MCT2 20 RJ45_MIDI1+ SANTA_130452-W
LAN_MIDI1- 6 TD2+ MX2+ 19 RJ45_MIDI1- CONN@
TD2- MX2-
7 18 DC23400AX00 40m il
LAN_MIDI2+ 8 TCT3 MCT3 17 RJ45_MIDI2+ RJ45_GND 1 2 LANGND
LAN_MIDI2- 9 TD3+ MX3+ 16 RJ45_MIDI2- CL19
TD3- MX3- 10P_0402_50V8J
10 15
40m il
LAN_MIDI3+ 11 TCT4 MCT4 14 RJ45_MIDI3+ LANGND
TD4+ MX4+
1
LAN_MIDI3- 12 13 RJ45_MIDI3- @EMI@
TD4- MX4- JUMP_43X118
JPL1 JPL2
DL1 @EMI@
GST5009-E MESC5V02BD03_SOT23-3 B88069X9231T203_4P5X3P2-2
ESD@
SP050006B10
2
4 4
1
8
7
6
5
Place close to TCT pin H : 4mm

CL20 RPL1
1
0.1U_0402_16V7K 75_0804_8P4R_1%
2
1
2
3
4
RJ45_GND
LAN_RTL8111H
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A B C D E

A B C D E
Wireless LAN
1 1
+3VS_WLAN
+3VALW
+3VS
60mil +3VS_WLAN UM1 W=60m ils
1U_0402_6.3V6K
CM4
5 1
RM11 2 0_0805_5% IN OUT
1
1 1 1 2
NBYOC@ CM1 @ @
GND
CM2 CM3 4 3
4.7U_0603_6.3V6K 2 EN OC
.1U_0402_16V7K
2 2 2 SY6288C20AAC_SOT23-5
.1U_0402_16V7K BYOC@
<29> WLAN_ON
NGFF WL+BT (KEY E)
2
KEY E +3VS_WLAN
2
JNGFF1
1 2
USB20_P5 3 GND_1 3.3VAUX_2 4
<13> USB20_P5 USB20_N5 USB_D+ 3.3VAUX_4
5 6
For BT <13> USB20_N5
7 USB_D- LED1# 8
9 GND_7 PCM_CLK 10
11 SDIO_CLK PCM_SYNC 12
13 SDIO_CMD PCM_OUT 14
15 SDIO_DAT0 PCM_IN 16
17 SDIO_DAT1 LED2# 18
19 SDIO_DAT2 GND_18 20
21 SDIO_DAT3 UART_WAKE 22 UART_2_CRXD_DTXD
SDIO_WAKE UART_TX UART_2_CRXD_DTXD <12>
23
SDIO_RST
PH +3VS at SOC
UART_2_CTXD_DRXD side, for win7 USB3 debug
24
UART_RX UART_2_CTXD_DRXD <12>
25 26
PCIE_CTX_C_DRX_P6 27 GND_33 UART_RTS 28 RM3 1 2 100K_0402_5%
<13> PCIE_CTX_C_DRX_P6 PCIE_CTX_C_DRX_N6 PET_RX_P0 UART_CTS E51TXD_P80DATA_R
29 30 RM2 2 @ 1 0_0402_5%
<13> PCIE_CTX_C_DRX_N6 PET_RX_N0 CLink_RST E51RXD_P80CLK_R E51TXD_P80DATA <29>
31 32 RM7 2 @ 1 0_0402_5%
PCIE_CRX_DTX_P6 GND_39 CLink_DATA E51RXD_P80CLK <29>
33 34
<13> PCIE_CRX_DTX_P6 PCIE_CRX_DTX_N6 PER_TX_P0 CLink_CLK
<13> PCIE_CRX_DTX_N6
35 36
37 PER_TX_N0 COEX3 38
CLK_PCIE_P2 39 GND_45 COEX2 40
<11> CLK_PCIE_P2 CLK_PCIE_N2 REFCLK_P0 COEX1 SUSCLK_R
41 42 T205 @
<11> CLK_PCIE_N2 REFCLK_N0 SUSCLK(32KHz) WL_RST#_R
43 44 RM4 1 @ 2 0_0402_5%
CLKREQ_PCIE#2 GND_51 PERST0# BT_ON PLT_RST_BUF# <11,23>
<11> CLKREQ_PCIE#2
45 46
WLAN_PME# CLKREQ0# W_DISABLE2# WL_OFF# BT_ON <29>
47 48
<29> WLAN_PME# PEWAKE0# W_DISABLE1# WL_OFF# <29>
49 50
3 51 GND_57 I2C_DAT 52 3
RM6 53 RSVD/PCIE_RX_P1 I2C_CLK 54
+3VS_WLAN
2 1 10K_0402_5% 55 RSVD/PCIE_RX_N1 I2C_IRQ 56 P80CLK and BT_ON enable seperate.
57 GND_63 RSVD_64 58
59 RSVD/PCIE_TX_P1 RSVD_66 60
61 RSVD/PCIE_TX_N1 RSVD_68 62
63 GND_69 RSVD_70 64
65 RSVD_71 3.3VAUX_72 66
67 RSVD_73 3.3VAUX_74
GND_75 68
69 GND1
GND2
BELLW_80152-3221
CONN@
SP070013E00
4 4

M.2 Key E (WLAN)
A B C D E

A B C D E
HD Audio Codec +PVDD_HDA
+5VS (output = 300 mA) +VDDA

SM01000EJ00 3000mA 220ohm@100mhz DCR 0.04
40mil 40mil JPA1 40mil Int. Speaker Conn.
+VDDA
LA1 2 1 1 2 40mil SPK_R+
JSPK1
HCB2012KF-221T30_0805 1 1 1 SPKR+ EMI@ 1 LA2 2 PBY160808T-121Y-N_2P 1
1
SPK_R- 1
10U_0603_6.3V6M
CA1
.1U_0402_16V7K
CA2
.1U_0402_16V7K
CA3
.1U_0402_16V7K
CA4
JUMP_43X118 4.75V SPKR- EMI@ 1 LA3 2 PBY160808T-121Y-N_2P 2
SPKL+ 1 2 SPK_L+ 3 2
@ EMI@ LA4 PBY160808T-121Y-N_2P
SPKL- 1 2 SPK_L- 4 3
EMI@ LA5 PBY160808T-121Y-N_2P
2
2 2 +AVDD1_HDA 2 5 4
@
6 G1
@ESD@ EMI request for solve EMI noise, SM01000OW00.
GN D GN D
GND & GNDA moat G2
3
GN D ACES_50278-00401-001
Place near Pin41 Place near Pin46 GND CONN@
@ESD@ @ESD@
1
DA1 DA2 SP02000RR00 1
TVNST52302AB0_SOT523-3 TVNST52302AB0_SOT523-3
20m il
1
CA5 1 2 10U_0603_6.3V6M RA1 1 @ 2
GN D +VDDA
10U_0603_6.3V6M
CA9
1
1
.1U_0402_16V7K
CA8
Pin9 need to matching with SOC HDA CA6 1 2 .1U_0402_16V7K 0_0603_5% GND GND
inter fac e. +3VS_DVDDIO
RA2 2 @ 1 0_0402_5% Place near Pin9
+3VS
2
2 @
+3VS_DVDD GND & GNDA moat
Analog MIC(SMD)
20m il GNDA +MICBIAS2
RA5 2 @ 1 0_0402_5% Place near Pin26
+3VS
1 1
2
+1.8VS_VDDA
.1U_0402_16V7K
CA11
CA10 RA6 2 @ 1
+1.8VS
1 RA7
1
.1U_0402_16V7K
CA12
CA13
10U_0603_6.3V6M
10U_0603_6.3V6M 0_0402_5% 2.2K_0402_5%
2 2
15m il 15m il AMIC1
1
2 @ INT_MIC_R RA8 1 @ 2 INT_MIC_R_1 1
+
Place near Pin1 GN D GNDA
0_0603_5% 2
Place near Codec 1
CA14 -
41
46
26
40
1
9
UA1 Place near Pin40 @EMI@ GETTOP SOM4013SL-G423-RC-HS
220P_0402_50V7K @
DVDD-IO
PVDD1
PVDD2
DVDD
AVDD1
AVDD2
2
CY000002V00
22
Omnidirect i onal
LINE1-L
LINE1-R 21 LINE1-L(PORT-C-L) 43 SPKL-
INT_MIC_R INT_MIC CA32 1 LINE2_L LINE1-R(PORT-C-R) SPK-OUT-L- GNDA Follow EA52_BM(LA-B511P) footprint
UA1 2 1 2 42 SPKL+
RA9 1K_0402_5% 24 SPK-OUT-L+
4.7U_0603_6.3V6K
CA33 1 2 LINE2_R 23 LINE2-L(PORT-E-L) 45 SPKR+
LINE2-R(PORT-E-R) SPK-OUT-R+ 44
4.7U_0603_6.3V6K SPKR-
2
RING2 17 SPK-OUT-R- 2
40m il SLEEVE 18 MIC2-L(PORT-F-L)/RING2
MIC2-R(PORT-F-R)/SLEEVE 32 HP_LEFT
ALC233-VB2-CG_MQFN48_6X6 Combo M IC
+MICBIAS 31 HPOUT-L(PORT-I-L) 33 HP_RIGHT
233@ +MICBIAS
30 LINE1-VREFO-L HPOUT-R(PORT-I-R)
SA00007BF10 +MICBIAS2 +MICBIAS2
LINE1-VREFO-R 10 HDA_SYNC_R
SYNC HDA_BIT_CLK_R HDA_SYNC_R <10>
2 6
GPIO0/DMIC-DATA BCLK HDA_BIT_CLK_R <10>
3
GPIO1/DMIC-CLK 1 @EMI@ 2 1 2 CA15 @EMI@ GN D
RA10 0_0402_5% 22P_0402_50V8J
EC_MUTE# 47 5 HDA_SDOUT_R
<29> EC_MUTE# HDA_RST#_R PDB SDATA-OUT HDA_SDIN0_AUDIO HDA_SDOUT_R <10>
11 8 1 RA33 2
<10> HDA_RST#_R RESETB SDATA-IN HDA_SDIN0 <10>
33_0402_5%
48
MONO_IN 12 SPDIF-OUT/GPIO2
10m il PCBEEP 16
HP_PLUG# RA13
Close
2
codec1 200K_0402_1% SENSE_A 13 MONO-OUT
<28> HP_PLUG# SENSE A +MIC2_VREFO
RA14 2 1 100K_0402_1% 14
+3VS SENSE B
1 29 10U_0603_6.3V6M 2 1 CA18 GN D
37 MIC2-VREFO
CA19 35 CBP 7 10U_0603_6.3V6M 2 1 CA20
CBN LDO3-CAP GNDA
2.2U_0402_6.3V6M 39
2 LDO2-CAP 27 10U_0603_6.3V6M 2 1 CA21
LDO1-CAP GNDA
36
+3VS_DVDD CPVDD 1 RA15 2
28 CODEC_VREF 100K_0402_5% 10m il
Pin20 RA16 1 @ 2 0_0402_5% 20 VREF
ALC283 : NC +3VALW CPVREF 1 1
Headphone Out
.1U_0402_16V7K
CA23
2.2U_0402_6.3V6M
CA24
15
JDREF
ALC255/256/233 : Power for combo jack depop GNDA
10U_0603_6.3V6M 2 1 CA22 19
MIC-CAP CPVEE
34 CPVEE
circuit at system shutdown mode 2 2
1 @
4 +MIC2_VREFO
Pin4 49 DVSS 25 CA26
ALC283 : DVSS Thermal PAD AVSS1 38 2.2U_0402_6.3V6M
ALC255/256/233 : DC DET (For Japen customer only) AVSS2 2
3 3
Place near pin28
ALC255-CG_MQFN48_6X6
1
SA000082700 GN D
GN D 255@ RA19 RA20
GNDA 2.2K_0402_5% 2.2K_0402_5%
GNDA
2
RA21 CA27 SLEEVE SLEEVE <28>
DOS mode 22K_0402_5% .1U_0402_16V7K Pin15 RING2 RING2 <28>
2 1 BEEP#_R 1 2 MONO_IN
<29> BEEP# ALC283 : Ref. Resistor for Jack Detect
ALC255/256/233 : Jack Detect for SPDIF-OUT and SPK-OUT port
2
RA22
22K_0402_5% @
1 10/20 vendor review change to 0.1uF.
OS mode
100P_0402_50V8J
CA28
4.7K_0402_5%
RA23
2 1
<10> PCH_SPKR
2
1
HP_LEFT RA24 1 @ 2 0_0603_5% HPOUT_L_1

HPOUT_L_1 <28>
HP_RIGHT RA27 1 @ 2 0_0603_5% HPOUT_R_1
HPOUT_R_1 <28>
GN D
LINE1-L 1 2
CA29 4.7U_0603_6.3V6K
LINE1-R 1 2
CA30 4.7U_0603_6.3V6K
+MICBIAS DA5
2 2 RA29 1
GND & GNDA moat 4.7K_0402_5%
JPA2 JPA3 1
JUMP_43X39 JUMP_43X39
1 2 1 2 3 2 RA32 1
1 2 1 2
@ @ 4.7K_0402_5%
BAT54A-7-F_SOT23-3
4 JPA4 JPA5 4
JUMP_43X39 JUMP_43X39
1 2 1 2
@ 1
2
@ 1
2
CA31 @
.1U_0402_16V7K
1 2
RA25 1 @ 2 0_0402_5% Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2016/07/18 2016/11/10 Title
Deciphered Date
HD Audio Codec ALC255/ALC233 Colay
GN D GNDA GN D GNDA AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
Dat e: Monday, July 18, 2016 Sheet 25 of 44
A B C D E

A B C D E
SATA HDD Conn. SATA ODD Conn.
1 1
JODD1
JHDD1
1
1 CO5 1 2 0.01U_0402_16V7K SATA_CTX_C_DRX_P1 2 GND
SATA_CTX_DRX_P0 SATA_CTX_C_DRX_P0 GND <13> SATA_CTX_DRX_P1 SATA_CTX_C_DRX_N1 A+
<13> SATA_CTX_DRX_P0
CO1 1 2 0.01U_0402_16V7K 2 <13> SATA_CTX_DRX_N1
CO6 1 2 0.01U_0402_16V7K 3
SATA_CTX_DRX_N0 CO2 1 2 0.01U_0402_16V7K SATA_CTX_C_DRX_N0 3 A+ 4 A-
<13> SATA_CTX_DRX_N0 A- SATA_CRX_C_DTX_N1 GND
4 CO7 1 2 0.01U_0402_16V7K 5
SATA_CRX_DTX_N0 SATA_CRX_C_DTX_N0 GND <13> SATA_CRX_DTX_N1 SATA_CRX_C_DTX_P1 B-
CO3 1 2 0.01U_0402_16V7K 5 CO8 1 2 0.01U_0402_16V7K 6
<13> SATA_CRX_DTX_N0 SATA_CRX_DTX_P0 SATA_CRX_C_DTX_P0 B- <13> SATA_CRX_DTX_P1 B+
CO4 1 2 0.01U_0402_16V7K 6 7
<13> SATA_CRX_DTX_P0 B+ GND
7
GND +5VS RO2 +5VS_ODD
0_0805_5% 80mils 8
RO1 8 1 2 + 5VS_ODD 9 DP
+3VS V33 +5V
0_0402_5% 9 10
+3VS_HDD V33 ODD_MD +5V
10U_0603_6.3V6M
.1U_0402_16V7K
1 @ 2 10 NBYOC@ 1 1 T206 11
V33 MD
CO9
CO10
11 @ 12 14
12 GND 13 GND GND 15
13 GND GND GND
RO3 1 @ 2 0_0805_5% +5VS_HDD 14 GND 2 2
+5VS V5
15 SANTA_201501-2
16 V5 CONN@
17 V5
18 GND SP01001MV00
19 Reserved 23
20 GND GND 24
21 V12 GND 25
22 V12 GND 26
V12 GND
2 +3VS +5VS_HDD 2
SANTA_194403-1 +5VS
+5VS_ODD
100mils CONN@
UO1
5 1
LTCX0078W00 IN OUT
10U_0603_6.3V6M
CO12
.1U_0402_16V7K
CO13 @
1 1
1
2
CO11
GND
.1U_0402_16V7K ODD_EN 4 3 ODD_OC#
T207
2
2 2 <29> ODD_EN EN OC
@ @
SY6288C20AAC_SOT23-5
BYOC@
3 3
4 4

HDD/ODD/ HDD Re-Driver
A B C D E

5 4 3 2 1
D D
C C
SPACE
B B
A A
2016/07/18
Compal Secret Data
2016/11/10 Title
EMMC STORAGE
5 4 3 2 1

A B C D E
USB3.0 (Port 1) +5VALW

For ESD request +USB3_VCCA
CS23
DS21 ESD@ .1U_0402_16V7K US21
USB3_CTX_L_DRX_P1 1 USB3_CTX_L_DRX_P1
@RF@ 1 10 9 1 2 5 1 W=100mil s
CS21 1 2 USB3_CTX_C_DRX_N1 RS21 1 2 0_0402_5% USB3_CTX_L_DRX_N1 IN OUT
<13> USB3_CTX_DRX_N1 USB3_CTX_L_DRX_N1 2 2 USB3_CTX_L_DRX_N1
.1U_0402_16V7K 9 8 2
@RF@ GND
CS22 1 2 USB3_CTX_C_DRX_P1 RS22 1 2 0_0402_5% USB3_CTX_L_DRX_P1 USB3_CRX_L_DTX_P1 4 7 7 USB3_CRX_L_DTX_P1 USB_EN 4 3 RS23 1 @ 2 0_0402_5%
<13> USB3_CTX_DRX_P1 4 <29> USB_EN USB_OC0# <13>
1 EN OC 1
.1U_0402_16V7K
USB3_CRX_L_DTX_N1 5 6 USB3_CRX_L_DTX_N1 SY6288C20AAC_SOT23-5
5 6 1
3 3 CS24
.1U_0402_16V7K
8 2
@
L05ESDL5V0NA-4 SLP2510P8
+USB3_VCCA
USB3_CRX_DTX_N1
@RF@
USB3_CRX_L_DTX_N1
Max H:6mm
RS24 1 2 0_0402_5% W=100mil s
<13> USB3_CRX_DTX_N1 SF00000690 0
@RF@ 1 1
USB3_CRX_DTX_P1 USB3_CRX_L_DTX_P1
220U_C6_6.3V_M_R15
RS25 1 2 0_0402_5%
<13> USB3_CRX_DTX_P1 +
CS25 CS26
470P_0402_50V7K
2 @
2
DS22 ESD@
U2DP1_L
USB3.0 Conn.
6 3
I/O4 I/O2 JUSB1
+USB3_VCCA 1
U2DN1_L 2 VBUS
LS23 5 2 U2DP1_L 3 D-
USB20_P1 2 1 U2DP1_L VDD GND 4 D+
<13> USB20_P1 USB3_CRX_L_DTX_N1 5 GND
USB3_CRX_L_DTX_P1 6 StdA-SSRX- 10
USB20_N1 3 4 U2DN1_L 4 1 U2DN1_L 7 StdA-SSRX+ GND 11
<13> USB20_N1 I/O3 I/O1 USB3_CTX_L_DRX_N1 GND-DRAIN GND
8 12
USB3_CTX_L_DRX_P1 9 StdA-SSTX- GND 13
MCM1012B900F06BP_4P AZC099-04S.R7G_SOT23-6
EMI@ StdA-SSTX+ GND
2 LOTES_AUSB0015-P001A 2
CONN@
DC23300AI00
USB2.0 (Port 2)
3 Need check pin def i ni t i o

n 3
+USB3_VCCA
2 1 USB20_P2_L
<13> USB20_P2
3 4 USB20_N2_L
W=100mil s IO/B (USB, AUDIO, CR)
<13> USB20_N2 1
MCM1012B900F06BP_4P CS27 JUSB3
LS24 470P_0402_50V7K HPOUT_L_1 1
EMI@ <25> HPOUT_L_1 1
2 @ HPOUT_R_1 2
<25> HPOUT_R_1 2
SLEEVE 3
USB2.0 Conn <25> SLEEVE
<25> RING2
RING2
HP_PLUG#
4
5
3
4
JUSB2 <25> HP_PLUG# 5
DS23 ESD@ 6
USB20_P2_L GNDA 6
6 3 1 5 7
I/O4 I/O2 USB20_N2_L 2 VBUS G1 6 8 7
+USB3_VCCA USB20_P2_L D- G2 +3VS 8
3 7 9
4 D+ G3 8 10 9
5 2 GND G4 USB20_N8 11 10
VDD GND <13> USB20_N8 USB20_P8 12 11
ACON_UARC9-4K1986
<13> USB20_P8 13 12
CONN@
USB20_P3 14 13
4 1 USB20_N2_L DC23300AH00 <13> USB20_P3 USB20_N3 15 14
I/O3 I/O1 <13> USB20_N3 15
16
USB_EN 17 16
AZC099-04S.R7G_SOT23-6
18 17
19 18
20 19
+5VALW 20
21
22 G1
G2
4 4
ACES_85201-2005N
CONN@
SP010011U00

USB Conn/IO_B
A B C D E

A B C D E
+3VLP_EC PN:SM 01000K500 +3VLP_ECA

+3VLP @ RB22 LB1
0_0805_5% FBMA-L11-160808-800LMT_0603
CB9 1 2 1000P_0402_50V7K EC_RST# 1 2 1 2 +3VLP_ECA
.1U_0402_16V7K
.1U_0402_16V7K
+3VALW_1.8VALW_PGPPA
1 1 1
CB1
CB2
0_0402_5%
CB3
RB2
.1U_0402_16V7K
+3VLP_EC 2 2 RB3 @ 2
0_0402_5%
ECAGND
@
2
EC_PME# ECAGND <34>
1 @ 2
2
1 RB5 47K_0402_5% +3VCC_LPC 1
EC_PME# PU +3V_LAN at LAN side
125
111
22
33
96
67
9
+3VLP_EC UB1
VCC
VCC
VCC
VCC
VCC0
VCC_LPC
AVCC
RB13 1 2 2.2K_0402_5% EC_SMB_CK1
RB14 1 2 2.2K_0402_5% EC_SMB_DA1
ESPI Bus Pin : 1~5.7.8.10.12.14
LPC Bus Pin : 3~5.7.8.10.12.13 SUSPWRDNACK 1 21 EC_VCCST_PG_R
<11> SUSPWRDNACK EC_KBRST# 2 GATEA20/GPIO00 EC_VCCST_PG/GPIO0F 23 BEEP# EC_VCCST_PG_R <11,32>
TPM_SERIRQ 3 KBRST#/GPIO01 BEEP#/GPIO10 26 FAN_PWM1 BEEP# <25>
<9> TPM_SERIRQ LPC_FRAME# 4 SERIRQ EC_FAN_PWM/GPIO12 27 I2C_TS_RST# FAN_PWM1 <31>
<9> LPC_FRAME# LPC_AD3_R LPC_FRAME# PW M Output AC_OFF/GPIO13 I2C_TS_RST# <21>
For turn off internal LPC module of KB9032 5
<9> LPC_AD3_R LPC_AD2_R LPC_AD3
7
<9> LPC_AD2_R LPC_AD1_R LPC_AD2 BATT_TEMP
ESPI@ 8 63
1 2 ESPI_RST# <9> LPC_AD1_R LPC_AD0_R 10 LPC_AD1 VCIN1_BATT_TEMP/AD0/GPIO38 64 VCIN1_BATT_DROP BATT_TEMP <34> +3VLP_EC
<9> LPC_AD0_R LPC_AD0LPC & MISC VCIN1_BATT_DROP/AD1/GPIO39 ADP_I VCIN1_BATT_DROP <34>
RB8 47K_0402_5% 65
CLK_LPC_EC 12 ADP_I/AD2/GPIO3A 66 AD_BID ADP_I <34,35>
<9> CLK_LPC_EC PLT_RST# CLK_PCI_EC AD Input AD_BID/AD3/GPIO3B WLAN_PME# LID_SW#
ESPI@ 13 75 RB15 1 2 100K_0402_1%
1 2 PLT_RST# <11> PLT_RST# EC_RST# 37 PCIRST#/GPIO05 AD4/GPIO42 76 EC_PME# WLAN_PME# <24>
<31> EC_RST# EC_SCI# 20 EC_RST# AD5/GPIO43 EC_PME# <23>
RB9 47K_0402_5% Combine w/ SMI
<7> EC_SCI# WLAN_ON 38 EC_SCI#/GPIO0E
<24> WLAN_ON CLKRUN#/GPIO1D I2C_TS_RST# RB6
1 2 2 1 100K_0402_5%
CB5 @ESD@ 100P_0402_50V8J 68 LAN_PWR_EN
<30> KSI[0..7] DA0/GPIO3C 70 LAN_PWR_EN <23>
DA Output EN_DFAN1/DA1/GPIO3D
KSI0 55 71
KSI1 56 KSI0/GPIO30 DA2/GPIO3E 72
1 2 AC_IN KSI2 57 KSI1/GPIO31 DA3/GPIO3F
KSI3 58 KSI2/GPIO32 83 EC_MUTE#
CB6 100P_0402_50V8J
59 KSI3/GPIO33 EC_MUTE#/PSCLK1/GPIO4A 84 USB_EN EC_MUTE# <25>
KSI4
KSI5 60 KSI4/GPIO34 USB_EN#/PSDAT1/GPIO4B 85 USB_EN <28>
@EMI@ @EMI@ T85 @
2 2 1 2 1 CLK_LPC_EC KSI6 61 KSI5/GPIO35 PSCLK2/GPIO4C 86 PM_SLP_S0# 2
KSI6/GPIO36 PS2 Interface PSDAT2/GPIO4D TP_CLK PM_SLP_S0# <11> SYS_PWROK_R
CB7 RB10 33_0402_5% KSI7 62 87 1 @ 2 SYS_PWROK <11,32>
<30> KSO[0..17] KSO0 39 KSI7/GPIO37 TP_CLK/GPIO4E 88 TP_DATA TP_CLK <30>
22P_0402_50V8J RB11 0_0402_5%
40 KSO0/GPIO20 TP_DATA/GPIO4F TP_DATA <30> PU at PTP side
KSO1
KSO2 41 KSO1/GPIO21
KSO3 42 KSO2/GPIO22 97 ENBKL
KSO3/GPIO23 ENKBL/GPXIOA00 TP_PWR_EN ENBKL <7>
KSO4 43 98
KSO4/GPIO24 WOL_EN/GPXIOA01 ME_EN TP_PWR_EN <30>
KSO5 44 99
KSO6 45 KSO5/GPIO25 Int. K/B ME_EN/GPXIOA02 109 VCIN0_PH ME_EN <10>
KSO7 46 KSO6/GPIO26 Matrix VCIN0_PH1/GPXIOD00 VCIN0_PH <34>
DB1
For Thermal Portect Shutdown
RB12 KSO8 47 KSO7/GPIO27 RB751V-40_SOD323-2
KSO8/GPIO28 SPI Device Interface 3V_EN
0_0402_5% KSO9 48 119 MAINPWON 1 2
1 2 EC_KBRST# 49 KSO9/GPIO29 MISO/GPIO5B 120 BT_ON 3V_EN <36>
@ KSO10
<9> EC_KBRST#_R KSO10/GPIO2A MOSI/GPIO5C BT_ON <24>
KSO11 50 SPI Flash ROM SPICLK/GPIO58 126
KSO12 51 KSO11/GPIO2B 128 3V_EN_R 1 2 RB17 1 2
KSO13 52 KSO12/GPIO2C SPICS#/GPIO5A RB16 1M_0402_5%
KSO14 53 KSO13/GPIO2D 1K_0402_5%
KSO15 54 KSO14/GPIO2E 73
KSO16 81 KSO15/GPIO2F EC_CIR_RX/AD6/GPIO40 74 SYS_PWROK_R
KSO17 82 KSO16/GPIO48 SYS_PWROK/AD7/GPIO41 89 BATT_4S
KSO17/GPIO49 GPIO50 90 BATT_BLUE_LED# BATT_4S <35>
BATT_CHG_LED#/GPIO52 ODD_EN BATT_BLUE_LED# <30>
91
EC_SMB_CK1 CAPS_LED#/GPIO53 PWR_LED#_R ODD_EN <26>
77 GPIO 92
<34,35> EC_SMB_CK1 EC_SMB_DA1 78 EC_SMB_CLK1/GPIO44 PWR_LED#/GPIO54 93 BATT_AMB_LED# PWR_LED#_R <30>
<34,35> EC_SMB_DA1 SOC_SML1CLK 79 EC_SMB_DAT1/GPIO45 BATT_LOW_LED#/GPIO55 95 SYSON BATT_AMB_LED# <30>
<9> SOC_SML1CLK SOC_SML1DATA 80 EC_SMB_CLK2/GPIO46 SYSON/GPIO56 121 EC_TP_INT# SYSON <14,32,37>
PU at CPU side <9> SOC_SML1DATA EC_SMB_DAT2/GPIO47 VR_ON/GPIO57 127
EC_TP_INT# <7,30>
DPWROK_EC/GPIO59
SM Bus
PM_SLP_S3# 6 100 EC_RSMRST#
<11,32> PM_SLP_S3# ESPI_RST# 14 PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXIOA03 101 EC_RSMRST# <11>
<9> ESPI_RST# 15 GPIO07 GPXIOA04 102 VCIN1_ADP_PROCHOT
SPOK
3 <36,39> SPOK TP_EN 16 GPIO08 VCIN1_ADP_PROCHOT/GPXIOA05 103 VCOUT1_PROCHOT# VCIN1_ADP_PROCHOT <34> 3
<30> TP_EN TS_EN 17 GPIO0A VCOUT1_PROCHOT#/GPXIOA06 104 MAINPWON
<12,21> TS_EN WL_OFF# 18 GPIO0B VCOUT0_MAIN_PWR_ON/GPXIOA07 105 MAINPWON <31,34,36>
BKOFF#
<24> WL_OFF# AC_PRESENT 19 GPIO0C BKOFF#/GPXIOA08 106 LAN_GPO BKOFF# <21>
<11> AC_PRESENT AC_PRESENT/GPIO0D GPIO GP O GPXIOA09 3V_EN_R LAN_GPO <23>
25 107
For abnormal shutdown FAN_SPEED1 28 PWM2/GPIO11 PCH_PWR_EN/GPXIOA10 108
<31> FAN_SPEED1 VR_ON 29 FAN_SPEED1/GPIO14 PWR_VCCST_PG/GPXIOA11
<32,40> VR_ON E51TXD_P80DATA 30 FANFB1/GPIO15
DB2
<24> E51TXD_P80DATA E51RXD_P80CLK 31 EC_TX/GPIO16 110 AC_IN
RB751V-40_SOD323-2
EC_RSMRST# <24> E51RXD_P80CLK PCH_PWROK EC_RX/GPIO17 VCIN1_AC_IN/GPXIOD01 EC_ON AC_IN <35>
SPOK 1 2 32 112
<11,32> PCH_PWROK PWR_SUSP_LED# 34 PCH_PWROK/GPIO18 EC_ON/GPXIOD02 114 EC_ON <36>
ON/OFFBTN#
<30> PWR_SUSP_LED# VR_PWRGD SUSP_LED#/GPIO19 ON/OFF#/GPXIOD03 LID_SW# ON/OFFBTN# <30>
DB3 36 GPI 115
<40> VR_PWRGD NUM_LED#/GPIO1A LID_SW#/GPXIOD04 116 LID_SW# <30>
RB751V-40_SOD323-2 SUSP#
1 2 PCH_PWROK SUSP#/GPXIOD05 117 SUSP# <14,32,35,37>
GPXIOD06 118 H_PECI_R 1 2
PBTN_OUT# PECI/GPXIOD07 H_PECI <7>
122 RB19 43_0402_1%
<11> PBTN_OUT# PM_SLP_S4# 123 PBTN_OUT#/GPIO5D 124
DB4
<11,32> PM_SLP_S4# PM_SLP_S4#/GPIO5E V18R/VCC_IO2 +3VLP_EC
RB751V-40_SOD323-2
AGND
1 2 EC_VCCST_PG_R
GND
GND
GND
GND
GND
KB9022QD_LQFP128_14X14
24
35
94
ECAGND 69
11
113
Board ID 20m il
+3VLP_EC
CO-LAY with KB9032QA (SA000080J00) 2 BATT_TEMP
CB8 1
100P_0402_50V8J
LB2 2 1
2
FBMA-L11-160808-800LMT_0603
RB1 PN:SM 01000K500
Ra 100K_0402_1%
1
4 AD_BID RB20 1 @ 2 0_0402_5% VR_HOT# 4

VR_HOT# <40>
1
1 H_PROCHOT#
RB4 RB21 1 @ 2 0_0402_5% VCOUT1_PROCHOT#
<7> H_PROCHOT#
Rb 15K_0402_1% CB4
.1U_0402_16V7K
2
@
2

Analog Board ID definition, EC ENE KB9022
Please see page 3. THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
A B C D E

A B C D E
KB Conn. JKB1
ON/OFF BTN
RK1
30
29
28
GND2
GND1
TP/B Conn.
100K_0402_5% ON/OFFBTN# 27 28
2 1 KSO0 26 27 +3V_PTP
+3VLP 26 +3VS +3VALW
KSO1 25 +3VALW +3V_PTP
KSO2 24 25
ON/OFFBTN# KSO3 23 24 2 @ 1
<29> ON/OFFBTN# 23
KSO4 22 0_0402_5% RK2
KSO5 21 22 UK1 2 @ 1
21
4.7U_0603_6.3V6K
KSO6 20 5 1 +3V_PTP 0_0402_5% RK3
@ SWK1 KSO7 19 20 IN OUT @ CK2
19 1
CK1
1 EVQPLDA15_4P KSO8 18 2 .1U_0402_16V7K 1
Test Only
2
1 3 KSO9 17 18 GND 2 1 JTP1
KSO10 16 17 4 3 1
BOT 2 4 15 16 EN OC 2 TP_CLK 2 1
KSO11 2 RK4
KSO12 14 15 SY6288C20AAC_SOT23-5 10K_0402_5% TP_DATA 3 2
KSO13 13 14 CK3
EC PS2 4 3
6
5
1
KSO14 12 13 1U_0402_6.3V6K EC_TP_INT# I2C_1_SDA_R 5 4
KSO15 11 12 1 I2C_1_SCL_R 6 5
KSO16 10 11 TP_PWR_EN <29> PCH I2C EC_TP_INT# 7 6
10 <7,29> EC_TP_INT# TP_EN 7
KSO17 9 8
9 <29> TP_EN 8
KSI0 8 9
KSI1 7 8 TP_PWR_EN follow SYSON behavior 10 GND
KSI2 6 7 GND
KSI3 5 6 ACES_51524-00801-001
KSI4 4 5
CONN@
KSI5 3 4
KSI[0..7] KSI6 2 3 SP01001A910
KSI[0..7] <29> 1 2 +3V_PTP +3V_PTP
KSI7
KSO[0..17] 1 +3V_PTP
KSO[0..17] <29>
ACES_85201-2805
CONN@
1
RK7 RK10
SP01000GO00
1
2.2K_0402_5% 2.2K_0402_5%
G
QK1B RK5 RK6
2N7002KDW_SOT363-6 4.7K_0402_5% 4.7K_0402_5%
2
3 4 I2C_1_SCL_R
2
<12> I2C_1_SCL
D
1 2 TP_CLK
<29> TP_CLK TP_DATA
RK8 @ 0_0402_5%
<29> TP_DATA
2
G
2 2
QK1A
2N7002KDW_SOT363-6
6 1 I2C_1_SDA_R
S
<12> I2C_1_SDA
D
1 @ 2
RK9 0_0402_5%
Lid Switch
(Hall Effect Switch)
Follow 2015
+3VLP
UG1
3 LID_SW#
OUT LID_SW# <29>
2
VDD 1
GND
1
APX8132AI_TSOT-23-3
CG2
.1U_0402_16V7K
3 2 3
SA00008K800, S IC APX8132AI-TRG SOT-23 3P HALL SENSOR
Bat t er y L E D
LED1
RG4
1.24K_0402_1%
BATT_AMB_LED# 1 2 3 A 4
<29> BATT_AMB_LED# +5VALW
BATT_BLUE_LED# 1 2 1 B 2
<29> BATT_BLUE_LED#
RG6
820_0402_5%
@ RG8 LTST-C295TBKF-CA_AMBER-BLUE
0_0402_5%
1 2 PWR_LED#
Follow Z5W1M LED.
Power LED
1
D
QG2
2 L2N7002LT1G_SOT23-3
<29> PWR_LED#_R LED2
G @ RG11
1
S 1.24K_0402_1%
3
RG9 PWR_SUSP_LED# 1 2 3 A 4
<29> PWR_SUSP_LED#
100K_0402_5% @
avoid flash issue when PWR_LED# 1 2 1 B 2

+5VALW
2
abnormall shutdown
4 RG10 4
820_0402_5%
LTST-C295TBKF-CA_AMBER-BLUE

KB & TP & TPM & LID SW & LED
A B C D E

A B C D E
FAN1 Conn Screw Hole

+5VS
40m il
RF1 1 @ 2 0_0603_5% +VCC_FAN1
1
1 2 1
H3 H4 H5 H6 H9 H10 H11 FD1 FD2
@EMI@ CF2 CF1 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0
1000P_0402_50V7K 4.7U_0603_6.3V6K
2 1 @ @
1
1
1
FIDUCIAL_C40M80 FIDUCIAL_C40M80
FD3 FD4
@ @ @ @ @ @ @
H13 H14 H15 @ @
1
H_3P6 H_3P6 H_3P6
+3VS FIDUCIAL_C40M80 FIDUCIAL_C40M80
1
1
RF2
10K_0402_5%
@ @ @
40m il
JFAN1
2
+VCC_FAN1 1
FAN_SPEED1 2 1
<29> FAN_SPEED1 FAN_PWM1 3 2
<29> FAN_PWM1 3
1 4
CF3 5 4 H23 H25 H12
1000P_0402_50V7K 6 G1 H_3P3X3P0N H_3P0N H_2P8X2P5N
@EMI@ G2
2 ACES_50278-00401-001
CONN@ @ @ @
1
SP02000RR00
2 2
Reset Circuit
+3VLP
RG1 1 @ 2 0_0402_5%
MAINPWON <29,34,36>
2
RG3 RG2 1 @ 2 0_0402_5%
EC_RST# <29>
10K_0402_5%
6
D
BI_GATE# 2
G 2N7002KDW_SOT363-6
BI_GATE PH to +RTCVCC at PWR side QG1A
3
D S
1
1
BI_GATE 5
3 <34> BI_GATE G C70 3
QG1B .1U_0402_16V7K
2N7002KDW_SOT363-6 S 2
4
BI SW
Reset But t on
3 SWG1 1
SWG2
1 2 BI_GATE BI_S <34>

4 2
SKPMAME010_2P ATE-2-V-TR_4P
H : 3.8mm
Release : Bat t er y Off

Push : Bat t er y ON
4 4

FAN & Screw Hole & Reset
A B C D E

A B C D E
DC Interface For Power ON/Off Sequence PM_SLP_S3

+3VALW
2
+5VS +3VS
G
1
Q1A
.1U_0402_16V7K
.1U_0402_16V7K
UQ1 R24 2N7002KDW_SOT363-6
1 14 @ JPQ2 1 1 100K_0402_5%
+5VALW VIN1 VOUT1 +5VS_OUT1
2 13 2 1 6
S
VIN1 VOUT1 1 2 +5VS EC_VCCST_PG_R <11,29>
CQ5
CQ6
D
2
RQ2 2 @ 1 0_0402_5% 5VS_ON 3 12 1 2 JUMP_43X118 MOW14, For tCPU28 200us(max)
ON1 CT1 CQ1 1000P_0402_50V7K 2 2 SLP_S3# to VCCST_PWRGD deassertion
5
1 2 @ CQ4 4 11
G
1
+5VALW VBIAS GND 1
.1U_0402_16V7K
SUSP# 1 @ 2 3VS_ON 5 10 1 2 1000P_0402_50V7K Q1B
RQ1 0_0402_5% ON2 CT2 CQ3 @ JPQ1 Q2A 2N7002KDW_SOT363-6
6 9 +3VS_OUT1 2 2N7002KDW_SOT363-6 4 3
S
+3VALW VIN2 VOUT2 1 2 +3VS VR_ON <29,40>
D
1 2 @ CQ2 7 8 D
.1U_0402_16V7K VIN2 VOUT2 JUMP_43X118 2
<11,29> PM_SLP_S3# MOW14, For tPLT17 200us(max)
15 G SLP_S3# to IMVP VR_ON deassertion
GPAD
5
G
EM5209VF_DFN14_2X3 S
1
Q2B
2N7002KDW_SOT363-6
4 3 SUSP#
D
MOW14, For tPLT18 200us(max)
SLP_S3# to VCCIO VR disable
2
G
Q3A @
+5VALW +0.6VS_VTT +1.2V_VDDQ +5VALW 2N7002KDW_SOT363-6
+2.5V 1 6
S
SYS_PWROK <11,29>
2
D
2
R25 R26 R27 R28
2
100K_0402_5% @ @ 470_0603_5% 470_0603_5% 100K_0402_5%
5
R31 @ @
G
470_0603_5% +3VALW Q3B @
1
1
+0.6VS_VTT_R
SUSP @ 2N7002KDW_SOT363-6
1
1
1
Q4A @ Q4B @ +1.2V_VDDQ_R SYSON# 4 3
S
PCH_PWROK <11,29>
D
2N7002KDW_SOT363-6 2N7002KDW_SOT363-6 R29
6
D D Q5A @ Q5B @ 100K_0402_5%
1
D
2 5 SUSP 2N7002KDW_SOT363-6 2N7002KDW_SOT363-6
<14,29,35,37> SUSP#
3
G G SYSON_2V5# 2 D D
2
2 <37> SYSON_2V5# SYSON# 2 5 SYSON PM_SLP_S4 2
G Q6A
SYSON <14,29,37>
1
S S @ Q7 S G G 2N7002KDW_SOT363-6
1
5
R30 L2N7002WT1G_SC-70-3 D
G
10K_0402_5% S S 2 Q6B
4
<11,29> PM_SLP_S4# G
@ 2N7002KDW_SOT363-6
2
S 4 3 SYSON
S
1
D
MOW14, For tPLT15 200us(max)
SLP_S4# to VDDQ ramp down
3 3
4 4

DC Interface
A B C D E

A B C D E
schematic from A4WAS
1 1
+19V_ADPIN HCB2012KF-121T50_0805
EMI@ PL101 +19V_VIN
1 2
@ PJP101
ACES_50305-00441-001_4P
1
1
1 EMI@ EMI@ PC104
2 PC102 1000P_0603_50V7K
2
3 100P_0603_50V8
2
4
GND
GND
2 2
@ PR101
0_0402_5%
1 2
+3VLP +CHGRTC
- PBJ101 @ + PR102
560_0603_5%
PR103
560_0603_5%
2 1 1 2 1 2
+RTCBATT
ML1220T13RE
3 3
4 4

PWR DCIN / Pre-charge
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. B5W1S M/B LA-D671P
A B C D E

A B C D E
2013/07/23
change PC5 and PC6 function field from 37.1 to 47.1
+3VLP
1 1
1
@ PC205
1
PR207 100_0402_1% 0.1U_0603_25V7K
MB:Battery Con Put TOP Side
2
1 2
EC_SMB_DA1 <29,35>
PR205 100_0402_1% @ PR215 @ PR214
1 2 10K_0402_1%
EC_SMB_CK1 <29,35> <45,47> 10K_0402_1%
2
1
@ PU201
Battery Bot Side PR202 @ PR213 1 8
200K_0402_1% 100K_0402_1% VCC TMSNS1
1 2 2 7 2 1
PIN1 GND @ PJP201 +3VLP GND RHYST1
2
PIN2 GND 1
<29,31,36> MAINPWON
MAINPWON 3 6 @ PR216
1
1 2 OT1 TMSNS2
PH203 @
1 2
100K_0402_1%_NCP15WF104F03RC
47K_0402_1%
PIN3 SMD 2 3 EC_SMB_DA1-1 BATT_TEMP <29> 4 5
3 4 EC_SMB_CK1-1 PR203 1K_0402_1% OT2 RHYST2 @ PH202
PIN4 SMC 4 5 BATT_TS G718TM1U_SOT23-8 100K_0402_1%_NCP15WF104F03RC
5 6 BATT_B/I
PIN5 TEMP close to RTC
2
6 7
PIN6 BI 7 8
8 9 +RT CVCC
PIN7 Batt+ GND 10
PIN8 Batt+ GND
CVILU_CI9908M2HR0-NH
1
PR212
100K_0402_5%
PQ201 Change to SB00000QO00,
SB501380010(BSS138LT1G Del)
1
2 D 2
2 PQ201
<31> BI_GATE G BSS138LT1G_SOT23-3
S
3
+17.4V_BATT+ 2014/09/25 update
EMI@ PL201 BI_S <31>
2
HCB2012KF-121T50_0805 For KB9022
change PL201, PL202 1 2
+17.4V_BATT
@ PR217
sense 20mΩ
Active Recovery
0_0402_1%
SM01000C000 to comm EMI@ PL202
45W PR206
HCB2012KF-121T50_0805
part SM01000P200
1
1 2
10K ohm 58.5W,0.61V 45W,0.47V
SD034100280
1
EMI@ PC201 EMI@ PC202 PH1 2V 1V

1000P_0402_50V7K 0.01U_0402_25V7K PH1 under CPU botten side :
2
CPU thermal protection at 89 +-3 degree C

Recovery at 56 +-3 degree C
2013/06/07
Add for ENE9022 Battery Voltage drop detection.
Connect to ENE9022 pin64 AD1.
3 +3VLP_ECA 3
ADP_I <29,35>
+19VB_5V
VAL50/ZAL20 Battery is 3-cell NVDC design.
1
B+=9V PR204
Change PR12=50k if Battery is 2-cell NVDC design 16.9K_0402_1%
B+=6V
1
2
@ PR209
80.6K_0402_1%
VCIN0_PH <29> 45W@
PR206
@ PR210 10K_0402_1%
2
0_0402_5%
1
1
1 2
VCIN1_BATT_DROP <29> PC203 must close to EC pin
2
PH201
@PC203 VCIN1_ADP_PROCHOT <29>
100K_0402_1%_NCP15WF104F03RC 0.1U_0402_25V6
1
1
1
2
2
@ PC204 @ PR211 PR208

0.1U_0402_25V6 10K_0402_1% T202 T201 must close to PH201
T202@ 10K_0402_1%
1
2
T201@
4
<29> ECAGND 4

PWR-BATTERY CONN/OTP
A B C D E

A B C D
Protection for reverse input

schematic from module
Need check the SOA for inrush
Vgs = 20V
1
PQ301 D
2
Vds = 60V +19VB
G Id = 250mA
S 2N7002KW_SOT323-3
3
PR302
PR301
1 2 1 2
1M_0402_5% 3M_0402_5%
1
@ PJ301 1
JUMP_43X79
PQ302 1 2
+19V_VIN MDU1512RH_POWERDFN56-8-5 PQ303 1 2
+19V_P1 AON7506_DFN33-8-5 +19V_P2 PQ304
1 1 PR303 EMI@ PL301 +19VB_CHG AON7506_DFN33-8-5
2 2 0.02_1206_1% 1UH +-30% 2.8A 1
5 3 3 5 1 4 1 2 2
Isat: 4A 5 3
2200P_0402_25V7K
10U_0805_25V6K
10U_0805_25V6K
2 3
2200P_0402_50V7K
0.1U_0402_25V6
DCR: 27mohm
0.1U_0402_25V6
4
@EMI@PC306
1
1
PC303
PC304
EMI@ PC305
0_0402_5%
0.01U_0402_50V7K
PC301
@ PR304
4
1
1
+19V_VIN
PC302
PC307
2
2
2
2
VF = 0.5V
2
2
3
2
PD301
BQ24725A_ACDRV_1
BAS40CW_SOT323-3
0.1U_0402_25V6
BQ24725A_BATDRV 1 2BQ24725A_BATDRV_1
0.1U_0402_25V6
Rds(on) = 30mohm max
1
1
PC308
PC310
PR305
Vgs = 20V
1 1
1 2
10_1206_1%
PC311 4.12K_0603_1%
0.047U_0402_25V7K Vds = 30V
PR306
2
PC309 1 2 ID = 7A (Ta=70C)
0.1U_0402_25V6 VF = 0.37V PQ305
5
AON7506_DFN33-8-5
2.2_0603_5%
PR307
PD302
BQ24725A_VCC2
RB751V-40_SOD323-2 Support max charge 3.5A
@ PR308
BQ24725A_ACP
0_0603_5%
Power loss: 0.245W
BQ24725A_REGN
BQ24725A_BST 2
2
DH_CHG 1 2 4 CSR rating: 1W
BQ24725A_LX
5*5*3 VSRP-VSRN spec < 81.28mV
4.12K_0603_1%
4.12K_0603_1%
2 2
1
PC312 +17.4V_BATT
PR309
PR310
DH_CHG
1 2 PL302
3.3UH_PCMB053T-3R3MS_5A_20% PR311
3
2
1
1 2
BQ24725A_ACN
1U_0603_25V6K 0.01_1206_1%
BQ24725A_LX 1 2 CHG1 4
2
PC313
5
1U_0603_25V6K 2 3
20
19
18
17
16
PQ306
PU301
AON7506_DFN33-8-5
CSON1
1
CSOP1
4.7_1206_5%
VCC
BTST
REGN
PHASE
HIDRV
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
PR312
@EMI@
21
PAD
0.1U_0402_25V6
0.1U_0402_25V6
PC314
PC315
PC324
1
1
1 15 DL_CHG 4
ACN LODRV
PC316
PC317
2
2
2 14
680P_0402_50V7K
ACP GND
PR313
3
2
1
2
1
@EMI@
BQ24735RGRR_QFN20_3P5X3P5 10_0603_1%
PC318
BQ24725A_CMSRC 3 13 SRP1 2 CSOP1
1
CMSRC SRP PR314
2
6.8_0603_1%
BQ24725A_ACDRV 4 12 SRN1 2 CSON1
2
ACDRV SRN
PC319
0.1U_0603_16V7K
1 2 5 11 BQ24725A_BATDRV
+3VLP ACOK BATDRV
PR315 100K_0402_1%
ACDET
IOUT
SDA
SCL
ILIM
+3VLP
<29> AC_IN
10
6
9
3 3
BQ24725A_ILIM
BQ24725A_ACDET
1 2
For 4S per cell 4.35V battery
BQ24725A_IOUT
PR324
100K_0402_1%
316K_0402_1%
0.01U_0402_25V7K
1
PC320
PR317
1
BQ24725A_ACDET PR318
422K_0402_1%
1 2
2
+19V_VIN
2
1
PR321
2M_0402_1%
2
1
2200P_0402_50V7K
66.5K_0402_1%
PR322 @
EC_SMB_CK1 <29,34>
0_0402_5%
100P_0402_50V8J
1
1
PC321
1
PC322
PR319
1 2
EC_SMB_DA1 <29,34>
2
PQ307 PR320
2
PR323 LTC015EUBFS8TL_UMT3F 0_0402_5%

100K_0402_1% 1 2
ADP_I <29,34>
1 2 2
<29> BATT_4S
1
PC323 @
100P_0402_50V8J
3
2
1
PQ308 D
4
2 Close EC chip 4
<14,29,32,37> SUSP# G Vin Dectector

S 2N7002KW_SOT323-3
Min. Typ Max.
3
L-->H 17.16V 17.63V 18.12V

H-->L 16.76V 17.22V 17.70V
VILIM = 20*ILIM*Rsr Issued Date 2015/10/02 Deciphered Date 2014/05/24 Title
ILIM = 3.3*100/(100+316)/20/0.01 CHARGER
= 3.966 A THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Common Circuit 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Dat e: Monday, July 18, 2016 Sheet 35 of 44
A B C D
A B C D E
PR402
499K_0402_1%
ENLDO_3V5V 1 2
+19VB
1
150K_0402_1%
PR404
EN1 and EN2 dont't floating
@ PJ403
JUMP_43X79
1 2
2
1 2
PU401
1 EMI@ PL401 SY8286BRAC_QFN20_3X3 @ PR401 1
+19VB HCB2012KF-121T50_0805 0_0603_5% PC401
+19VB_3V BST_3V
2200P_0402_50V7K
1 2 1 2 1 2
@EMI@ PC403
EMI@ PC404
10U_0805_25V6K
0.1U_0402_25V6
0.1U_0603_25V7K
1
5*5*3 Common part SH000016800
PC405
BS
IN
IN
IN
IN
PL402
2
LX_3V6 20 LX_3V 1 2
LX LX +3V ALWP
7 19 1.5UH_PCMB053T-1R5MS_6A_20%
GND LX
@EMI@
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
PR405
1
1
680P_0603_50V7K 4.7_1206_5%
8 18
+3V ALWP GND GND
PC407
PC408
PC409
PC410
9 17
+3VLP
2
PG LDO
1 3V_SN
10 16
2
NC NC
1
Check pull up resistor of SPOK at HW side PC411
OUT
EN2
EN1
21
NC
FF
4.7U_0603_6.3V6M
2
PR406 GND
100K_0402_5%
12
13
14
15
11
@EMI@
PC412
3.3V LDO 150mA~300mA
2
<29,39> SPOK Ipeak=4.834A
ENLDO_3V5V PC402 PR403 Imax=3.384A
1000P_0402_25V8J1K_0402_5%
3V_EN 3V_FB 1 2 1 2 Iocp=10A
<29> 3V_EN
@ PJ404
JUMP_43X79
1 2
2 1 2 2
+19VB_5V
+19VB EMI@ PL403 @ PR408
PC418
HCB2012KF-121T50_0805 PU402 SY8286CRAC_QFN20_3X3 0_0603_5%
1 2 +19VB_5V BST_5V1 2 1 2
1
0.1U_0603_25V7K
BS
IN
IN
IN
IN
5*5*3 Common part SH000016800
LX_5V 6
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
20
LX LX PL404
7 19 LX_5V 1 2
GND LX +5V ALWP
1
1
@ PC414
PC415
EMI@ PC416
@EMI@ PC417
8 18 1.5UH_PCMB053T-1R5MS_6A_20% @ @ @
GND GND
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
PC419 4.7U_0603_6.3V6M
2
1
9 17 1 2
PG VCC
1
PR409
PC420
PC421
PC422
PC423
PC424
PC425
PC429
4.7_1206_5%
1SPOK_R
@EMI@
10 16
2
NC NC
OUT
LDO
EN2
EN1
21
FF
GND
2
PR413 @
12
13
14
15
11
0_0402_5%
VL
15V_SN
4.7U_0603_6.3V6M
5V LDO 150mA~300mA
2
680P_0603_50V7K
PC427
SPOK
Ipeak=7.74A
ENLDO_3V5V Imax=5.418A
PC426
2
@EMI@
Iocp=10A
2
5V_EN
3 3
PC413 PR407
1000P_0402_25V8J 1K_0402_5%
5V_FB 1 2 1 2
PR410
2.2K_0402_5%
1 2
<29> EC_ON @ PR411
0_0402_5% @ PJ401
1 2 +3V AL WP 1 2 +3VALW
<29,31,34> MAINPWON 1 2
JUMP_43X118
5V_EN
1M_0402_1%
4.7U_0402_6.3V6M
1
@ PJ402
1
PR412
PC428
+5V AL WP 1 2 +5VALW
1 2
JUMP_43X118
2
2
4 4

PWR-3.3VALWP/5VALWP
A B C D E

A B C D E

IC change RT8207K
@ PJ503
JUMP_43X79 Pin19 need pull separate from +1.35VP.
1 2
1 2 +19VB_1.2VP If you have +1.35V and +0.675V sequence question, 0.6Volt +/- 5%
EMI@ PL501 you can change from +1.35VP to +1.35VS. TDC 0.7A
HCB2012KF-121T50_0805
1
1 2 +19VB_1.2VP PR502 Peak Current 1A 1
+19VB 2.2_0603_5%
BST_1.2VP_R 1 2 BST_1.2VP
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
+1.2VP
1
@EMI@ PC502
EMI@ PC503
PC504
PC505
UG_1.2VP +0.6VSP
2
PQ503
AON7408L_DFN8-5
10U_0603_6.3V6M
10U_0603_6.3V6M
5
1
PC506 LX_1.2VP
1
PC507
PC508
0.1U_0603_25V7K
16
17
18
19
20
2
2
BOOT
VLDOIN
VTT
PHASE
UGATE
4 21
PAD
LG_1.2VP 15 1
LGATE VTTGND
1
2
3
PL502 14 2
1UH_6.6A_20%_5X5X3_M PR503
PGND VTTSNS
16K_0402_1% PU501
1 2LX_1.2VP 1 2 CS_1.2VP 13 3
+1.2VP PC509
CS RT8207PGQW_WQFN20_3X3
GND
5
1U_0402_10V6K
1 2 12 4 VTTREF_1.2VP
@EMI@ PR504 PR505
VDDP VTTREF
2 4.7_1206_5% 5.1_0603_5% 2
1 2 VDD_1.2VP 11 5
1 2
+5VALW VDD VDDQ
+1.2VP
1
PGOOD
4 PC516
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
1
TON
1
1
PC510
PC512
PC513
PC514
PC515
PC511
@EMI@ PC518 PC517 0.033U_0402_16V7K
FB
S5
S3
2
680P_0402_50V7K
2
2
PQ502 1U_0402_10V6K PR511
1
2
3
6
10
SI7716ADN-T1-GE3_POWERPAK8-5 2.2_0402_1%
FB_1.2VP
TON_1.2VP
EN_1.2VP
PR506
EN_0.6VSP
6.19K_0402_1%
+5VALW PR507 1 2 +1.2VP
470K_0402_1%
+19VB_1.2VP 1 2
1
PR501
2.2K_0402_5%
Vout=0.75V* (1+Rup/Rdown)
<14,29,32> SYSON
1 2 PR508 =0.75*(1+(6.19/10))
10K_0402_1%
=1.21V
2
1
PC501
0.1U_0402_10V7K
2
@ PR509
+3VALW 0_0402_5%
1 2
<14,29,32,35> SUSP#
3 @ PR510 @ PJ501 3
2
0_0402_5% JUMP_43X118
@ 1 2 +1.2VP 1 2 +1.2V_VDDQ
2
PJ505 <8> SM_PG_CTRL 1 2

JUMP_43X79
1
1
@ PC519 @ PJ502
PU502 JUMP_43X39
1
VIN_2.5VALW 1 8 +5VALW 0.1U_0402_10V7K

+0.6VSP
1 2
+0.6VS_VTT
2
VIN NC 1 2
+5VALW 2
GND NC
7
2
1
1
PC520 3 6 PC521 MOSFET: 3x3 DFN

4.7U_0603_6.3V6M PR513
VREF VCNTL 1U_0402_6.3V6K
H/S Rds(on): 27mohm(Typ), 32mohm(Max)
1
6.49K_0402_1% 4 5
VOUT NC Idsm: 7.5A@Ta=25C, 5.5A@Ta=70C
1
PR516 9
2
TP
100K_0402_1%
VREF_2.5VALW
L/S Rds(on): 13mohm(Typ), 15.8mohm(Max)
APL5336KAI-TRL_SOP8P8
Idsm: 12A@Ta=25C, 10.5A@Ta=70C
2
PQ504B D
20.5K_0402_1%
0.1U_0402_16V7K
+2.5VP
1
SYSON_2V5# 5
PR512
Choke: 7x7x3
PC522
G
Rdc=14mohm(Typ), 15mohm(Max)
6
PQ504A D
1 2 2 S PC524 Mode Level +0.6VSP VTTREF_1.2V

4
<14,29,32> SYSON G 10U_0805_6.3V6M Switching Frequency: 538kHz

S5 L off off
2
@ PR515 @ Ipe ak=7. 5A

PJ504 S3 L off on
0_0402_5% S
Iocp=Ipeak*1 .2A
1
+2.5VP 1
1 2
2
+2.5V S0 H on on
4
OVP: 110%~120% 4
JUMP_43X79 Note: S3 - sleep ; S5 - power off VFB=0.75V, Vout=1.365V
MOSFET footprint: SIS412DN
<32> SYSON_2V5# Security Classification

2015/10/02
Compal Secret Data
2016/11/10 Title
RT8207P
A B C D E

A B C D E
EN pin don't floating

If have pull down resistor at HW side, pls delete PR702
@ PJ705
JUMP_43X79
2 1
1 2 1 +19VB_1VALW @EMI@ PR605 @EMI@ PC602
1
4.7_1206_5% 680P_0603_50V7K @ PJ601

EMI@ PL601 1 2 SNUB_1VALW 1 2 JUMP_43X118
HCB2012KF-121T50_0805 PU601 1 2
+19VB_1VALW +1.0VALWP 1 2 +1.0VALW_PRIM
+19VB 1 2 2
IN PG
9 @ PR606
0_0603_5%
PC603
10U_0805_25V6K
0.1U_0402_25V6
3 1 BST_1VALW 1 2 BST_1VALW_R1 2 PL602
2200P_0402_50V7K
1
1
IN BS
EMI@ PC604
@EMI@ PC605
PC606
1UH_6.6A_20%_5X5X3_M
LDO_3V LX_1VALW
4
IN LX
6
0.1U_0603_25V7K
1 2
+1.0VALWP
2
5 19
14K_0402_1%
330P_0402_50V7K
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
220U_B2_4VM_R35M
1
1
IN LX
1
1
PR608
PC608
PC609
PC610
PC611
PC612
PC615
@ PR607 7 20
GND LX +
PC616
0_0402_5% 8 14 FB_1VALW Rup
2
GND FB
2
2
ILMT_1VALW 18 17 LDO_3V 2 @
GND VCC
1
1
EN_1VALW 11 10
EN NC
@ PR609 PC613 FB = 0.6V
1
ILMT_1VALW 13 12 2.2U_0402_6.3V6M
2
ILMT NC PR610
0_0402_5%
15 16
+3VALW Rdown
2
BYP NC 20K_0402_1%
21
Ipeak=9.5A
2
PAD
Imax=6.65A
SY8288RAC_QFN20_3X3 Pin 7 BYP is for CS.
1
The current limit is set to 6A, 8A or 12A when this pin Common NB can delete +3VALW and PC15
PC614
is pull low, floating or pull high 1U_0402_6.3V6K
2
=0.6*(1+(14/20))
Vout=1.02V
2 2
+3VALW
2
@ PR603
10K_0402_1%
1
@ PR602
0_0402_5%
EN_1VALW 1 2 +1.8VALW_PG <39>
1
@ PC601
PR601
0.22U_0402_10V6K
2
1M_0402_1%
2
3 3
4 4

Issued Date 2015/10/02 Deciphered Date 2016/11/10 Titl e
VCCP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Siz e Docu men t Nu mb er R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.2
D a te : Monday, July 18, 2016 She e t 38 of 44

A B C D E
A B C D E

IC change to G971
1 1
+3VALW
1
+3VALW
@ PJ703
1
JUMP_43X79
2
VIN_1.8VALW
1
+3VALW PC707
VIN_1.8VALW @ PJ702
1U_0402_6.3V6K JUMP_43X79
2
1
PC708 1 2
+1.8VALWP +1.8VALW_PRIM
2
1 2
4.7U_0603_6.3V6K PR702
2
10K_0402_1%
6
PU702
1
5 VIN_1.8VALW
VPP
VIN
2 7 2
<38> +1.8VALW_PG POK 9
TPAD
3
VO
1 2 EN_1.8VALW 8 4
<2 9,36 > S PO K VEN VO +1.8VALWP
GND
0.01U_0402_25V7K
1
@ PR708 2
1
ADJ
PC709
0_0402_5% PR709
PR710 @ PC710 G971ADJF11U_SO8 12.7K_0402_1%
Rup
1
1M_0402_1% 0.1U_0402_16V7K
2
2
1
FB_1.8VS PC711
2
22U_0603_6.3V6M
2
1
PR711
10K_0402_1%
Rdown
2
Vout=0.8V* (1+(12.7/10)) = 1.816V
3 3
4 4

SY8032

A B C D E
A B C D E
PC802
0.01U_0402_25V7K PR802
1.5K_0402_1%
1 2 1 2
1 2
1 1
PC803 PC804
1000P_0402_50V7K 15P_0402_50V8J
1 2
1000P_0402_50V7K
PR803 100_0402_1%
24K_0402_1%
1
2
1 2 @ PR804 PR805 CS N_ 1b < 41 >
+VCC_SA
1
PR808
PC806
0_0402_5% 1.8K_0402_1%
1 2 VSPP_1b 1 2 VSP_1b PH802
0.01U_0402_25V7K
<14> VCCSA_SENSE
1
100K_0402_1%_NCP15WF104F03RC
4700P_0402_25V7K
1
PC805 PR807 pl a c e
2
1000P_0402_50V7K 649_0402_1% cl o s e
1 2
2
1
VSNN_1b 2VSN_1b
PC809
PC833
1 2 1
<14> VSSSA_SENSE to SA chock
2
1 2 @ PR806 1 2 PR816
2
0_0402_5%
PR809 100_0402_1% PR811 PC807 @ 15K_0402_1%
20K_0402_1% 2200P_0402_50V7K
1 2 @ PR812 1 2 PR819
+VCC_GT
2
PR810 100_0402_1% 0_0402_5% 66.5K_0402_1% 2 1
<16> VCCGT_SENSE
1 2 VSP_2ph 2 1 PR818 S W_ 1b <4 1> +3VS
1
PC811 8.25K_0603_1% PR821
@ PR813 PC808 PR814 470P_0402_50V7K 10K_0402_1%
0_0402_5% 1000P_0402_50V7K 1K_0402_1% 1 2
2
1 2 VSNN_2ph 1 2 VSN_2ph VR _P W R G D <2 9 >
<16> VSSGT_SENSE
1
1 2 1 2 @ PR863
PR815 PR817 PC810 0_0402_5% +1.0V_VCCST
100_0402_1% 49.9_0402_1% 3300P_0402_50V7-K 1 2 close to the longer distance phase(81208 or 81210)
549_0402_1%
1
VR _ON <29 ,32 >
Alert , D a t a , C l k .
PR822 24.9K_0402_1%
PR820
1 2
45.3_0402_1%
110_0402_1%
100_0402_1%
P WM_ 1b < 4 1>
470P_0402_50V7K
0.1U_0402_16V7K
2
1
pl a c e PC812
110_0402_1%
DR VON <4 1>
1
PC813
PC815
PR828
cl o s e 470P_0402_50V7K
2
to GT chock PR829
4.75K_0402_1%
49
48
47
46
45
44
43
42
41
40
39
38
37
PH803 8.25K_0603_1%
2
2
PR823
THERM_ 220K 5% 0402 PC814 PR834 @ 1 2
SW_1a <41>
2
VR_ H O T# < 2 9>
PR824
PR826
PR866
1 2 15P_0402_50V8J 49.9_0402_1% PR835
VSN_2ph
VSP_2ph
VSP_1b
VSN_1b
COMP_1b
CSN_1b
CSP_1b
IOUT_1b
EN
PSYS
VR_RDY
ILIM_1b
TAB
1
1 2 15K_0402_1%
2 1 2 2
1 1
PR825 PR830 PC818 1 36 @ PR860 @ S OC _ SVID_ C LK <1 6> PC819 pl a c e
2200P_0402_25V7K
2
0.033U_0402_16V7K
2 IOUT_2ph PWM_1b 35 1 0_0402_5%
2
73.2K_0603_1% 165K_0402_1% 56P_0402_50V8 470P_0402_50V7K cl o s e
SWN_GT1 DIFFOUT_2ph DRVON
PC820
PC834
1 2 1 2 1 2 PR833 PC816 3 34 SCLK 1 2
S OC _ S VID _AL ER T# _R <1 6> to L1
2
1
1
4 FB_2ph SCLK 33 ALERT#
PR831 12.4K_0402_1% 2200P_0402_50V7K PU801 PR862
1
COMP_2ph ALERT#
75K_0402_1% 1 2 5 32 SDIO 110_0402_1%2 PR836 PH804
ILIM_2ph SDIO SO C_S VID_D A T < 16 >
PC817 2 6 NCP81208 31 1 2 66.5K_0402_1% @ 100K_0402_1%_NCP15WF104F03RC
2
CSCOMP_2ph VR_HOT#
1000P_0402_50V7K 7 30 PR869 100_0402_1% 2 1
2
8 CSSUM_2ph IOUT_1a 29
<41> CSN_GT1
2
1 2 9 CSREF_2ph CSP_1a 28
+5VS @ PR868 0_0402_5% 10
CSP2_2ph CSN_1a
27
CSN_1a <41>
ROSC_COREGT
0.1U_0402_25V6
CSP1_2ph ILIM_1a
ADDR_VBOOT
1 2 11 26
34.8K_0402_1%
0.1U_0402_16V7K
4700P_0402_25V7K
1
1
TSENSE_1ph
TSENSE_2ph COMP_1a
RSOC_SAUS
ICCMAX_2ph
PC821
PC825
1 2 12 25
+19VB
100K_0402_1%_NCP15WF104F03RC
ICCMAX_1a
ICCMAX_1b
PWM1_2ph
PWM2_2ph
1
VRMP VSN_1a
PC822
PR842
@ PR864 PR801 PC826
PWM_1a
1
VSP_1a
0_0402_5% 1K_0402_1% PC824 1000P_0402_50V7K
0.01U_0402_50V7K
2
2
1
1
PH801
PC801
3300P_0402_50V7-K
61.9K_0402_1%
VCC
1 2
1 2 @ PR865 PR840 PC829
1
PC827 0_0402_5% 100_0402_1% 15P_0402_50V8J
2
1 2 1000P_0402_50V7K VSN_1a 1 2 1 2 2 1
13
14
15
16
17
18
19
20
21
22
23
24
<41> SWN_GT1
2
PR844
@ PR850
1
PR845 1 2 PR843 PR848
2.26K_0402_1% +5VS 2_0402_1% 715_0402_1% PC828 1000P_0402_50V7K
VSSSENSE <16>
1.62K_0402_1%
2
24K_0402_1%
33.2K_0402_1%
2
1
1
1 0 0 度C PR870 PR846 2.43K_0402_1%
1 2 1 2 1 2
PR853
PR854
pl a c e +5VALW VCCSENSE <16>
2_0402_1%
cl o s e VSP_1a 1 2 1 2
@ PR847 2 1
to GT high side PC830 0_0402_5% PR851 +VCC_CORE
2
1
1000P_0402_50V7K PR867 2.43K_0402_1% 100_0402_1%
PC831
1U_0603_10V6K
2
1 2
1
@ PR852
1000P_0402_50V7K
PC832
0_0402_5%
61.9K_0402_1%
1
1
2
P WM_ 1a < 4 1> PH805
100K_0402_1%_NCP15WF104F03RC
3 3
PR855
pl a c e
2
cl o s e
100K_0402_1%
10K_0402_1%
to VCC_CORE high side
48.7K_0402_1%
15.8K_0402_1%
1
1
PR856
PR857
PR858
PR859
2
2
P WM1_ 2p h <4 1>
4 4

IMVP8, NCP81206

A B C D E
A B C D E
@ PJ901
JUMP_43X79
+19VB schematic from A4WAS
1 2
1 2
EMI@ PL9002
HCB2012KF-121T50_0805
+19VB_CPU 1 2
change PL9002, PL9003
InputCapacitor:
10uF_0805_X5R_25V SM01000C000 to comm VC C :
part SM01000P200 Imax=21A Ipeak=29A Iocp=37.7A
@EMI@ PC9208
10U_0805_25V6K
10U_0805_25V6K
2200P_0402_50V7K
VC C G T :
EMI@ PC9003
1
0.1U_0402_25V6
5
Imax=18A Ipeak=31A Iocp=40A
@EMI@ PC9015
0.1U_0402_25V6
1
1
1 + 1
PQ9002
PC9014
PC9002
PR9001 PC9001 PC9004
AON6428L_DFN8-5
2.2_0603_5% 0.22U_0603_16V7K @EMI@ 33U_25V_M VC C S A :
1 2 1 2 PR9015 Imax=4A Ipeak=4.5A Iocp=10A
2
0_0603_5% 2
1 2 4
PU9001
NCP81253MNTBG_DFN8_2X2
(Common Part) +VCC_CORE
3
2
1
1 8 HG_VCORE SH000011H00 7*7*4
BST DRVH
PL9001 0.22UH 20% FDUE0640J -H 25A
2 7 SW_VCORE 1 4
<40> PWM_1a PWM SW
3 6 2 3
<40> DRVON
5
EN GND
4 5
@EMI@ PR9002
+5VS
PAD
AON6794_DFN5X6-8-5
AON6794_DFN5X6-8-5
VCC DRVL
PQ9001
PQ9003
4.7_1206_5%
1
1
CSN_1a <40>
9
LG_VCORE 4 LG_VCORE 4 DCR=0.98m ohm +-5%

PC9049
4.7U_0603_6.3V6K
@
Common part SH000011H00
2
2
3
2
1
3
2
1
PC9073
680P_0603_50V7K
1
2
SW_1a <40> @ PJ902
@EMI@
JUMP_43X79
1 2
1 2 +19VB
EMI@ PL9007
HCB2012KF-121T50_0805
PR9005 PC9083 +19VB_CPU_GT 1 2
2.2_0603_5% 0.22U_0603_16V7K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
2200P_0402_50V7K
@ PC9187
EMI@ PC9086
1 2 1 2
33U_25V_M
2 1 2
1
+
@EMI@ PC9085
PC9087
PC9088
PC9206
PC9207
0.1U_0402_25V6
1
5
2
2
2
AON6428L_DFN8-5
PU9003
4 (Common Part) +VCC_GT InputCapacitor:
PQ9005
NCP81151MNTBG_DFN8_2X2
1 9
BST FLAG SH000011H00 7*7*4 10uF_0805_X5R_25V
2 8 HG1_GT
<40> PWM1_2ph PWM DRVH
PL9005 0.22UH 20% FDUE0640J -H 25A
3
2
1
DRVON 3 7 SW1_GT 1 4 +VCC_GT
1
EN SW
@ PC9210
+5VS
4 6 2 3 DCR=0.98m ohm +-5%
1
VCC GND
100P_0402_25V8K @
Common part SH000011H00
5
5
@EMI@ PR9010
PC9209 PR9009 10_0402_1%
1
DRVL 1 2
PQ9009
PQ9007
4.7_1206_5%
100P_0402_25V8K
AON6794_DFN5X6-8-5
AON6794_DFN5X6-8-5
1
CSN_GT1 <40>
PC9090
4.7U_0603_6.3V6K
2
LG1_GT 4 LG1_GT 4 @
SWN_GT1 <40>
PC9092
680P_0603_50V7K
3
2
1
3
2
1
1 2
@EMI@
InputCapacitor: @ PJ903
JUMP_43X79
10uF_0805_X5R_25V +19VB_SA 1 2 +19VB
1 2
10U_0805_25V6K
10U_0805_25V6K
2200P_0402_50V7K
EMI@ PC9118
@EMI@ PC9117
0.1U_0402_25V6
1
3 3
PC9115
PC9116
PR9013 PC9119
2
2.2_0603_5% 0.22U_0603_16V7K
1 2 1 2
HG_SA
AON7934
Rds(on)=12.4~15.8m ohm
PU9004
PQ9008 DCR=6.2m ohm +-5%
4
NCP81253MNTBG_DFN8_2X2 AON7934_DFN3X3A8-10
Common part SH000015M00 +VCC_SA
D1
D1
D1
G1
1 8
BST DRVH PL9006
2 7 10 9 SW_SA 1 4
<40> PWM_1b PWM SW D1 D2/S1
DRVON 3 6 2 3
@EMI@ PR9014
EN GND
G2
S2
S2
S2
4.7_1206_5%
1
4 5
+5VS
PAD
VCC DRVL 0.47UH_MMD05CZR47M_12A_20%

5
8
1
9
PC9154
4.7U_0603_6.3V6K
CSN_1b <40>
2
PC9155
680P_0603_50V7K
1
SW_SA SW_1b <40>

2
LG_SA
@EMI@
4 4

Power Train

A B C D E
1
0.2
R ev
44
of
42
She e t
B5W1S M/B LA-D671P
E
E
Monday, July 18, 2016
Power Train
Nu mb er
+VCC_SA
Docu men t
PC9162
1U_0201_4V6M
+VCC_SA
1 2
PC9161
D a te :
Titl e
Siz e
PC9125 PC9140 1U_0201_4V6M
22U_0603_6.3V6M 22U_0603_6.3V6M
C
1 2
1 2 1 2 PC9160
PC9124 PC9139 1U_0201_4V6M
22U_0603_6.3V6M 22U_0603_6.3V6M
22uF_0603*3
22uF_0603*9
1 2
1uF_0201*7
1 2 1 2
PC9159
PC9123 PC9138 1U_0201_4V6M
22U_0603_6.3V6M 22U_0603_6.3V6M
1 2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
1 2 1 2
PC9158
2016/11/10
PC9121 PC9137 1U_0201_4V6M
@
unpop:
22U_0603_6.3V6M 22U_0603_6.3V6M
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1 2
1 2 1 2
PC9157
pop:
@
PC9120 PC9203 1U_0201_4V6M

22U_0603_6.3V6M 22U_0603_6.3V6M
1 2
SA
1 2 1 2
PC9156
@
PC9136 PC9204 1U_0201_4V6M

22U_0603_6.3V6M 22U_0603_6.3V6M
1 2
Deciphered Date
1 2 1 2
Compal Secret Data

D
D
2015/10/02
+VCC_GT
+VCC_GT
PC9104 PC9114 PC9135 PC9188 PC9153 PC9143

@
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 0.47U_0201_4V6M 1U_0201_4V6M
1 2 1 2 1 2 1 2 1 2 1 2
PC9103 PC9112 PC9134 PC9189 PC9152 PC9142
@
Issued Date
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 1U_0201_4V6M 1U_0201_4V6M
1 2 1 2 1 2 1 2 1 2 1 2
PC9102 PC9111 PC9133 PC9190 PC9151 PC9183
1 2 1 2 1 2 1 2 1 2 1 2
PC9101 PC9110 PC9163 PC9191 PC9176 PC9181
0.47uF_0201*4
1 2 1 2 1 2 1 2 1 2 1 2
PC9100 PC9109 PC9167 PC9194 PC9149
22uF_0603*30
C
C
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 1U_0201_4V6M
22uF_0603*6
1uF_0201*9
1uF_0201*1
1 2 1 2 1 2 1 2 1 2
PC9099 PC9108 PC9165 PC9195 PC9148
@
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 1U_0201_4V6M

220_D2*2
1 2 1 2 1 2 1 2 1 2
330uF*1
PC9098 PC9107 PC9168 PC9147

unpop:
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 1U_0201_4V6M
1 2 1 2 1 2 1 2
PC9097 PC9130 PC9170 PC9146
@
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M SGA20221D40 1U_0201_4V6M
1 2 1 2 1 2 1 2
PC9096 PC9129 PC9171 PC9186 PC9145
@
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 220U_D2 SX_2VY_R9M 1U_0201_4V6M

+
1
1 2 1 2 1 2 1 2
PC9095 PC9126 PC9169 PC9093 PC9144
@
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 220U_D2 SX_2VY_R9M 0.47U_0201_4V6M

+
1
1 2 1 2 1 2 1 2
+
1
2
330U_2V_M
PC9205
+VCC_CORE
B
B
543016_543016_SKL_PDG_UY_1_0_pub
PC9021 PC9038 PC9062 PC9052 PC9041 PC9048 PC9078 PC9198

@
+VCC_CORE
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M
1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2
@

VCORE Output Capacitor:
1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2
@
1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2
1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2
@
1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2
330uF_R9_1PCS
PC9018 PC9033 PC9057 PC9177 PC9023 PC9072 PC9174

@
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M

22uF_0603*25
22_0603_8PCS
1uF_0201*35
1 2 1 2 1 2 1 2 1 2 1 2 1 2
PC9006 PC9032 PC9056 PC9022 PC9071 PC9065
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M
220uF *1
1 2 1 2 1 2 1 2 1 2 1 2
@
PC9017 PC9031 PC9055 PC9011 PC9070 PC9064

220U_D2 SX_2VY_R9M
UNPOP
1 2 1 2 1 2 1 2 1 2 1 2
PC9005 PC9030 PC9054 PC9010 PC9069 PC9196
@
A
1 2 1 2 1 2 1 2 1 2 1 2
PC9027
PC9016 PC9029 PC9053 PC9009 PC9066 PC9197

1 2 1 2 1 2 1 2 1 2 1 2
+
1

1
4
5 4 3 2 1
Version change list (P.I.R. List) Page 1 of 1

for PWR
Item Fixed Issue Reason for change Rev. PG# Modify List Date Phase
01 CPU transient modify transient set P40 PR857 change to 100K ohm
PR842 change to 34.8K ohm 4/12 DVT
D
PR836 change to 66.5k ohm D
PR843 change to 715 ohm

PR515, PR804, PR806, PR812, PR813. PR865. PR847. PR860, PR863, PR852, PR864,
02 BOM change reduce BOM quantity PR9015 change to R-Short 7/6 PVT
03 sequen ce add RC to adjuct PR501 change to 2.2K from R-short

POP PC501to 0.1U
C C
B B
A A

PIR
5 4 3 2 1

A B C D E
Version change list (P.I.R. List) Page 1 of 1 for HW
Item Page Title Date Issue Description Solution Description Phase Rev.
1 14,32 Load SW 4/15 For load SW output stable. 1. Add CC127, CQ5, CQ6. DVT 0.2
DVT 0.2
2 29 EC 4/15 Update Board ID. 1. Change RB4 from 0 ohm to 12k ohm.
1 1
DVT 0.2
3 30 LED 4/15 1. Change RG4,RG11 to 1.24k ohm.
Follow B5W1S LED brightness test.
2. Change RG6,RG10 to 820 ohm.
4 20 Ripple 5/13 Improve +0.6VS DDR4 ripple quality. 1. Change CD64 from non-pop to pop. DVT 0.2
5 14 Ripple 5/13 Improve +VCCIO & +1.0VS_VCCSTG ripple 1. Pop UC6. DVT 0.2
2. Depop UC8 & CC126.
Change Q1, Q2, Q6, QC2, QG1, QK1, QY1 from SB00000DH00 (S TR DVT 0.2
Standard DMN66D0LDW-7 2N SOT363-6) to SB00000EO00 (S TR 2N7002KDW 2N
6 part 5/18 Follow standard part.
SOT-363-6 PANJIT)
7 25 ESD diode 5/26 No spacing to add test point for ATE. Change DA1,DA2 from reserve MESC5V02BD03_SOT23-3 to DVT 0.2
TVNST52302AB0_SOT523
2
8 23 Crystal cap 5/27 Fine tune 25MHz crystal to minimum frequency shif t. Chagne CL17 from 12P_0402_50V8J to 10P_0402_50V8J DVT 0.2 2
1 NPI test 7/6 For NPI test only. 1. Change RC125, RD43, RD44, RD45, RD52, RD54, RD56, RX10, RX11, RY1~RY5, RY7, PVT 1.0
RY8, RY10, RS21, RS22, RS24, RS25, RG8 from 0_0402 resistor to R-short
2. Change RL1, RL13, RB22 from 0_0805 to R-short
2 29 Board ID 7/6 Change board ID for PCB Rev1.0 Change RB4 from 12K_0402 to 15K_0402. PVT 1.0
3 30 NPI test 7/14 For NPI test only. Change SWK1 from pop to non-pop. PVT 1.0
4 32 NPI test 7/15 To reduce +2.5V powe falling t i me. Reserve R31 & Q7 discharge circuit. PVT 1.0
3 3
4 4

Issued Date 2016/07/18 Deciphered Date 2016/11/10 Tit le
PIR-HW1
Size Document Number R ev
Date : Monday, July 18, 2016 Sh ee t 44 of 44

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Acer Extensa 2540 B5W11 LA-E061P LA-E061P 1.0-LA-D671P

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Acer Extensa 2540 B5W11 LA-E061P LA-E061P 1.0-LA-D671P

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A B C D E

B5W11 MB Schematic Document

I'm from VIETNAM

HDMI Conn. eDP Fan Control

SATA3.0 SATA3.0 48M H z

RJ45 conn. LPC/eSPI BUS

RTC CKT. Sub Board

4 DC/DC Interface CKT. 4

Security Classification Compal Secret Data Compal Electronics, Inc.

I'm from VIETNAM

Board ID Table for AD channel

+VCC_G T Processor Graphics Power Rails ON O FF O FF

+VCC _ S A System Agent power rail ON O FF O FF

+0.6VS_VTT DDR +0.6VS power rail for DDR terminator . ON O FF O FF

+1.0VALW_PRIM +1.0V Always power rail ON ON ON*1

+VC C IO CPU IO power rail ON O FF O FF

+1.2V_ V D D Q DDR4 +1.2V Power Rail ON ON O FF

Unpop @ +3VLP +19VB to +3VLP power rail for suspend power ON ON ON

Connector CONN@ +3VALW System +3VALW always on power rail ON ON ON*1

CODEC(ALC255) 255@ +5VS System +5V power rail ON O FF O FF

CODEC(ALC233) 233@ +RTCVC C RTC Battery Power ON ON ON

LPC MODE for EC LPC@

EMI requirement EMI@

43 level BOM table

Security Classification Compal Secret Data

I'm from VIETNAM

+1.2VP (PJ501) +1.2V_VDDQ (JPC1,JPC2) +1.2V_VDDQ_CPU (RC141) +1.2V_VCCSFR_OC R-Short

SYSO N APL5336KAI R-Short

(PU502) +2.5VP (RC172) +3VALW_1.8VALW_PGPPD (RC178) +1.8VS_3VS_PGPPA 2

EN_1VA LW SY8288RAC JUMP R-Short R-Short

Security Classification Compal Secret Data Compal Electronics, Inc.

77 EC_SMB_C K 1 100 ohm 7

KBC SCL2 79 SOC _S ML1C LK

I2C Address Table

BQ24780 (Charger IC) 0x12

I'm from VIETNAM

+VCCPRIM_CORE/+1 .0VALW _P RIM

Security Classification Compal Secret Data Compal Electronics, Inc.

I'm from VIETNAM - SuaLaptop365

RC2 1 2 1K_0402_5% H_THERMTRIP#

1 2 H_PROCHOT#_R C65 PECI

1 2 100K_0402_5% TP_INT# A65 THERMTRIP# B61 CPU_XDP_TCK0

RC15 2 CMC@ 1 100_0402_5% SOC_XDP_TDO

Security Classification Compal Secret Data Compal Electronics, Inc.

I'm from VIETNAM - SuaLaptop365

A 4 DDR_DRAMRST# CC70 1 2 .1U_0402_16V7K

74AUP1G07GW_TSSOP5 DDR_VTT_CNTL to DDR

Security Classification Compal Secret Data Compal Electronics, Inc.

I'm from VIETNAM - SuaLaptop365

SOC_SMBCLK_1 RC222 1 2 2.2K_0402_5%

SOC_SML0CLK RC49 1 2 499_0402_1%

SOC_SML0DATA RC50 1 2 499_0402_1%

Security Classification Compal Secret Data Compal Electronics, Inc.

I'm from VIETNAM - SuaLaptop365

HDA for AUDIO HDA_SYNC

SPKR / GPP_B14 (Internal Pull Down):

TOP Swap Override A36 C37 +3VALW_1.8VALW_PGPPD

Security Classification Compal Secret Data Compal Electronics, Inc.

I'm from VIETNAM - SuaLaptop365

RC91 1 2 20K_0402_5% SOC_SRTCRST# SOC_XTAL24_OUT 1 2

1 2 EC_VCCST_PG Rev_0.53 Cannonlake U use 38.4M 30 ohm ESR

CC50 2 1 .1U_0402_16V7KH_CPUPWRGD B 4 PLT_RST_BUF#

#543016 PDG2.0 P.599