JM3 Power-up Sequence

1. To know JM3 Power-Up Sequence.

2. More easy to find out the root-cause if system
Lock-Up of No-Power.
3. To realize each step before BIOS is working.
4. Summarized preliminary Power-Up sequence
diagram.
5. Power-up sequence after POWER_SW# in the
Nutshell.

2003/2/20 JM3 Team

 Block Diagram High Volt.
Section

DCIN+ +DC_IN DC_IN+ SDC_IN+

Adapter is
12V alive Charging PBATT+ PWR_SRC
System on, Bat V-CHG
powered only
SBATT+
Charging
PWR-
charging
PCIRST#
Warm swap only D/D Power GOOD,
CPURST# RBAT_7.2V +RTCSRC D/D
shutdown
+3VALW,+5VALW
Section
+5VSUS,
Banias CPU +RTC_PWR3_3V +RTC_PWR5V +1_5VSUS +3VSUS
+2_5VSUS
FSB THERM_STP#
LIVE_ON_BATT
VCCRTC
Montara GM ALWON
RTCRST# ACAV_IN

HUB -LINK
BUS
SUSPWROK
Section 1715PWROK
SUS_ON
ICH4 AUX_EN

+VCC1_2_GMCH,
LPC VTT, SLP_S3#
ICH4
MACALLEN
SIO 12V
(LPC47N254)
(MACALLEN) RUN_ON
+5VRUN, +3VRUN,
+1_5VRUN, +2_5VRUN,
X-BUS Delay VHCORE +1_8VRUN
RUNPWROK
Flash ROM (3~12mS) (IMVP IV)
2003/2/20 JM3 Team
(8M bit) DELAY_IMVP_PWRGD
Binchuan:
Binchuan:
(1).ADP-IN
(1).ADP-IN
(2).+DC_IN
(2).+DC_IN
ADAPTER-IN(P43)
(3).DC_IN+
(3).DC_IN+
Schematic
Schematicpage
page29
29
R380 D24
2 1 D13R_VCC 2
DC_IN+
15K 3 SBATT_CH

1
+12V

1
PWR_SRC
RB715F R379
10K
+RTCSRC Binchuan:
Binchuan:
Q48
D25 FDG316P
6 H HH: :High
HighLevel.

2
30 RBAT_7.2V
2 1 4 5
2
Level.
TRACE:20MIL TRACE:20MIL 1
C208
1N5819HW
LL: :Low
LowLevel
Level
TRACE:20MIL
1000P
RP97 And
Andso soon.
on.

3
2
4
1
3 L
4P2R-S-100K
+3VALW

3
Near JDCIN1
2 47K Q46
21 SYS_SUSPEND
DTC144EUA
ADP-IN (1)
1

47K
2

Near JDCIN1 D44 D45 C855

+DC_IN (2) DC_IN+ (3)
DA204U 100P_50V

1
UDZ3.6B_NC

C856
Near JDCIN1
3

100P_50V

Q37
RV3 +DC_IN FDS6679
JDCIN1 1 2 DC_IN+
POWER_JACK 8

1
L27 BLM11B102S VZ0603M260APT
PS_ID 22,34
H
1
2
3
7
6
5
H
H
1

1
2 DCIN+ 2 3 C35

1
DCIN- 1 4
3 C857 .47U_0805 R27 C38 C41 C357 C42 C363 R542
+
FL1 CM1922 .1U_50V 25V 240K .01U .1U_50V .1U_50V .1U_50V 10U_25V_1210 4.7K
4
1

RV2 RV1
CM1922 C858
9
8
7
6
5
4

2
2003/2/20 VZ0603M260APT 0.01U_50V JM3Q49_G
Team
R22 47K
2

1 2
VZ0603M260APT
Binchuan:
Binchuan:
(4).
(4).DC_IN+
DC_IN+totoSDC_IN+
Schematic
SDC_IN+ SDC_IN+(P37)
Schematicpage
page37
37
SDC_IN+(4)
H
H
DC_IN+

2003/2/20 JM3 Team

Binchuan:
Binchuan:
(5).
(5).SDC_IN+
SDC_IN+toto PWR_SRC
Schematic
PWR_SRC PWR_SRC(P36)
Schematicpage
page36 36

PWR_SRC

2003/2/20 JM3 Team

Binchuan:
Binchuan:
+RTCSRC
+RTCSRCsupply
and
supply+RTC_PWR5V
+RTC_PWR5V +RTCSRC(P41,43)
and+RTC_PWR3_3V
+RTC_PWR3_3V

R380 D24
2 1 D13R_VCC 2
DC_IN+
15K 3 SBATT_CH

1
+12V
+RTCSRC PWR_SRC
RB715F R379 +RTCSRC
10K
D25
Q48
FDG316P
PWR_SRC
6

2
2 1 4 5
30 RBAT_7.2V

C208
TRACE:20MIL 1N5819HW TRACE:20MIL
H 2
1 H
TRACE:20MIL
1000P
RP97

3
2 1
4 3

4P2R-S-100K

3
2 47K Q46
21 SYS_SUSPEND
DTC144EUA

47K

1
+RTCSRC
+RTCSRC H
+RTCSRC +RTCSRC

R382 10K H R394 10K H

H 1 2
U35 MAX1615
1 2
U39 MAX1615
1 3 +RTC_PWR3_3V 1 3 +RTC_PWR5V
IN OUT 4 IN OUT 4
C645 5/3# C662 5/3#
C644 5 2 C646 C661 5 2 C654
SHDN GND SHDN GND
.1U_50V SOT23-5 +RTC_PWR3_3V
10U_10V .1U_50V SOT23-5 10U_10V
+RTC_PWR5V
1U_25V 1U_25V

2003/2/20 JM3 Team

Binchuan:
Binchuan:
ACAV_IN
ACAV_INwill
generated
willbe
be ACAV_IN(P37)
generatedafter
after
+RTC_PWR5V.
+RTC_PWR5V.
+RTC_PWR5V

DC_IN+ (3) DC_IN+ +RTC_PWR5V

H
H

1
R459
R468 1K
75K/F
R465 10K 1
1 2 2 Q61

2
3 3906
R464 1M
1 2
ACAV_IN 22,36,41
1

2
U52
H

1
R471
12.7K/F
1 LM431SACMF ACAV_IN
R458
100K
2

Binchuan:
Binchuan:
2003/2/20 JM3 Team ACAV_IN
ACAV_INgenerate
generatetotonotice
noticeSIO
SIO
about
aboutAdaptor(Present).
Adaptor(Present).
Binchuan:
Binchuan:
MAX1999
+3VALW&+5VALW(P41)
MAX1999use useLDO
LDOtoto
output
output+5VALW&+3VALW
+5VALW&+3VALW
while
whileU50
U50pinpin17(VCC)
17(VCC)
has
has Power Sourceand
Power Source and
Pin 6 is at Logic H.
Pin 6 is at Logic H. H
PWR_SRC

H VCC

SHDN

THERM_STP#

2003/2/20 JM3 Team

Binchuan:
Binchuan:
(6).As
(6).Assoon
RTCRST#
soonas
RTCRST#will
(Reset
as+RTC_PWR3_3V
+RTC_PWR3_3Von,
willbe
(Reset CMOS)
CMOS)
befrom
fromLow
on,then
Low?High.
?High.
then
RTCRST#(P9)
VCCRTC

+RTC_PWR3_3V
H
H

Binchuan:
H
Binchuan:
RTCRST#
CLK_32KX1/X2
CLK_32KX1/X2must must
be
be generated, it’sfor
generated, it’s for
RTCCLK units(ICH4)
RTCCLK units(ICH4)
using
usingtotogenerate
generate
SLP_S3#
SLP_S3#&SLP_S5#.
&SLP_S5#. ICH4

OSCILLATION

2003/2/20 JM3 Team

Binchuan:
Binchuan:
(A).POWER_SW#
(A).POWER_SW# generate
the
generate POWER_SW#(P41,P21)
thePOWER_SIO#,
POWER_SIO#,and andIfIf
MACALLEN(SIO)
MACALLEN(SIO)isisalive
alive
then
then it’ll assert SUN_ONtoto
it’ll assert SUN_ON +RTC_PWR5V

+RTC_PWR5V +RTC_PWR5V

MAX1999
MAX1999(3/5VSUS)

1
C658
(3/5VSUS)
H-L-H R391

10K
5
U36A
7WZ14
1

.1U
2

U41
5 7SH32

2
POWER_SW# 1 6 2
POWER_SW# 27,28 POWER_SW#
4
C650 1

.1U

D26
2 1
21 PWRSW_SIO#
+RTC_PWR5V
RB751V
C657
1 2

POWER_SIO# H-L-H R397

1
100K
2
5
.1U
U40
NC7ST32
2
22 LIVE_ON_BATT 4
1
22,36,37 ACAV_IN

MACALLEN(SIO)

H-L-H

H
SUS_ON
2003/2/20 JM3 Team
Binchuan:
Binchuan:
THERM_STP#
THERM_STP#isisOD
generated its
ODand
function
andwill
willbe
after
be
+3VSUS.
generated its function after +3VSUS.
MAX1999(P41)
SHDN#
MAX1999

ON3

ON5

SUS_ON H
SUS_ON
H

Binchuan:
Binchuan:
With
Withrespect
respectof
ofMAX1999,
MAX1999,the
theSHDN#
SHDN#pin
pinneed
2003/2/20
Keep ‘H’
H
JM3 Team to at Logic ‘H’and Enable ON3 & ON5 from
need
to at Logic ‘H’and Enable ON3 & ON5 from
SUS_ON
SUS_ONsignal
signalto
togenerate
generate3/5/12V.
3/5/12V.
Binchuan:
Binchuan:
SUS_ON
SUS_ONturn
While
turnon
WhileMAX1999
on+3/5VSUS
+3/5VSUSpower.
MAX1999stable
stablethen
power.
thenitit
3/5/12V(P41)
generate
generateSUSPWROK_5V.
SUSPWROK_5V.

15V
+5VSUS
H H
H
+3VSUS

MAX1999
H
H SUSPWROK_5V

+12V

2003/2/20 JM3 Team

Binchuan:
Binchuan:
+3VSUS?
+3VSUS? THERM_STP#
THERM_STP#atatLogicLogic‘H’.
‘H’.
THERM_STP#(P28)
Guardian
GuardianThermal
ThermalICICcontrol
controlcurrently
currently
System
SystemThermal
Thermal2status.
status.
THERMDA ATF_INT# 21

2 THERMDC +5VSUS RT1 should be placed near DDR.

Thermal IC U4
R317

2.21K/F
R80 14,22,25 DAT_SMB DAT_SMB 1 +5VSUS
CLK_SMB 2 THDAT_SMB 9
+3VSUS 14,22,25 CLK_SMB THCLK_SMB ATF_INT#

1
RT1
49.9/F C104 R267 13 TH11-3H103FT
THERMDA 1K SMBADDRSEL
.1U C114 18 R309
REM_DIODE2_P
THERMDC 2200P
17
REM_DIODE2_N VCP
23 VCP
Q42
t 10Kohm
@25 degree C
10K

32
R92 11 +3VSUS C105
9,35 SUSPWROK VSUS_PWRGD
+RTC_PWR3_3V 1K 2
10 2200P 5V_CAL_SIO# 21
+RTC_PWR3V 16
C115 R265 5 RESSERVED RHU002N06

1
35 +3V_PWROK 1K +3V_PWROK#
.1U +3VSUS 21
27,41 POWER_SW# POWER_SW# Place under CPU
Notes: THERMTRIP1# 6 19
THERMTRIP1# REM_DIODE1_N 20
R86 7 REM_DIODE1_P Q17 1
Vset=(Tp-75)/16 C461 100K THERMTRIP2# +3VALW C110 2
Where Tp=75 to R268 R87 8
THERMTRIP3#
15
THERMTRIP_SIO 24
3
106 degree C .1U 100K 2200P
30.1K/F 22 THERM_STP# 3904
14 VSET R330
Set trip point=90 degree c 3 HW_LOCK# 12
VSS INTRUDER# Put 2200P close to Guardian.
Vset = (90-75)/16= 100K
0.9375 V R269
C852 R266
Guardian temp-tolerance= +/-3 degree C 12.1K/F 1K THERMTRIP_SIO22
2200P

THERM_STP#41
EMC6N300
+3VSUS
INTRUDER#9

R534
8.2K

THERMTRIP1#
VTT

R535 2.2K Q85 3

2
1
C853
Binchuan:
Binchuan:
3904 .1U

2,9 THERMTRIP# While

While
near Guardian IC. THERM_STP# to be
C853 needs to be placed
THERM_STP# to be
2003/2/20 JM3 Team generated
generatedwill willcause
causeMAX1999
MAX1999
force
forcePOWER POWERSHUT SHUTDOWN.
DOWN.
Binchuan:
Binchuan:
When
When+5VSUS
+5VSUSsupply
supplySC1486
SC1486then
thenit’ll
it’ll 1.25V_PWRGD(P40)
generate +2_5VSUS,SMDDR_VTERM
generate +2_5VSUS,SMDDR_VTERM
and
and1.25V_PWRGD 2.5V_PWRGD. .
1.25V_PWRGD&&2.5V_PWRGD

+5VSUS
H 2.5V_PWRGD
+2_5VSUS
H
SMDDR_VTERM
H (1.25V)

SC1486
H

2003/2/20
1.25V_PWRGD JM3 Team
Binchuan:
Binchuan:
(C).
(C).When
When+5VSUS
+5VSUSsupply
MAX1715
MAX1715then
thenit’ll
supply
it’llgenerate
+1.5VSUS,+2.5VSUS
+1.5VSUS,+2.5VSUSand
generate
and
1715PWROK(P42)
1715SUSOK.
1715SUSOK.
+5VSUS

VTT(1.05V) H
+VCC1_2_GMCH(1.2V)

H
H

MAX1715

H 1715PWROK

2003/2/20 JM3 Team

Binchuan:
Binchuan:
SUSPWROK_5V
SUSPWROK_5Vas as+3/5VSUS
+3/5VSUS
isisok.
ok.Then
Then ititwill
willconnect
connectwith
AND-Gate
AND-Gatewith
AND with
withSUS_ON
SUS_ONthen
2.5V_PWRGD
with
then
to
SUSPWROK(P35)
AND with 2.5V_PWRGD to
produce
produceSUSPWROK.
SUSPWROK.

+3VRUN +3VSUS +3V_PWROK 28

C595 +3VSUS

1
R346
Keep Away from high speed buses
100K .1U +3VSUS
5 U28A 5 U28B
C601

2
1 6 3 4

.1U
C602
7WZ14 7WZ14 14 U30A
.1U 1
3
+3VSUS 2

+3VSUS 39 1715_1.5V_PWRGOOD 74AHC08

U30B
5 4
5 2 6
RUNPWROK 22,38,41,42
40 1.25V_PWRGD 2 4 5
4 1
21,23,39,44 RUN_ON 1 74AHC08
U27
U32 7SH08
7SH08
SUSPWROK 9,28
+3VSUS

H
U30C

SUSPWROK_5V
C613
40 2.5V_PWRGD
9
8 SUSPWROK
.047U H 10

41 SUSPWROK_5V
H 5
2
74AHC08

21,40,41 SUS_ON 1
4
H
U31
7SH08

2003/2/20 JM3 Team

Binchuan:
Binchuan:
RTCRST#
RTCRST#inactive
inactivetotoSUSCLK
running,SLP_S3#,SLP_S5#
running,SLP_S3#,SLP_S5#
SUSCLK
SLP_S3#,SLP_S5#(P09)
inactive.
inactive.

RSMRST#
SUSPWROK H

ICH4

SLP_S3#
Binchuan:
L?H SLP_S5# Binchuan:
RSMRST#
RSMRST#used usedfor
for
resetting the resume
resetting the resume
power
powerplane
planelogic.
logic.

ICH4 Binchuan:
Binchuan:
Inactive
InactiveSLP_S3#
SLP_S3#signal
signal
detected by MACALLEN(SIO).
detected by MACALLEN(SIO).
2003/2/20 JM3 Team
Logical
LogicalLevel
LevelL?
L?H.
H.
Binchuan:
Binchuan:
(D).
(D).SLP_S3#
SLP_S3#generate
RUN_ON
RUN_ONtototurn
Power
generate
turnon
onRUN
RUN RUN_ON(P21)
Powerplane.
plane.
P.S.:
P.S.:MACALLEN(SIO)
MACALLEN(SIO)
ignore
ignorethe
theSLP_S5#
SLP_S5#signal
signal

SLP_S3# H

MACALLEN(SIO)

H RUN_ON(D)

2003/2/20 JM3 Team

 MAX1715 1.8VRUN(P39)
+5VSUS
H
+1.8VRUN
+1.5VSUS H
RUN_ON
H
H
MAX1715

H 1715_1.5V_PWRGOOD
2003/2/20 JM3 Team
 RUN POWER(P44)
+5VALW 12OUT
+5VSUS
Q2
SI3456DV +5VRUN +5VRUN
6
5 4
H

1
2
R472 R481 1
C31
RUN_ON_5V# 100K 100K

H 4.7U_10V

3
2

2
H

1
RUN_ON_5V# 2 R1
C826 470K_NC
4700PF

1
3

2
21,23,35,39 RUN_ON
2

Q69
Q74
RHU002N06 +3V_SRC

Q56
+3VRUN +3VRUN

1
RHU002N06 6

RUN_ON H
5 4
2
1
HC763

4.7U_10V

3
SI3456DV

Binchuan:
Binchuan: Q67

RUN_ON
+1_5VSUS
SI3456DV +1_5VRUN
+1_5VRUN
RUN_ONturn
turnon
onallallRUN
RUNPOWER.
POWER. 6
5 4

RUN_ON
RUN_ONenable
enableasasbelow:
below:
2
1 HC819

1.1. +3VRUN,
+3VRUN,+5VRUN,
+5VRUN,+1_5VRUN,

3
4.7U_10V
+1_5VRUN,
+2_5VRUN(P44)
+2_5VRUN(P44)
2.2. +1_8VRUN
+1_8VRUN(P39)
(P39)
+2_5VSUS Q73 +2_5VRUN

3 1

NDS351AN
H +2_5VRUN
C822

2
1U_10V

2003/2/20 JM3 Team ID = 300mA(Max).

Rds= 1.0 Max @Vgs=10V.
Rds= 0.7 (Typ.)@Vgs=10V.
 Binchuan:
Binchuan:
RUNPWROK
RUNPWROKturns
turnson
onCPU
CPU
VCORE
VCOREPOWER.
POWER.
RUNPWROK(P35)
+3V_PWROK 28
+3VRUN +3VSUS
C595 +3VSUS

1
R346
Keep Away from high speed buses
100K .1U +3VSUS
5 U28A 5 U28B
H C601
2
1 6 3 4

.1U
C602
7WZ14 7WZ14 14 U30A
.1U 1
3
1715_1.5V_PWRGOOD
+3VSUS
H +3VSUS 2

74AHC08
RUNPWROK
39 1715_1.5V_PWRGOOD
U30B
5 4
5 2 6
40 1.25V_PWRGD
2 4
H
5
H RUNPWROK 22,38,41,42

H 1
4 1
74AHC08
21,23,39,44 RUN_ON

U32
H U27
7SH08
RUN_ON & 1.25V_PWRGD
7SH08
+3VSUS H SUSPWROK 9,28

SUSPWROK
U30C
C613 9
40 2.5V_PWRGD
8
10
.047U
74AHC08
5
2
41 SUSPWROK_5V
4
1
2003/2/20
21,40,41 SUS_ON JM3 Team
U31
7SH08
Binchuan:
Binchuan:
DBR#(Date
DBR#(DateBus
processor
BusReset)
Reset)isisused
usedonly
onlyin
in IMVP_PWRGD(P35)
processorsystems
systemswhere
whereno nodebug
debugport
port
isisimplemented
implementedon onsystem
systemboard.
board.(Can
(Can
be drive as system reset.)
be drive as system reset.)

+3VSUS
Remove one gate
+3VSUS

1
R339 C597

10K_NC

.047U
DBP# 2
R340 5
H
2,9 DBR#
1 2
H 2
4 12
U30D

0 1 11 IMVP_PWRGD
IMVP_PWRGD 5,9,12
+3VSUS 13
U26
74AHC08 IMVP_PWRGD
1
7SH08
R345

10K
1715PWROK
2

9,42 1715PWROK H

H
22 RESET_OUT#

RESET_OUT# Binchuan:
Binchuan:
2003/2/20 JM3 Team RESET_OUT#
RESET_OUT#comes
comes
from
fromMACALLEN(SIO).
MACALLEN(SIO).
Binchuan: Binchuan:
Binchuan: VTT_PWRGD#(P09,P1 Binchuan:
SLP_S3# Then VTT_PWRGD# causes CK-408 pin-28 active to
SLP_S3#&&SLP_S1_G#
SLP_S1_G#inactive
inactive 2) Then VTT_PWRGD# causes CK-408 pin-28 active to
transmit All system clocks.(STP_PCI#,STP_CPU# can let
generate
generateSLP_S1#
SLP_S1#inactive,
inactive,so
soitit transmit All system clocks.(STP_PCI#,STP_CPU# can let
system stop its Clock .)
causes CK-408 active. system stop its Clock .)
causes CK-408 active.

Binchuan:
R389 0_NC Binchuan:
STP_CLK#
STP_CLK#isn’t isn’tworking,
working,it’s
it’signored
+3VSUS +3VRUN
C652
.047U ignored
by its inner register of BIOS controlling
SLP_S1#_G
5
2
L R352
10K
by its inner register of BIOS controlling
from
fromSMBus.
SMBus.
4 SLP_S1# 12,14
SLP_S3# 1
VTT_PWRGD#
38 VTT_PWRGD#
H

3
U37 R351
7SH08 Q43 2
IMVP_PWRGD 5,9,35
10K
RHU002N06

1
IMVP_PWRGD#
PWR_DWN#

L
VTT_PWRGD#

STP_PCI#
STP_S1_G#

STP_CPU#
ICH4
CK-408
2003/2/20 JM3 Team
Binchuan:
Binchuan:
RUNPWROK?
RUNPWROK ?VHCORE
VHCORE VHCORE, DELAY_IMVP_PWRGD(P38)
?DELAY_IMVP_PWRGD.
?DELAY_IMVP_PWRGD.

RUNPWROK
VHCROE
H
H
VID ISL6217
PGOOD
VHCORE

Binchuan:
Binchuan:
ISL6217
ISL6217uses
usesTwo-Faces
Two-Faces
ofofVHCORE POWER
VHCORE POWER

2003/2/20 VTT_PWRGD# L
JM3 Team
DELAY_IMVP_PWRGD
Binchuan:
Binchuan:
(H).
(H).DELAY_IMVP_PWRGD
DELAY_IMVP_PWRGD
access
accessinto
intoICH4
ICH4will
willgenerate
PCIRST#(Low?
PCIRST#(Low?High)
generate
High)L?H
L?H PCIRST#(P7,9)

ICH4
L?H
PCIRST#

PCIRST#

Transition

DELAY_IMVP_PWRGD PWROK
H

2003/2/20 JM3 Team ICH4

Binchuan:
Binchuan: Binchuan:
Binchuan:
(I).
(I).PCIRST#
GMCH
PCIRST#access
accessinto
GMCHtotogenerate
generate
into CPURST#(P4,5) PCIRST#
PCIRST#inactive
occur
inactivewill
CPURST#
occur CPURST#
will

CPURST#.
CPURST#. inactive.
inactive.

GMCH

L?H
RSTIN# PCIRST#

Transition

L?H GMCH
CPURST#
CPURST#

2003/2/20 JM3 Team

Binchuan:
Binchuan:
After
AfterCPURST#
CPURST#inactive,
necessary
inactive,and
signals are all
andall
to
necessary signals are all to be
allother
be
other ADS#, Miscellanea(P2)
initiated
initiatedfrom
fromICH-4
ICH-4totoCPU
CPUthat
that
have correct configuration.
have correct configuration.

CENTRINO
L?H
RESET# CPURST#
… HHLL… .LHLHH.. Transition

ADS#
ADS#
CENTRINO

2003/2/20 JM3 Team

Binchuan:
Binchuan:
The
TheInner
InnerA0#~A2#
A0#~A2#value
value
The address of Entry-Point(P2)
isis000.
000.
FFFFFFF0
FFFFFFF0point
pointtotoBIOS
BIOS 0
Entry-Point.
Entry-Point. 1
1
1
1
1
1
1
1
1 CENTRINO
1
1
1
1
FFFFFFF0 1
1
1
1
1
1
1
1
1
1
Binchuan: 1
Binchuan: 1
1
AGTL+?
AGTL+ ? HUBLINK?PCI/LPC
HUBLINK?PCI/LPCtoto 1
point
pointBIOS
BIOSaddress
addressofofEntry
Entry 1
2003/2/20 JM3 Team
address.
address.
Binchuan:
Binchuan:
FLASH
FLASHneed needVCC1_PWROK#
totoreset,
Signal
and
VCC1_PWROK#
reset, and FLASHControl
FLASH Control Remainder action of Power
Signalfrom
fromMACALLEN(SIO).
MACALLEN(SIO).
on(P25) Binchuan:
Binchuan:
VCC1_PWROK#
VCC1_PWROK#inactive
inactivewhile
while
+3VALW assert.
+3VALW assert.
8Mbit (1M Byte),NO PLCC TYPE
SIO_FA[0..19] U6 SIO_FD[0..7]
22 SIO_FA[0..19] SIO_FA0 21 25 SIO_FD0 SIO_FD[0..7] 22
SIO_FA1 20 A0 D0 26 SIO_FD1
SIO_FA2 19 A1 D1 27 SIO_FD2
SIO_FA3 18 A2 D2 28 SIO_FD3
A3 D3
SIO_FA4
SIO_FA5
SIO_FA6
SIO_FA7
17
16
15
14
A4
A5
A6
D4
D5
D6
32
33
34
35
SIO_FD4
SIO_FD5
SIO_FD6
SIO_FD7
L?H
SIO_FA8 8 A7
A8
RESET# D7 R101 0
SIO_FA9 7 10 2 1 VCC1_PWROK VCC1_PWROK 22
SIO_FA10 36 A9 RESET#/NC 12
MACALLEN(SIO) Transition SIO_FA11 6 A10
A11
RY/BY#/NC
NC
29
SIO_FA12 5 38 T30 PAD
SIO_FA13
SIO_FA14
4
3
A12
A13
NC
NC
11 +3VALW VCC1_PWROK#
SIO_FA15 2 A14 31
SIO_FA16 1 A15 VCC 30
SIO_FA17 40 A16 VCC C159 C158
SIO_FA18
SIO_FA19
13
37
A17
A18
A19
FLASH 23
.1U .047U

FCS# 22 GND 39
22 FCS# CE# GND
22 FRD# FRD# 24
FWR# 9 OE#
22 FWR# WE#

ST MICRO M29W008AB1/SST39VF080

Binchuan:
Binchuan:
FLASH
FLASHControl
Control Binchuan:
Binchuan:
signals.
signals. FLASH
FLASHconnect
connectwith
withMACALLEN(SIO)
MACALLEN(SIO)by by
2003/2/20 JM3 Team X-BUS.
X-BUS.AndAndSIOSIOhas
hassome
sometranslated
translated
instructions
instructions to do its interpretation/translation.
to do its interpretation/ translation.
 Summary Sequence (1)
Test Purpose: To record the timing sequence for the power rails.

Overview of Procedure: Measure the timing of the power rails. The definition of these timing variables is
given in the power sequencing document attached below this table.
Timing Variable Time Comments
T1 280us Delay time form DC_IN+ to +RTCSRC
T2 -200us Delay time form +RTCSRC to +RTC_PWR5V
T3 -184us Delay time form +RTC_PWR5V to +RTC_PWR3_3V
T4 170us Delay time form +RTC_PWR3_3V to +3VALW
T5 -80us Delay time form +3VALW to +5VALW
T6 580us Delay time form +5VALW to POWER_SIO#
T7 -454.2ms Delay time form POWER_SIO# to SUS_ON
T8 -3.744us Delay time form SUS_ON to AUXEN
T9 520us Delay time form AUXEN to +3V_LAN
T10 -80us Delay time form +3V_LAN to 12OUT
T11 30us Delay time form 12OUT to +5VSUS
T12 10us Delay time form +5VSUS to +3V_SRC
T13 46.8ms Delay time form +3V_SRC to SUSPWROK_5V
T14 -46ms Delay time form SUSPWROK_5V to +1.5VSUS
T15 -880us Delay time form +1.5VSUS to 3VSUS_ON
T16 -80us Delay time form 3VSUS_ON to +3VSUS
T17 860us Delay time form +3VSUS to +2.5VSUS
T18 780us Delay time form +2.5VSUS to SMDDR_VREF
T19 420us Delay time form SMDDR_VREF to 2.5V_PWRGD
T20 157ms Delay time form 2.5V_PWRGD to LAN_PWROK
2003/2/20 JM3 Team
 Summary Sequence (2)
T21 -127ms Delay time form LAN_PEROK to SUSPWROK
T22 98ms Delay time form SUSPWROK to RUN_ON
T23 290us Delay time form RUN_ON to +2_5VRUN
T24 30us Delay time form +2.5VRUN to +3VRUN
T25 -57us Delay time form +3VRUN to +1.5VRUN
T26 110us Delay time form +1.5VRUN to +5VRUN
T27 256us Delay time form +5VRUN to SMDDR_VTERM
T28 1.372ms Delay time form SMDDR_VTERM to
1.25V_PWRGD
T29 -1.728ms Delay time form 1.25V_PWRGD to +1.8VRUN
T30 194us Delay time form +1.8VRUN to
1715_1.5V_PWRGOOD
T31 8.86ms Delay time form 1715_1.5V_PWRGOOD to
RUNPWROK
T32 15.12us Delay time form RUNPWROK to +12V
T33 940us Delay time form +12V to +VCC1_2V_MCH
T34 -70us Delay time form +VCC1_2V_MCH to CPU VTT
T35 410us Delay time form CPU VTT to 1715PWROK
T36 9.79ms Delay time form 1715PWROK to
VCORE_PWRGOOD_D

2003/2/20 JM3 Team

 Summary Sequence (3)
T37 9.2ms Delay time form VCORE_PWRGOOD_D to DBR#
and RESET_OUT#
T38 -10us Delay time form DBR# and RESET_OUT# to
IMVP_PWRGD
T39 -29.26ms Delay time form IMVP_PWRGD to VTT_PWRGD#

T40 9.16ms Delay time form VTT_PWRGD# to VHCORE

T41 28.88ms Delay time form CPU VCC CPRE to

DELAY_IMVP_PWRGD
T42 -7.16ms Delay time form DELAY_IMVP_PWRGD to CK408
OUT PUT
T43 8.32ms Delay time form CK408 OUT PUT to PCIRST#

T44 900us Delay time form PCIRST# to CPURST#

T45 -28.86ms Delay time form CPURST# to CPU VID

Section Owner:

Section Tester:

Time To Complete:

Date Finished: Dec/05/2002

2003/2/20 JM3 Team

 The Procedure of Power-UP(1)

2003/2/20 JM3 Team

 The Procedure of Power-UP(2)

2003/2/20 JM3 Team

 The Procedure of Power-UP(3)

2003/2/20 JM3 Team

 The Procedure of Power-UP(4)

2003/2/20 JM3 Team

 Appendix.
DAYTONA
AC/BATT
CONNECTOR PG 43 1.5V,1.8V
Banias CPU VR Vtt & CLOCKS RESET CKT
DC/DC VCC_1.2_MCH
RUN POWER 2.5V,1.25V
SW BATT
SELECTOR PG 36
PG 42 PG 38 PG 39 PG 41 PG 12 PG 35
PG 44 (Micro-FCPGA)
BATT PG 2,3 FAN & PAD & SWITCH &
CHARGER PG 37
LVDS Panel Connector THERMAL SCREW LED
PG 14 PG 28 PG 17 PG 27
DDR-SODIMM1 4X100MHZ
PG 10
Chrontel 7009 DVI
DVOB
Montara-GM TV EN-CONDE
DDR-SODIMM2 S-Video
266/200 MHZ DDR MGM PG 13 SEE I/O Board PG 1
PG 10
732 Micro-FCBGA
VGA
PG 4,5,6 PG 15
DDR-Termiation
PG 11 66(266)MHZ, 1.8V
HUB I/F 1 Ports
IDE1 - HDD USB
ATA 66/100
PG 16 33MHZ, 3.3V PCI DOCKING
Internal Media Bay ATA 66/100 CONNECTOR
CD-ROM ICH4-M
PG 16 USB
421 BGA PG 34
USB CONN.
USB X2 USB 2.0 MINI-PCI CARDBUS
PHY Wireless LAN
PG 26 USB PG 7,8,9 Bluetooth OZ6912
AC97 PG 31
PG 19 PG 18
Blue Tooth
CONN.
LPC
PG 25 SWITCH Magnetics RJ45
PG 31 PG 32 PG 32
AUDIO MDC
PG 29,30 PG 20 SIO(Macallen) USB
256 Pins LBGA DOCK LPC

S/PDIF to Audio RJ11 to Tip

DOCK Jacks DOCK X-Bus
Ring PG 21,22
PG 33 PG 29 PG 33 PG 20
QUANTA
PS/2 COMPUTER
2003/2/20 JM3 Team
Touchpad/ Flash
Title
Schematic Block Diagram1
IrDA Keyboard Parallel Serial Stick point Size Document Number Rev
PG 3 PG 22 PG 24 PG 23 PG 26 PG 25 JM3 1A

Date: 星期二, 二月11, 2003 Sheet 1 of 55