Computers and Electrical Engineering 68 (2018) 629–645

Contents lists available at ScienceDirect

Computers and Electrical Engineering

journal homepage: www.elsevier.com/locate/compeleceng

CMOS design of computational current-mode static and

dynamic functions based on analog translinear cellR
Mohammad Moradinezhad Maryan, Seyed Javad Azhari∗
Department of Electrical and Electronics Engineering, Iran University of Science and Technology (IUST), Tehran, Iran

a r t i c l e i n f o a b s t r a c t

Article history: In this paper, the systematic realizations of some low-power nonlinear current-mode com-
Received 10 August 2016 putational/configurable analog blocks (CABs) are presented. These CABs are based on a
Revised 23 February 2018
most demanded novel precise analysis and removal method of complete non-idealities
Accepted 23 February 2018
of CMOS transistors. The proposed CAB architecture consists of a novel MOS translinear
cell (MTC) that includes two overlapping up-down loops using MOS translinear principle
Keywords: (MTLP) in sub-threshold region. The proposed design with properly signal/bias injection
Current-mode scheme to MTC via NMOS-PMOS arrays is able to produce some current-mode nonlinear
Configurable analog block (CAB) static and dynamic functions. Those are as vector summation, cube/third power, true RMS
MOS translinear cell (MTC) to DC converter and first-order low-pass log-domain filter. The designed functions are sim-
Sub-threshold ulated by HSPICE simulator in TSMC 0.18 μm (level-49 parameters) CMOS technology. Pre
MOS translinear principle (MTLP)
and post-layout simulation results both plus Monte Carlo analysis are compared with other
Analog signal processing
artworks that verified the functionality, flexibility and superiority of the proposed CABs.
© 2018 Elsevier Ltd. All rights reserved.

1. Introduction

Analog computational circuits are very useful building blocks finding many applications in analog signal processing
(ASP) to implement some important mathematical functions, fuzzy systems, neural networks etc. The circuit’s simplicity,
area efficiency, operation speed, lower supply voltage and power consumption are their most important characteristics.
Current-mode and voltage-mode are two approaches to design analog integrated circuits. Compared to voltage-mode cir-
cuits, current-mode ones have been receiving considerable attentions due to their potential advantages such as inherently
wide bandwidth (BW), higher slew-rate, more linearity, wider dynamic range, simple circuitry and lower power consumption
[1].
In recent years, a considerable increased interest is observed to design flexible circuits and configurable analog blocks
(CABs). This interest is mainly towards performing more various static and dynamic analog computation functions by mod-
ifying the input signals easier [2–4] or via programming and reconfiguration [5–8] of few basic cells. These circuits are
capable to implement such various nonlinear functions as multiplier/divider, squarer, square-rooter, vector summation, RMS
to DC converter, filter, etc. Today such flexible circuits and CABs are the most efficient blocks for ASP and nonlinear com-
putation. Although the low-voltage low-power (LV-LP) gift of the current-mode processing is well acknowledged but the
thirst is stronger to be quenched. That is basically due to demands for extended battery life in portable applications, bio-

R
Reviews processed and recommended for publication to the Editor-in-Chief by Associate Editor Dr. M. Daneshtalab.
∗
Corresponding author.
E-mail address: azhari@iust.ac.ir (S.J. Azhari).

https://doi.org/10.1016/j.compeleceng.2018.02.037
0045-7906/© 2018 Elsevier Ltd. All rights reserved.
630 M.M. Maryan, S.J. Azhari / Computers and Electrical Engineering 68 (2018) 629–645

Fig. 1. Basic translinear loops (a) stacked topology (b) up-down topology.

instruments and the scaling down trend of modern technologies dictate the certain use of still lower voltage and power
circuits in the next few years. Using the MOS transistors in sub-threshold is also a powerful plan to grant this wish [9].
The versatile building blocks for implementing analog functional circuits have been proposed in [2]. High BW has been
achieved; still, supply voltage, power consumption and linearity have not been improved. The proposed work in [3] is based
on MTL principle in sub-threshold region [10] that although suffers from low BW and linearity but generally is best for LV-
LP cases. Floating-gate MOS (FGMOS) transistors are other devices to build LV-LP basic cells for implementing the various
analog functions [4]. However they need special technology of double poly that is more expensive and complicated than
standard CMOS process (single poly). Meanwhile the resulted circuits are more complex and unable to process DC signals.
In [5] the logarithmic and exponential cells are the basic blocks for realization of the proposed CAB in sub-threshold, but
suffer from high nonlinearity and distortion. Besides it cannot implement the dynamic functions. Multiple input translinear
elements (MITEs) [6] and reconfigurable translinear cell (RTC) [7] based-CABs are capable to implement the static and dy-
namic current-mode functions. Nevertheless, the work [6] suffers from the mismatches between numerous MITEs, structure
complexity and expensive technology problems even more than [4] since uses multiple input FGMOS transistors. And CAB
architecture of [7] can’t implement any function alone so that needs some 4 and 8 numbers of its proposed CAB to realize
one quadrant multiplication and vector summation, respectively. The MOS translinear (MTL) principle (MTLP) in saturation
region [11] is used in [8] to implement the basic building cell and nonlinear analog computation. However, working in
saturation region causes cell to suffer from high supply voltage and power consumption, results in unsuitability for LV-LP
systems.
Vector summation, third power, true RMS to DC converter and first-order low-pass log-domain filter are computational
current-mode functions that are presented in this paper. These functions have been realized with a LV-LP, high-speed simple
structure CAB that is almost free from the problems so far stated in the introduction. A novel MOS translinear cell (MTC) is
the core of the proposed CAB which includes two overlapping up-down loops using MTL principle in sub-threshold region.
This paper is organized as follows; in Section 2 the description of the MTC and proposed CAB architecture are given. The
examples of the static and dynamic functions, pre and post-layout simulations and Monte Carlo analysis will be reported in
Section 3. The second order effects (non-idealities) of the proposed MTC and the current mirrors mismatch effects will be
discussed in Section 4 and finally, Section 5 concludes the paper.

2. Proposed CAB description

2.1. MTL principle in sub-threshold region

Fig. 1 shows the basic four transistors translinear (TL) loops. The type depicted in Fig. 1(a) is called stacked topology and
the one of Fig. 1(b) is entitled the up-down topology. The up-down topology is more frequently preferred due to featuring
lower supply voltage requirement and free from body effect non-ideality problem [1]. However, applying MTL principle on
either loops of Fig. 1 assuming work in sub-threshold, directly gives the current multiplication relation as [10]:
I1 .I2 = I3 .I4 (1)
It is clear that multiplication and division of several unipolar currents can be easily performed by using the MTL principle
in sub-threshold region. Moreover, Eq. (1) is independent of the process and temperature variations [12].

2.2. The novel MTC

Fig. 2 shows the proposed novel MTC that consists of six matched NMOS transistors (M1 −M6 ) and Mb . These transistors
have been biased in sub-threshold region and form the two overlapping up-down TL loops as one novelty of this MTC. As its
another novelty the transistor Mb forms the negative feedback loop consisting of M1 and Mb transistors to both reduce the
impedance of drain node of M1 and provide the required bias of M1 . The M1 and M2 transistors constitute the overlapped
part of two TL loops of this MTC that leads to a less power consumption and distortion. As one of the powerful novel idea of
this work, this plan reduced the size and power consumption by 25%. More importantly it greatly increases the similarity of
 M.M. Maryan, S.J. Azhari / Computers and Electrical Engineering 68 (2018) 629–645 631

Fig. 2. Proposed MOS translinear cell (MTC).

Fig. 3. The complete block diagram of the proposed CAB architecture.

the two TL loops that proportionally reduces the distortion and nonlinearity of the novel MTC. Applying the MTL principle
in sub-threshold to the first loop that consists of M1 to M4 , gives:
I1 .I4 = I2 .I3 (2)
In the same way, the second TL loop consisting of the M1 , M2 , M5 and M6 transistors, gives:
I1 .I6 = I2 .I5 (3)
Now, with properly usage of the Eqs. (2) and (3) and suitable signal/bias injection scheme, one can easily implement the
various current-mode nonlinear functions.

2.3. Proposed CAB architecture

The complete block diagram of the proposed CAB architecture is illustrated in Fig. 3. It consists of the proposed novel
MTC, two local switch networks and NMOS-PMOS arrays. NMOS-PMOS arrays provide the signal and bias currents for MTC
632 M.M. Maryan, S.J. Azhari / Computers and Electrical Engineering 68 (2018) 629–645

Table 1
Transistors aspect ratios of the proposed CAB.

M1-6 Mb PMOS array NMOS array

W (μm) 0.3 3.6 0.4 2.5

L (μm) 1 0.2 0.5 1

Fig. 4. Complete schematic of the proposed CAB based-current-mode vector summation circuit.

and allow the proposed CAB to implement more functions. One of the most important features of the proposed CAB is that
some recurrent paths have been anticipated in the architecture, which is very useful in realization of some more operations.
In brief, besides the novel MTC, as the dominant novelties of this work that impress the entire work are; (a) properly
signal/bias injection scheme, (b) deliberately reconfiguration and design of each part. Innovatively thoughtful application of
these two plans caused the creation of such current-mode nonlinear functions as vector summation, third power, true RMS
to DC converter and first-order low-pass log-domain filter.

3. Examples of static and dynamic nonlinear functions executers using the proposed CAB

Some computational processors based on the proposed CAB have been simulated in 0.18 μm TSMC CMOS technology.
Pre and post-layout simulations of these functions are carried out. In all simulations, supply voltage (VDD ) and bias current
(IB ) are 1 v and 100 nA, respectively. Also, Monte Carlo analysis with 5% variation of the channel width and length of
all transistors are performed for important parameters, like –3 dB BW. First, some static functions were examined including
circuits for vector summation and cube power. Next, dynamic functions were experienced counting true RMS to DC converter
and first-order low-pass log-domain filter. The aspect ratios of the transistors that used in CAB architecture are listed in
Table 1. In order to minimize the non-idealities (second order) effects, some used lengths are chosen large enough compared
to the minimum length offered by the process.

3.1. Static functions

Vector summation has found applications in a wide variety of instrumentation, communication, neural network and dis-
play systems. Some vector summation circuits have been implemented in bipolar technology and some more in CMOS tech-
nology [13–14]. Fig. 4 shows the proposed CAB based-current-mode vector summation circuit. One of the most important
features of the proposed design is utilization of only one TL loop without interference of the other one. In order to imple-
ment this circuit; six transistors of the PMOS array and properly current signal injection are used. Using current signals that
is depicted in Fig. 4 at Eq. (2), it results:
(IOUT − Iy ).(IOUT + Iy ) = Ix 2 (4)

IOUT 2 −
Iy 2 = Ix 2
(5)
IOUT = Ix 2 + Iy 2
Eq. (5) denotes the vector summation operation with two inputs (IX and IY ). In order to complete the TL loop, the
source terminals of M3 and M4 are connected to Vb voltage that is 100 mV. Drain and source terminals of M5 and M6
are connected to ground, to mask their effects on first TL loop and circuit performance. The transient response has been
simulated by applying two triangular waves with 100 nA amplitude, 1 and 5 kHz frequencies to the input currents IX and IY ,
respectively that are shown in Fig. 5. Maximum linearity error of transient response for pre and post-layout simulations are
 M.M. Maryan, S.J. Azhari / Computers and Electrical Engineering 68 (2018) 629–645 633

Fig. 5. Transient response of the proposed vector summation circuit, (a) output current (b) linearity errors.

Fig. 6. Monte Carlo analysis of the –3 dB BW for the proposed vector summation circuit (a) pre-layout (b) post-layout.

Fig. 7. Behavior of frequency response respect to (a) temperature (b) supply voltage variations.

2%. To evaluate the –3 dB BW, an AC input current IY with 100 nA dc component and a DC current IX = 100 nA, are used.
Fig. 6(a) and (b) show the Monte Carlo analysis of –3 dB BW for pre and post-layout cases in which the mean values of 100
repetitions are 111.15 and 107 MHz, respectively.
The robustness of the circuit respect to temperature and supply voltage variations are also studied that are shown in
Fig. 7(a) and (b), respectively. The variations values are of –25 °C to 100 °C with 25 °C steps for temperature, and 0.9–
1.1 V in 50 mV steps for supply voltage. Stability of the proposed vector summation circuit respect to PVT variations is
634 M.M. Maryan, S.J. Azhari / Computers and Electrical Engineering 68 (2018) 629–645

Table 2
Comparison between the proposed vector summation and other publications.

Ref. Technology Supply Power Input range Bandwidth Linearity Num. of transistor/ Sim/
(μm) voltage(V) (μW) (nA) (MHz) error(%) complexity meas

[7] 0.35 3.3 733 5 μA 20 NA∗ >90 Meas.

[14] 3 ±5 NA ±2V 1 <1 22 Sim.
Proposed 0.18 1 0.72 100 111.15 2 11 Pre layout Sim + MC#
Proposed 0.18 1 0.72 100 107 2 11 Post layout Sim + MC
∗
Not Available.
#
Mont Carlo.

Fig. 8. Complete schematic of the proposed CAB based-current-mode cube/third power circuit.

inherited from MTL principle nature in sub-threshold region [12]. A comparison between the proposed circuit and other
vector summation circuits is presented in Table 2. Lower supply voltage and power dissipation, better linearity, wider BW
and simpler structure are the most important features of the proposed circuit respect to previous artworks. As the strong
reason that greatly motivated the current authors to work on this topic is the scarcity, thus uniqueness of sub-threshold
LV/LP small/simple CABs of this type so that could not find even one counterpart for the current-mode cube/third power
CAB and those two ones; [7,14] compared with the proposed vector summation CAB in Table 2. To add, Liu and Chang [14] is
a 22 years old voltage-mode high voltage circuit and Fernandez et al. [7] is a large sized complex one.
The proposed CAB based-current-mode cube/third power circuit is depicted in Fig. 8. To implement this circuit, one
NMOS and five PMOS transistors arrays, respectively and suitable current signal/bias injection are used. Transistor Mn1 that
forms a negative feedback from drain node of transistor M5 plays the same role as that of transistor Mb . Using current
signals illustrated in Fig. 8 at Eq. (2), it gives:

2
IIN
IO1 = (6)
IB

Then, applying the shown signals to second TL loop, it results:

3
IIN
IOUT = (7)
IB 2

It can be seen from Eq. (7) that the proposed circuit implements the current cube power operation. DC transfer char-
acteristics for IB = 50 nA, 100 nA and 150 nA is depicted in Fig. 9. Maximum linearity error of DC transfer characteristics
for the case that IB =100 nA and for pre and post-layout simulations are 1.3%. In this case, maximum power consumption
is 850 nW. Fig. 10(a) and (b) show the Monte Carlo analysis of −3 dB BW with 100 iterations. In this case, the proposed
circuit has been simulated through the utilization of an AC input current IIN with 100 nA dc component. Fig. 10 show the
mean values of the −3 dB BW for pre and post-layout cases as 46 and 45 MHz, respectively. Insensitivity of the circuit versus
temperature and supply voltage variations (with same values and steps as Fig. 7) are also studied and shown in Fig. 11(a)
and (b). However, as is mentioned above as the uniqueness of this CAB, the current authors couldn’t find any matching CAB
to compare.
 M.M. Maryan, S.J. Azhari / Computers and Electrical Engineering 68 (2018) 629–645 635

Fig. 9. DC transfer characteristics of the proposed cube power for IB = 50 nA, 100 nA and 150 nA.

Fig. 10. Monte Carlo analysis of the –3 dB BW for the proposed cube/third power circuit (a) pre-layout (b) post-layout.

3.2. Dynamic functions

True RMS to DC converter as an electronic measuring circuit is used for estimation of the average energy content in an
electronic signal. The true RMS to DC converter, which directly measures the RMS value, is a very attractive electronic pro-
cessor. It is widely used to measure the AC power of electronic blocks and systems especially the biomedical and instrumen-
tation ones. Depending on the circuit implementation, RMS to DC converters can be divided into explicit (direct) [15–16] and
implicit (indirect) [16–19] computation schemes. Explicit computation technique uses a sequence of squaring, averaging, and
then square-rooting circuits; the last one computes the RMS value. The implicit computation scheme uses indirect method
to perform the conversion as is shown in Fig. 12. The proposed CAB based- novel two-quadrant squarer/divider circuit is
depicted in Fig. 13. It shows that five transistors of each NMOS and PMOS arrays are needed to implement this function.
Moreover, IIN /2 as the required current signal for this function is easily provided by class AB current mirrors with 0.5 ratio.
In Fig. 13, IIN + and IIN − are defined as follows:

1 1
IIN + = (IB + IIN ), IIN − = (IB − IIN ) (8)
2 2

Applying MTL principle to first TL loop of Fig. 13 (M1 −M4 ), it gives:

IIN + .I4 = IIN − .I3 (9)

636 M.M. Maryan, S.J. Azhari / Computers and Electrical Engineering 68 (2018) 629–645

Fig. 11. Behavior of frequency response respect to (a) temperature (b) supply voltage variations.

Fig. 12. Block diagram of implicit scheme current-mode RMS to DC converter.

Fig. 13. Proposed CAB based-current-mode two-quadrant squarer/divider circuit.

Since I3 + I4 = IIN + and IIN + + IIN − = IB , thus for I3 and I4 currents it yields:
2
(IIN + )
I3 = (10-a)
IB
− +
IIN IIN
I4 = (10-b)
IB
Repeating the above process for second TL loop (I5 + I6 = IIN − ), it results:
+ −
IIN IIN
I5 = (11-a)
IB
− 2
(IIN )
I6 = (11-b)
IB
Then the output current of the proposed squarer/divider circuit, can be written as:
IIN 2
ISQ = ISQ + − ISQ − = I3 + I6 − I4 − I5 = (12)
IB
 M.M. Maryan, S.J. Azhari / Computers and Electrical Engineering 68 (2018) 629–645 637

Fig. 14. Complete schematic of the proposed current-mode RMS to DC circuit based on implicit computation scheme.

Table 3
Comparison between the proposed RMS to DC circuit and other reported works.

Ref. Technology Supply voltage Power consumption Num. of transistors Operation Sim/
(μm) (V) (μW) (Complexity) region meas

[15] 0.35 1.5 <1 22 Sub-threshold Simulation

[17] 0.35 0.9 <1.5 7 + 6 FGMOS Sub-threshold Simulation
[18] 0.18 1 <3 43 Sub-threshold Simulation
[19] 0.35 1.5 0.12 nW 20 Sub-threshold Simulation
Proposed work 0.18 1 <1 19 Sub-threshold Simulation

Complete schematic of the proposed current-mode RMS to DC converter circuit based on the implicit computation
scheme is illustrated in Fig. 14. It clearly displays the transistor-level structure of proposed RMS to DC converter being dif-
ferent from other ones [16–19] as follows. The recurrent paths scheme is used to equalize the averaging and bias currents.
Also to support the RMS to DC circuit to correctly operate the proposed CAB-based novel two-quadrant squarer/divider cir-
cuit of Fig. 13 is used to square the input signal. The squaring current injected to simple first-order low-pass filter circuit
consists of grounded capacitor CAVG and diode-connected transistor Mn1 [18]. This filter integrates the injected current thus
computes the average of input signal (IIN 2 /I ) as follows:
B

1
IAVG = 2
IIN (t )dt (13)
τ IB
where, τ = CAVE /gmn1 is the filter’s time constant and gmn1 is transconductance of the Mn1 , and transistors Mn1 and Mn5
have two times aspect ratios respect to other transistors in NMOS array. In order to give a good performance for the required
frequency range, the value of capacitor CAVG should be chosen such that [18]:
5IRMS−MAX
CAVG ≥ (14)
ηVT 2π fmin
where fmin is the lower end of the frequency range, IRMS-MAX is the higher end of the converter output current range, η is
sub-threshold exponential slope factor and VT is thermal voltage. Bias and averaging currents (IB = IAVG ) are equalized using
recurrent paths. So, from Eq. (13), it results:
 
1 2 (t )dt
IOUT = IRMS = IIN (15)
τ
Eq. (15) obviously indicates that the output current is the root-mean-square (RMS) value of the input current IIN . To
simulate this circuit, external capacitor CAVG was chosen as 20 nF. Fig. 15(a) and (b) show steady-state time response of the
new RMS to DC converter for 230 nAp-p amplitude and 1 kHz frequency for sinusoidal and triangular waves, respectively.
In Table 3, as other significant merits, the proposed design proves lower supply voltage, power consumption and number of
transistors (complexity and size) compared to earlier reported artworks.
638 M.M. Maryan, S.J. Azhari / Computers and Electrical Engineering 68 (2018) 629–645

Fig. 15. Steady-state time response of the proposed RMS to DC converter circuit for (a) sinusoidal (b) triangular waves.

Fig. 16. The method for implementation of class A log-domain filter in [22].

Electronic filters are also very useful processors that actually perform unique functions in the field of either passing or
rejection of electronic signals [20–25]. Fig. 16 shows a method for implementation of class (A) log-domain filter by FGMOSTs
reported in [22]. The transfer function of a first-order low-pass filter is usually as:
IOUT (s ) K
H (s ) = = (16)
Iin (s ) 1 + τs
where K is the DC gain and ω − 3dB = 1/τ . Eq. (16) can be modified in time domain as a linear differential equation:
.
τ IOUT + IOUT = KIin (17)

Assuming τ = C/g (C and g are capacitance and transconductance values, respectively) and the output current IOUT to be
nonlinearly related to a certain voltage VCAP as:

IOUT = IB .eαVCAP (18)

IB and α have Ampere and 1/Volt dimensions, respectively. Now Eq. (17) can be rewritten as follows:
. α IOUT
CVCAP . + IOUT = KIin (19)
g
IB1 and IB2 are constant currents that are capable to tune the cut-off frequency and DC gain of the filter and are defined
as:
Kg g
IB1 = (A ), IB2 = (A ) (20)
α α
Combining Eq. (20) with Eq. (19) and rewrite the result gives:
. IB1 .Iin
CVCAP = − IB2 (21)
IOUT
Eq. (21) describes the transfer function of a low-pass filter (KCL in node A) with DC gain and cut-off frequency of:
IB1 α IB2
K= , ω−3dB = (22)
IB2 C
 M.M. Maryan, S.J. Azhari / Computers and Electrical Engineering 68 (2018) 629–645 639

Fig. 17. The proposed current-mode class A first-order low-pass log-domain filter.

In other hand, the I–V characteristic of a MOS transistor operating in sub-threshold region is as [1]:
VGS

IDS = ID0 e ηVT (23)

where VGS and VT are gate to source and thermal voltages, respectively. ID0 is specific current that related to aspect ratio and
process parameters. Comparing Eq. (23) with Eq. (18) implies that if IB = ID0 , α = 1/ηVT and VCAP = VGS , the filter output
current IOUT of Eq. (18) becomes the drain current of a MOS transistor in sub-threshold region as is shown in Eq. (23).
Thus it is proved that the circuit shown in Fig. 16 is able to implement the class A first-order low-pass log-domain filter.
The proposed transistor level filter is shown in Fig. 17. FGMOSTs used in [22] suffer from what explained in introduction
plus large sizes. Thus, to get free from all those drawbacks, this novel filter is realized by two standard NMOS transistor
arrays and four PMOS ones. Layout design pictures of all of the designed computational blocks in this work are shown in
Fig. 18(a)–(d). The corresponding chip areas (without pads) are 506, 506, 884 and 400 μm2 . Favorably, the proposed circuits
don’t suffer from the body effect, because the MTC utilizes the up-down topology, PMOS transistors have separate wells and
source terminals of the NMOS transistors are connected to ground (VBS = 0).
To simulate the proposed filter, voltage Vb =50 mV and capacitor C = 100 pF, are used. The simulated frequency response
of the filter for bias currents IB1 = IB2 ranging from 1 to 600 nA is illustrated in Fig. 19. The corner frequency ranging from
almost 55 to 15,250 Hz was observed. Total harmonic distortion (THD) parameter is evaluated by applying the sinusoidal sig-
nal with 10 kHz frequency and amplitude ranging from 20 to 200 nA for IIN and 200 nA DC current for IB1 and IB2. Fig. 20(a)
shows the THD curves for pre and post-layout simulations. Also, to have fairly comparison with the reported work [22], the
THD parameter is given in the same frequency (100 Hz) of Fig. 20(b). The static and maximum power dissipation for the
case of IB1 = IB2 = 100 nA are 545 and 840 nW, respectively. A comparison between the performance of the previous filters
and the proposed filter is presented in Table 4. The reported works in [20,21,23, and 24] have used current conveyors (CCIIs)
and current differencing buffered amplifier (CDBA) for the proposed filters, result in very complex and large structures thus
are not included in the comparison table.

3-3. Brief analysis and comparison

Inspection of the available current-mode CABs in CMOS technology, show that each structure suffers from one or more
of the following disadvantages:

1. unsuitable for LV-LP systems (high supply voltage and power consumption) [2, 7–8]
2. low BW [3, 5–6]
3. poor linearity [2, 5]
4. needing special technology (more cost) [4, 6]
5. unable to implement the dynamic functions [2–3, 5]
6. high complexity [6–7]

In contrast with previously proposed artworks, the processors introduced in present work implemented by the proposed
CAB have such superiorities as:

1. suitable for LV-LP systems (VDD ≤1 V, power<1 μW)

2. high BW
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M.M. Maryan, S.J. Azhari / Computers and Electrical Engineering 68 (2018) 629–645
Table 4
A comparison between the performance of the proposed filter and other works.

Ref. Technology (μm) Supply voltage (V) Power consumption (μW) Frequency range (KHz) THD 100 Hz (%) Num. of transistors /complexity Sim/meas

[22] 0.8 1 0.84 (IB1 = IB2 =50 nA) 1.2–19 0.45 (IIN = 240 nA) 20 + 8 FGMOS Simulation
[22] 0.8 1.6 6.3 (IB1 = IB2 =280 nA) 0.25–4 −46 dB (IIN =1 ??A) 20 + 8 FGMOS Meas.
[25] 0.18 1 480 70 MHz–131 MHz 3 27 Post sim.
Proposed work 0.18 1 0.84 (IB1 = IB2 =100 nA) 0.055–15.25 0.29 (IIN = 200 nA) 11 Simulation
Proposed work 0.18 1 0.84 (IB1 = IB2 =100 nA) 0.055–15.25 0.35 (IIN = 200 nA) 11 Post sim.
 M.M. Maryan, S.J. Azhari / Computers and Electrical Engineering 68 (2018) 629–645 641

Fig. 18. Layout design of the proposed functions (a) vector summation (b) cube power (c) RMS to DC converter (d) filter.

Fig. 19. The frequency response of the proposed filter.

3. good linearity and robustness despite of application of 5% non-idealities in Monte Carlo analyses
4. implemented in standard CMOS technology
5. able to implement both static and dynamic functions
6. low complexity
642 M.M. Maryan, S.J. Azhari / Computers and Electrical Engineering 68 (2018) 629–645

Fig. 20. THD parameter, (a) 10 kHz (b) 100 Hz.

4. Analysis and compensation of second order effects (non-idealities)

The authors humbly evaluate this part of the work as its best theoretical and most helpful practical part. It starts with a
precise deep and comprehensive analysis of both inter-die/global and intra-die/local technological variations that concludes
with some helpful practical key guide directions to optimally compensate those non-idealities and provide close to ideal
achievements, as follows [10, 12]:

4.1. Second order effects (non-idealities) of the MTC

The I–V relation of an NMOS transistor in sub-threshold region is [1, 12]:

VGS −VTH
 −VDS

IDS = Is .e ηVT
1−e VT
(24)

while VGS, VDS , VTH and VT are gate to source, drain to source, threshold and thermal voltages, respectively. Also, IS is specific
current and η is sub-threshold exponential slope factor. Since the error caused by variation of VDS is fairly low, thus is
ignored and the errors in the proposed MTC can be mainly produced by the process dependent mismatches in IDS . This one
itself originates from parameter IS and VTH mismatches, while those are shown by (1 + ࢞IS )IS and (1 + ࢞VTH )VTH , where IS
and VTH are a mean value, ࢞IS and ࢞VTH are a mismatch percentage of IS and VTH , respectively. Thus IDS can be written as:
VGS i −(1+VT Hi )VT H

IDSi = (1 + ISi )IS e ηVT

(25)
Note that ࢞VTHi represents the mismatch effect of VTH and not the body effect error. Therefore, VGS can be extracted
from Eq. (25) as:
IDSi
VGSi = ηVT Ln( ) + (1 + VT Hi )VT H (26)
(1 + ISi )IS
Applying Eq. (26) on to the first TL loop of MTC and doing some manipulation, results:
I1 .I4 = λ1 I2 .I3 (27)
While λ1 is defined as:
(1 + IS1 )(1 + IS4 ) (VTH2 +VTH3 −ηVVTTH1 −VTH4 ).VTH
λ1 = .e (28)
(1 + IS2 )(1 + IS3 )
Similarly, the second TL loop yields:
I1 .I6 = λ2 I2 .I5 (29)
Also, λ2 is defined as:
(1 + IS1 )(1 + IS6 ) (VTH2 +VTH5 −ηVVTTH1 −VTH6 ).VTH
λ2 = .e (30)
(1 + IS2 )(1 + IS5 )
4.2. Second order (non-idealities) effects of the cube power circuit

To evaluate the second order effects of the proposed cube power, Eqs. (27) and (29) should be applied on both TL loops
of the circuit, it gives:
3
 IIN
IOUT = λ1 λ2 . (31)
IB 2
 M.M. Maryan, S.J. Azhari / Computers and Electrical Engineering 68 (2018) 629–645 643

Comparing Eqs. (7) and (31) implies that the non-ideality errors produce a gain error term. While with properly designing
and good layout drawing, λ1 and λ2 can approach to one, thus most favorably, error terms could be removed and make
Eq. (31) to approach towards the errorless ideal Eq. (7).

4.3. Second order effects (non-idealities) of the RMS to DC converter circuit

To properly evaluate the non-ideality errors of the proposed RMS to DC converter, Eqs. (27) and (29) should be applied
on both TL loops of the circuit. Then to avoid such bothersome time taking (yet) trivial computation, assume λ1 = λ2 = λ,
causes (with some slight manipulation) the Eq. (12) to become modified to:
 
(1 + λ ) IB .IIN .(1 − λ )
I = IIN 2
. + (32)
SQ
IB .(1 + λ ) + IIN .(1 − λ ) IB .(1 + λ ) + IIN .(1 − λ )
Comparing Eqs. (12) and (32) implies that the second order effects plus technology mismatches altogether (all non-
ideality errors together) produce a gain error term (the coefficient in [] sign in Eq. (32)) that depends on IIN and IB signals
and a DC offset term (last term of Eq. (32)). However, the squaring current of I’ SQ is injected to filter to be integrated in
time domain. The filter thus computes the average of input signal as follows:
  
 1 (1 + λ ) IB . (1−τ λ) . IIN (t )dt
IAVG = IIN 2 (t )dt. + (33)
τ IB .(1 + λ ) + (1−τ λ) . IIN (t )dt IB .(1 + λ ) + (1−τ λ) . IIN (t )dt

Suppose that 1/τ ʃ IIN (t)dt = IA , IB = I’ AVG and with some manipulation it yields:
 
 1 2 (t )dt = I
IRMS = IIN (34)
τ RMS

It is obvious that all non-ideality errors are skillfully compensated together.

4.4. Current mirrors mismatch errors

The mismatch in current mirrors (that all together form the major part of the proposed CAB) is one of the main reasons
of gain and DC offset errors in the proposed circuits. Assume ε ij represent the mismatch effects between Mi and Mj transis-
tors (Mi and Mj form a simple current mirror). As a result, output current of a unity gain current mirror is IOUT =IIN .(1+ε ij ).
As the worst case, let’s assume this error is regarded for all current mirrors of the proposed RMS to DC converter circuit,
thus summed those up together, then going through some long computation and ignore the terms of ε ij∗ ε xy and ε ij 2 as
infinitesimal values, results:

 = α. IIN 2
ISQ + β IIN (35)
IB
where α and β are defined as follows:
1
α= (36)
1 + 2εn1 p1 + ε p1 p3 + ε p1 p2
εn1n3 − εn1n4 + ε p1 p3 − ε p1 p2
β= (37)
2(1 + 2εn1 p1 + ε p1 p3 + ε p1 p2 )
Then the average of squaring signal becomes:
 
 α β
IAVG = . IIN 2 (t )dt + . IIN (t )dt (38)
τ IB τ
Again using the same abovementioned assumption of 1/τ ʃ IIN (t)dt = IA and IB = I’ AVG , and solving quadratic equation of
Eq. (38) for I’ AVG leads to:
 
 1 2 1 β 
IAVG = β + 4α . IIN 2 (t )dt + .IA = IRMS (39)
2 τ 2

1  β

IRMS = β 2 + 4α .IRMS + .IA (40)
2 2
It can be deduced from Eq. (40) that the current mirrors mismatch errors also produce a gain error and a DC offset term.
It is clear from Eq. (40) that with using properly aspect ratios for transistors of current mirrors, ε ij s approach to zero (α and
β approach to one and zero, respectively) that converts Eq. (40) to pure Eq. (15). Note that the effects of non-idealities have
been evaluated via Monte Carlo simulations in Section 3.
644 M.M. Maryan, S.J. Azhari / Computers and Electrical Engineering 68 (2018) 629–645

5. Conclusion

Field programmable analog arrays (FPAAs) are type of reconfigurable integrated circuits capable of realizing a wide va-
riety of analog functions. The CABs are the basic building blocks in realization of FPAAs. A systematic realization of low-
power, high-speed static and dynamic nonlinear functions based on computational current-mode CAB in sub-threshold re-
gion, was presented. The proposed CAB architecture consists of a MTC, two local switch networks and NMOS-PMOS arrays.
The proposed design with properly signal/bias injection scheme to MTC via NMOS-PMOS arrays was able to produce some
current-mode nonlinear functions such as vector summation, cube/third power, true RMS to DC converter, first-order low-
pass log-domain filter and much other. Basically, the proposed CAB architecture consisting NMOS and PMOS arrays is easily
capable to implement the addition, subtraction and averaging of input current signals. Besides, using the proposed CAB in
FPAA architecture facilitates to implement any static and dynamic current-mode nonlinear functions. Most favorably as an
outstanding novelty, the non-idealities errors of the CMOS devices, main computational CAB and some proposed circuits are
precisely analyzed and compensated that caused high non-idealities robust structures despite the application of 5% non-
idealities in Monte Carlo simulations. Thus, this analysis and included compensation techniques will encourage interested
researchers to employ it as a profitable practical guide.

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 M.M. Maryan, S.J. Azhari / Computers and Electrical Engineering 68 (2018) 629–645 645

Mohammad Moradinezhad Maryan was born in Talesh, Iran, in 1990. He received B.Sc. and M.Sc. degrees in electronic engineering from Iran University of
Science and Technology (IUST), Iran, in 2013 and 2016, respectively. He is currently a Ph.D student of IUST and his research interests are analog integrated
circuit design especially in current-mode field.

Seyed Javad Azhari Since 2001, he has been an Associate Professor of electronic engineering with the Electrical Engineering Faculty and the Electronic
Research Center, IUST where in 2016 has been promoted to professor of electronic engineering. His research interests include circuit and system design,
particularly current-mode field, electronic instrumentation and measurement, semiconductor devices, and sensor technology.