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# (FOR IV SEMESTER BE E&C)

## HDL LAB – 10ECL48

(AS PER VTU SYLLABUS)

By
BALAJI B.S.
Asst. Prof, Dept ECE.

DEPARTMENT
OF
ELECTRONICS AND COMMUNICATION ENGINEERING,

## BGS INSTITUTE OF TECHNOLOGY

B G NAGARA, NAGAMANGALA TALUK,
MANDYA – 571448.
2011–2012
HDLLABMANUAL-10ECL48_______________________________________________________________2012
HDL LAB PROGRAMS- IV Semester ECE (10ECL48)

LIST OF EXPERIMENTS………………..
PROGRAMMING USING VHDL & VERILOG – NON INTERFACING (PART – A)
1. Write HDL code to realize all the logic gates.
2. Write a HDL code for the following combinational designs
a. 2 to 4 decoder
b. 8 to 3 (encoder without priority & with priority)
c. 8 to 1 Multiplexer
d. 4 bit binary to gray code converter
e. Multiplexer, Demultiplexer, Comparator.
3. Write a HDL code to describe the functions of a Full Adder using three modelling
styles.
4. Write a model for 32 bit ALU using the schematic diagram shown below.

A(31:0) B(31:0)
Opcode(3:0)
Enable
Out(31:0)
ALU should use combinational logic to calculate an output based on the four bit op-
code input.
 ALU should pass the result to the out bus when enable line is high, and tri-state the
out bus when the enable line is low.
 ALU should decode the 4 bit op-code according to the given in example below.

## OPCODE ALU OPERATION

0000 A+ B
0001 A– B
0010 A Complement
0011 A* B
0100 A AND B
0101 A OR B
0110 A NAND B
0111 A XOR B
1000 A NOR B

5. Write the HDL code for the following flip-flops: SR, JK, D, T.
6. Design 4 bit binary, BCD counters (Synchronous reset and Asynchronous reset)
and “any sequence” counters.

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i) 4 bit Synchronous reset Binary counter
ii) 4 bit Asynchronous reset Binary counter
iii) 4 bit Synchronous reset BCD counter
iv) 4 bit Asynchronous reset BCD counter
v) 4 bit binary UP-DOWN Counter.

INTERFACING (PART – B)
1. Write HDL code to display messages on the given seven segment display and LCD
and accepting Hex key pad input data.
2. Write HDL code to control speed, direction of DC and Stepper motor.
3. Write HDL code to accept 8 channel Analog signal, Temperature Sensors and display
the data on LCD panel or Seven segment display.
4. Write HDL code to generate different waveforms (Sine, Square, Triangle, Ramp etc.,)
using DAC change the frequency and amplitude.
5. Write HDL code to simulate Elevator operations.
6. Write HDL code to control external lights using relays.

## XILINX ISE 9.1i

It is one of most popular software tool used to synthesize VHDL code. This tool includes
many steps. To make user feel comfortable with the tool the steps are given below:-

##  Double click on Project navigator. (Assumed icon is present on desktop).

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 Select NEW PROJECT in FILE MENU.
Enter following details as per your convenience
Project name : sample
Project location : C:\Xilinx
Top level module : HDL

##  In NEW PROJECT dropdown Dialog box, Choose your appropriate device

specification. Example is given below:
Device family : Spartan3
Device : xc3s400
Package : PQ208
TOP Level Module : HDL
Synthesis Tool : XST
Simulation : ISE Simulator
Generate sim lang : VHDL

##  In source window right click on specification, select new source

Enter the following details
Entity: sample
Architecture : Behavioral
Enter the input and output port and modes.
This will create sample.VHDL source file. Click Next and finish the initial
Project preparation.

 Double click on synthesis. If error occurs edit and correct VHDL code.
 Double click on Launch ISE simulator (or any equivalent simulator if you are
using) for functional simulation of your design.

##  Right click on sample.VHDL in source window, select new source

Select source : Implementation constraints file.
File name : sample
This will create sample. UCF constraints file.

##  Double click on Edit constraint (Text) in process window.

Edit and enter pin constraints with syntax:
NET “NETNAME” LOC = “PIN NAME”

 Double click on Implement, which will carry out translate, mapping, place
and route of your design. Also generate program file by double clicking on it,
in turn which will create .bit file.
 Connect JTAG cable between your kit and parallel port of your computer.
 Double click on configure device and select mode in which you want to
configure your device. For ex: select slave serial mode in configuration

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 Right click on device and select ‘program’. (Verify your design giving
appropriate inputs and check for the output.) Click OK and run the program
on the FPGA Kit.
 Also verify the actual working of the circuit using pattern generator & logic
analyzer.

## Procedure to view output on ISE Simulator

1. After the program is synthesized create a Test bench wave form by clicking on New
2. Highlight the tbw file and click onto ISE Simulator Simulate behavioral model.
3. Now click the waveform and zoom it to view the result.

1) Create a UCF(User Constraints File). or Click on User constraints on Processes
Window then click on assign package pins .
2) Click on UCF file and choose assign package pins option as shown in the figure
below.

## 3)Assign the package pins as shown in fig below

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## 3) save the file.

4) Click on Implement design and then Generate Programming File.
5) Click on the module and choose configure device option.
6) The following icon will be displayed.

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## 7) Right click on the icon and select program option.

8) Program succeeded message will be displayed.
9) Make connections to main board and daughter boards( before configuring ) , give
necessary inputs from pins of +5V and GND pins for each package pins and observe
the output on LEDs.

## NET "a" LOC = "p74" ;

NET "b" LOC = "p75" ;
NET "c" LOC = "p84" ;
NET "d" LOC = "p114" ;
NET "e" LOC = "p113" ;
NET "f" LOC = "p115" ;
NET "g" LOC = "p117" ;
NET "h" LOC = "p118" ;
NET "i" LOC = "p121" ;

## Repeat the above Procedure to all the Programs.

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## EXPERIMENT 1 - HDL code to realize all logic gates

AIM: To Simulate and realize all logic gates.
COMPONENTS REQUIRED: FPGA board, FRC’s and power supply.
THEORY :A logic gate is an electronic circuit/device which makes the logical decisions
alternatively a logic gate performs a logical operation on one or more logic inputs and
produces a single logic output. The logic normally performed is Boolean logic and is most
commonly found in digital circuits. Logic gates are primarily implemented using diodes or
transistors. The logic gates are broadly classified into 3 types:
Basic gates: AND, OR, NOT / INVERTER
Universal gates: NAND, NOR
Special gates: XOR, XNOR
Truth table with symbols

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## DATAFLOW DESCRIPTION IN VHDL:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity gates is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
y : out STD_LOGIC_VECTOR (6 downto 0));
end gates;

begin
y(0)<= a and b;
y(1)<= a or b;
y(2)<= a nand b;
y(3)<= a nor b;
y(4)<= a xor b;
y(5)<= a xnor b;
y(6)<= not a;

end Behavioral;

## module gates(a, b, y);

input a;
input b;
output [6:0] y;
assign y = a & b;
assign y = a | b;
assign y = ~(a & b);
assign y = ~(a | b);
assign y = a ^ b;
assign y = ~(a ^ b);
assign y = ~a;
endmodule

## BEHAVIORAL DESCRIPTION IN VHDL:

library IEEE;

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use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity gates is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
y : out STD_LOGIC_VECTOR (6 downto 0));
end gates;

begin
process(a, b)
begin
y(0)<= a and b;
y(1)<= a or b;
y(2)<= a nand b;
y(3)<= a nor b;
y(4)<= a xor b;
y(5)<= a xnor b;
y(6)<= not a;
end process;
end Behavioral;

## module gates(a, b, y);

input a;
input b;
output [6:0] y;
reg [6:0] y;
always @ (a,b)
begin
y = a & b;
y = a | b;
y = ~(a & b);
y = ~(a | b);
y = a ^ b;
y = ~(a ^ b);
y = ~a;
end
endmodule

Simulation Result
Before Execution

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After Execution

## User Constraint File

net “a” loc = “p74”;
net “b” loc = “p75”;
net “y(0)” loc = “p84”;
net “ y(1)” loc = “p85”;
net “ y(2)” loc = “p86”;
net “ y(3)” loc = “p87”;
net “ y(4)” loc = “p88”;
net “ y(5)” loc = “p89”;
net “ y(6)” loc = “p90”;

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## COMPONENTS REQUIRED: FPGA board, FRC’s and power supply.

THEORY : A decoder is a multiple input, multiple output logic circuit that converts coded
inputs into coded outputs where the input and output codes are different. The enable inputs
must be ON for the decoder to function, otherwise its outputs assumes a ‘disabled’ output
code word. Decoding is necessary in applications such as data multiplexing, seven segment

a) 2 to 4 Decoder

Block Diagram

Truth table

inputs outputs
en D_in(1) D_in(0) y3 y2 y1 y0
1 0 0 0 0 0 1
1 0 1 0 0 1 0
1 1 0 0 1 0 0
1 1 1 1 0 0 0
0 x x 0 0 0 0

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DECODER 2 to 4 – VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Dec24 is
Port ( I : in STD_LOGIC_VECTOR (1 downto 0);
en : in STD_LOGIC;
Y : out STD_LOGIC_VECTOR (3 downto 0));
end Dec24;

## architecture Behavioral of Dec24 is

begin
process(I, en)
begin
if(en = '0') then
Y <= "0000";
else
case I is
when "00" => Y <= "0001";
when "01" => Y <= "0010";
when "10" => Y <= "0100";
when "11" => Y <= "1000";
when others => null;
end case;
end if;
end process;
end Behavioral;

DECODER 2 to 4 – VERILOG

## module dec24v(i, en, y);

input [1:0] i;
input en;
output [3:0] y;
reg [3:0] y;
always @ (en, i)
begin
if (en = = 0)
y = 4'b0000;

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else
begin
case (i)
2'b00 : y = 4'b0001;
2'b01 : y = 4'b0010;
2'b10 : y = 4'b0100;
2'b11 : y = 4'b1000;
default: y = 4'b0000;
endcase
end
end
endmodule

Simulation Result
Before Execution

After Execution

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## THEORY : An encoder is a digital circuit which performs the inverse of decoder. An

encoder has 2N input lines and N output lines. In encoder the output lines generate the binary
code corresponding to input value. The decimal to BCD encoder usually has 10 input lines
and 4 output lines. The decoder decimal data as an input for decoder an encoded BCD output
is available at 4 output lines.

Block Diagram

Truth Table

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## ENCODER 8 to 3 (without priority) – VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity enc83 is
Port ( I : in STD_LOGIC_VECTOR (7 downto 0);
en : in STD_LOGIC;
Y : out STD_LOGIC_VECTOR (2 downto 0));
end enc83;

## architecture Behavioral of enc83 is

begin
process (I, en)
begin
if(en = '0') then
Y <= "000";
else
case I is
when "00000001" => Y <= "000";
when "00000010" => Y <= "001";
when "00000100" => Y <= "010";
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when "00001000" => Y <= "011";
when "00010000" => Y <= "100";
when "00100000" => Y <= "101";
when "01000000" => Y <= "110";
when "10000000" => Y <= "111";
when others => null;
end case;
end if;
end process;
end Behavioral;

## module enc8_3 (i, en, y);

input [7:0]i;
input en;
output [2:0]y;
reg [2:0]y;
always @ (en, i)
begin
if(en == 0)
y=3'b000;
else
case(i)
8'b00000001: y=3'b000;
8'b00000010: y=3'b001;
8'b00000100: y=3'b010;
8'b00001000: y=3'b011;
8'b00010000: y=3'b100;
8'b00100000: y=3'b101;
8'b01000000: y=3'b110;
8'b10000000: y=3'b111;
endcase
end
endmodule

Simulation Result

Before Execution

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After Execution

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Block diagram

Truth table

## ENCODER 8 to 3 (with priority) – VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity penc8_3 is
Port ( I : in STD_LOGIC_VECTOR (7 downto 0);
en : in STD_LOGIC;
y : out STD_LOGIC_VECTOR (2 downto 0));
end penc8_3;

## architecture Behavioral of penc8_3 is

begin
y<= "000" when en = '0' else
"111" when I(7)='1' else
"110" when I(6)='1' else
"101" when I(5)='1' else
"100" when I(4)='1' else
"011" when I(3)='1' else
"010" when I(2)='1' else
"001" when I(1)='1' else
"000" when I(0)='1' else
"000";
end Behavioral;

## module encoder (i, en, y);

input [7:0] i;
input en;
output [2:0] y;
reg [2:0] y;
always @(i,en)
begin
if(en==0)
y = 3'b000;
else
casex (i)
8'b00000001: y=3'b000;
8'b0000001x: y=3'b001;
8'b000001xx: y=3'b010;
8'b00001xxx: y=3'b011;
8'b0001xxxx: y=3'b100;
8'b001xxxxx: y=3'b101;
8'b01xxxxxx: y=3'b110;
8'b1xxxxxxx: y=3'b111;
default: y=3'b000;
endcase
end
endmodule

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Simulation Result
Before Execution

After Execution

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## net “en” loc = “p74”;

net “i0” loc = “p84”;
net “i1” loc = “p85”;
net “i2” loc = “p86”;
net “i3” loc = “p87”;
net “i4” loc = “p93”;
net “i5” loc = “p94”;
net “i6” loc = “p95”;
net “i7” loc = “p100”;
net “y0” loc = “p112”;
net “y1” loc = “p114”;
net “y2” loc = “p113”;

c. 8 to 1 Multiplexer

THEORY : Multiplexer is a digital switch.It allows digital information from several sources
to be rooted on to a single output line.The basic multiplexer has several data input lines and a
single output line.The selection of a particular input line is controlled by a set of selection
lines.Normally there are 2N input lines and N selection lines whose bit combinations
determine which input is selected.Therefore multiplexer is many into one and it provides the
digital equivalent of an analog selector switch.

Block Diagram:

Truth table:

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## Truth Table: Multiplexer 8 to 1

8 to 1 Multiplexer – VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Mux8_1 is
port ( SEL: in STD_LOGIC_VECTOR(2 downto 0); -- Select Lines
I: in STD_LOGIC_VECTOR(7 downto 0); -- Inputs of the Mux.
Y: out STD_LOGIC ); -- OutPut of the Mux.
end Mux8_1;

## architecture mux8_1_arch of Mux8_1 is

begin
process (SEL,I)
begin

case SEL is
when "000" => Y <= I(0);
when "001" => Y <= I(1);
when "010" => Y <= I(2);
when "011" => Y <= I(3);
when "100" => Y <= I(4);
when "101" => Y <= I(5);
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when "110" => Y <= I(6);
when "111" => Y <= I(7);
when others => null;
end case;
end process;
end mux8_1_arch;

8 to 1 Multiplexer – VERILOG

module mux8_1
input [7:0]I;
output [2:0]sel;
output y;
input en;
reg y;
always @(en,sel,I)
begin
if (sel == 0)
y = 1’b0;
else
case (sel)
3’b000: y = I;
3’b001: y = I;
3’b010: y = I;
3’b011: y = I;
3’b100: y = I;
3’b101: y = I;
3’b110: y = I;
3’b111: y = I;
default: y = 1’b0;
endcase
end
endmodule

Simulation Result
Before Execution

After Execution

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d. 4 to 1 Multiplexer

4 to 1 Multiplexer – VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Mux4_1 is
port ( SEL: in STD_LOGIC_VECTOR(1 downto 0); -- Select Lines
I: in STD_LOGIC_VECTOR(3 downto 0); -- Inputs of the Mux.
Y: out STD_LOGIC ); -- OutPut of the Mux.
end Mux4_1;

## architecture mux4_1_arch of Mux4_1 is

begin
process (SEL,I)
begin

case SEL is
when "00" => Y <= I(0);
when "01" => Y <= I(1);
when "10" => Y <= I(2);
when "11" => Y <= I(3);

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when others => null;
end case;
end process;
end mux4_1_arch;

4 to 1 Multiplexer – VERILOG

module mux4_1
input [3:0]I;
output [1:0]sel;
output y;
input en;
reg y;
always @(en,sel,I,y)
begin
if (sel == 0)
y = 1’b0;
else
case (sel)
2’b00: y = I;
2’b01: y = I;
2’b10: y = I;
2’b11: y = I;
default: y = 1’b0;
endcase
end
endmodule

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e. De-Multiplexer ( 1 to 4)

## THEORY : A demultiplexer is a circuit that receives information on a single line and

transmits this information on one of 2N output lines. The selection of specific output lines is
controlled by the value of N selection lines. The single input variable din as a path to all 4
outputs but the input information is directed to only one of the output lines.

Block Diagram

## Block Diagram of Demultiplexer 1 to 4

Truth table

i en Sel1 Sel0 y3 y2 y1 y0
1 1 0 0 0 0 0 1
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1 1 0 1 0 0 1 0
1 1 1 0 0 1 0 0
1 1 1 1 1 0 0 0
0 0 x x 0 0 0 0

## Truth Table: Demultiplexer 1 to 4

1 to 4 Demultiplexer – VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Demux1_4 is
port ( I, en : in STD_LOGIC;
sel: in STD_LOGIC_VECTOR (1 downto 0);
Y: out STD_LOGIC_VECTOR (3 downto 0));
end Demux1_4;

## architecture demux1_4_arch of Demux1_4 is

begin
process(d_in,sel)
begin
if (en = ‘0’) then
Y<="0000";
else
Y<="0000";
case sel is
when "00" => Y(0)<=I;
when "01" => Y (1)<=I;
when "10" => Y (2)<=I;
when others => Y (3)<=I;
end case;
end if;
end process;
end demux1_4_arch;

1 to 4 Demultiplexer – VERILOG

## module demux (sel, i, en, y);

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input en, i;
input [1:0]sel;
output [3:0]y;
reg [3:0]y;
always @ (en or sel or i)
begin
if(en= =0)
y = 4’b0000;
else
y = 4’b0000;
case(sel)
2’b00 : y = i;
2’b01 : y = i;
2’b10 : y = i;
2’b11 : y = i;
endcase
end
endmodule

f. N-Bit Comparator

## THEORY : Comparator is a special combinational circuit designed primarily to compare the

relative magnitude of 2 binary numbers. It receives 2N bit numbers A and B as inputs and the
outputs are A>B, A=B and A<B. Depending upon the relative magnitudes of the 2 numbers
one the outputs will be high.

Block diagram

Comparator – VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity comparator is
Generic (N: integer := 3);
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## Port( A,B: in STD_LOGIC_VECTOR(N downto 0); -- Inputs for Comparison

ALB,AGB,AEB: out STD_LOGIC); -- Output Signals to show Less than, Greater than
-- or Equal.
end comparator;

## architecture Comparator_arc of comparator is

begin
process(A,B)
begin
if ( A < B ) then
ALB <= '1';
AGB <= '0';
AEB <= '0';
end if;
if ( A > B ) then
AGB <= '1';
ALB <= '0';
AEB <= '0';
end if;
if ( A = B ) then
AEB <= '1';
AGB <= '0';
ALB <= '0';
end if;
end process;
end Comparator_arc;

Comparator – VERILOG

// Comparator Nbit
module comparatorNbit( a, b, agb, alb, aeb);
parameter N = 3;
input [N:0] a, b;
output agb, alb, aeb;
reg agb, alb, aeb;
always@(a, b)
begin
if( a > b)
begin
agb = 1;
alb = 0;
aeb = 0;
end

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else if( a < b)
begin
agb = 0;
alb = 1;
aeb = 0;
end
else if( a == b)
begin
agb = 0;
alb = 0;
aeb = 1;
end
end
endmodule

## g. 4 bit Binary to Gray code converter

Block diagram

Logic Diagram

Boolean expression

Truth table:
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En B3 B2 B1 B0 G3 G2 G1 G0
0 0 0 0 0 0 0 0 0
1 0 0 0 1 0 0 0 1
1 0 0 1 0 0 0 1 1
1 0 0 1 1 0 0 1 0
1 0 1 0 0 0 1 1 0
1 0 1 0 1 0 1 1 1
1 0 1 1 0 0 1 0 1
1 0 1 1 1 0 1 0 0
1 1 0 0 0 1 1 0 0
1 1 0 0 1 1 1 0 1
1 1 0 1 0 1 1 1 1
1 1 0 1 1 1 1 1 0
1 1 1 0 0 1 0 1 0
1 1 1 0 1 1 0 1 1
1 1 1 1 0 1 0 0 1
1 1 1 1 1 1 0 0 0
VHDL Dataflow Description

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity B2G is
port ( b : in std_logic_vector(3 downto 0);
g : out std_logic_vector(3 downto 0));
end B2G;

## architecture BG2 of B2G is

begin
g(3) <= b(3);
g(2) <= b(2) xor b(3);
g(1) <=b(1) xor b(0);
g(0) <= b(1) xor b(0);
end BG2;

Verilog

## // Binary to Gray 4bit Converter

module b2g(b,g);
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input [3:0] b;
output [3:0] g;
assign g=b;
assign g = (b^b);
assign g = (b^b);
assign g = (b^b);
endmodule

AIM: Write HDL code to describe the functions of a full Adder Using three modeling styles.

## COMPONENTS REQUIRED: FPGA board, FRC’s and power supply.

Block Diagram

Truth table

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## Full Adder Data Flow Description

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
Port ( a_in, b_in, c_in : in STD_LOGIC;
sum, carry : out STD_LOGIC);

## architecture Data_Flow of FullAdder_DF is

begin
sum <= a_in xor b_in xor c_in;
carry <= (a_in and b_in) or (b_in and c_in) or (a_in and c_in);
end Data_Flow;

Verilog

## // FullAdder - Data Flow Model

module FullAdder_DF( a_in, b_in, c_in, sum, carry );

## output sum, carry;

assign sum = a_in ^ b_in ^ c_in;
assign carry = (a_in & b_in) | (b_in & c_in) | (c_in & a_in);
endmodule
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VHDL
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
Port ( a_in, b_in, c_in : in STD_LOGIC;

## architecture Behavioral of FullAdder_Behav is

begin
process ( a_in, b_in, c_in)
begin

## if(a_in='0' and b_in='0' and c_in = '0') then

sum <= '0';carry <= '0';
elsif (( a_in='0' and b_in='0' and c_in = '1') or (a_in='0' and b_in='1' and c_in = '0') or (a_in='1'
and b_in='0' and c_in = '0')) then
sum <= '1';carry <= '0';
elsif (( a_in='0' and b_in='1' and c_in = '1') or (a_in='1' and b_in='0' and c_in = '1') or (a_in='1'
and b_in='1' and c_in = '0')) then
sum <= '0';carry <= '1';
elsif(a_in='1' and b_in='1' and c_in = '1') then
sum <= '1';carry <= '1';
end if;

end process;
end Behavioral;

Verilog
module FullAdder_Behav( a_in, b_in, c_in, sum, carry );
input a_in, b_in, c_in;
output sum, carry;

## wire a_in, b_in, c_in;

reg sum, carry;
always @ ( a_in, b_in, c_in)
begin
if(a_in==0 & b_in==0 & c_in==0)
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begin
sum = 0;
carry = 0;

end
else if (( a_in==0 & b_in==0 & c_in == 1) | (a_in==0 & b_in==1 & c_in == 0) | (a_in==1 &
b_in==0 & c_in == 0))
begin
sum = 1;
carry = 0;
end
else if (( a_in==0 & b_in==1 & c_in == 1) | (a_in==1 & b_in==0 & c_in == 1) | (a_in==1 &
b_in==1 & c_in == 0))
begin

sum = 0;
carry = 1;
end
else if(a_in==1 & b_in==1 & c_in == 1)
begin
sum = 1;
carry = 1;
end
end
endmodule

## Full Adder Structural Description - VHDL

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

port ( x,y : in std_logic;
sum,carry : out std_logic);

## architecture behavioral of halfadder1 is

begin
sum<= x xor y;
carry <= x and y;
end behavioral;

library ieee;
use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity or_gate is
port ( p,q : in std_logic;
r : out std_logic);
end or_gate;

## architecture behavioral of or_gate is

begin
r<= p or q;
end behavioral;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

port (x, y, cin : in std_logic;
sum, cout : out std_logic);

## architecture structural of fulladder1 is

port (x, y : in std_logic;
sum,carry : out std_logic);
end component;

component or_gate
port (p, q : in std_logic;
r : out std_logic);
end component;

## signal temp1, temp2, temp3 :std_logic;

begin
L1: halfadder1 port map (x, y, temp1, temp2);
L2: halfadder1 port map (temp1, cin, sum, temp3);
L3: or_gate port map (temp2, temp3, cout) ;
end structural;

## module fa (x, y, cin, carry, sum);

input x, y, cin;

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output carry, sum;
ha ha1 (y, cin, s0, c0);
ha ha2 (x, s0, sum, c1);
or ( carry, c0, c1);
endmodule

module ha(a, b, s, c);
input a, b;
output s, c;
xor(s, a, b);
and (c, a, b);
endmodule

Simulation Result
Before Execution

After Execution

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## net “x” loc = “p74”;

net “y” loc = “p75”;
net “sum” loc = “p84”;
net “cout” loc = “p85”;

## EXPERIMENT 5 32 bit ALU

AIM: Write a model for 32 bit ALU using the schematic diagram shown below.

## COMPONENTS REQUIRED:FPGA/CPLD board, FRC’s, jumper and power supply.

Block diagram

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Truth table

## OPCODE ALU OPERATION

0000 A+ B
0001 A– B
0010 A Complement
0011 A* B
0100 A AND B
0101 A OR B
0110 A NAND B
0111 A XOR B

8 bit ALU
VHDL
--ALU32bit – Behavioral
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity alu32bit is
Port ( en : in BIT;
opc : in STD_LOGIC_VECTOR (3 downto 0);
a_in, b_in : in STD_LOGIC_VECTOR (31 downto 0);
y_op : out STD_LOGIC_VECTOR (31 downto 0));
end alu32bit;
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## architecture Behavioral of alu32bit is

begin
process(en, a_in, b_in, opc)
begin
if (en = '1') then -- Active High Enabled
case opc is
when "0000" => y_op <= a_in + b_in;
when "0001" => y_op <= a_in - b_in;
when "0010" => y_op <= not a_in;
when "0011" => y_op <= a_in * b_in;
when "0100" => y_op <= a_in and b_in;
when "0101" => y_op <= a_in or b_in;
when "0110" => y_op <= a_in nand b_in;
when "0111" => y_op <= a_in xor b_in;
when others => null;
end case;
else
y_op <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
end if;
end process;
end behavioral;

Verilog
// ALU 32bit
module alu32bit( en, opc, a_in, b_in, y_op );
input en;
input [3:0] opc;
input [31:0] a_in, b_in;
output [31:0] y_op;
wire en;
wire [3:0] opc;
wire [31:0] a_in, b_in;
reg [31:0] y_op;
always @ ( en, opc, a_in, b_in)
if (en == 1) // Active High Enabled
case (opc)
4'b0000 : y_op = a_in + b_in;
4'b0001 : y_op = a_in - b_in;
4'b0010 : y_op = ~ a_in;
4'b0011 : y_op = a_in * b_in;
4'b0100 : y_op = a_in & b_in;
4'b0101 : y_op = a_in | b_in;
4'b0110 : y_op = ~ (a_in & b_in);
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4'b0111 : y_op = a_in ^ b_in;
default null;
endcase
else
y_op = 32'bZ;
endmodule

## vhdl 8 bit ALU

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
entity ALU is
Port ( A : in std_logic_vector(7 downto 0); -- First Input
B : in std_logic_vector(7 downto 0); -- Second Input
Opcode : in std_logic_vector(2 downto 0); -- Op-code to select the operations
enb : in std_logic; -- Enable Signal
op : out std_logic_vector(7 downto 0)); -- Output of the ALU
end ALU;
architecture Behavioral of ALU is
begin
process(A,B,Opcode,enb)
begin
if enb= '1' then
case Opcode is
when "000" => op<= A+B;
when "001" => op<= A-B;
when "010" => op<= not A;
when "011" => op<= A*B;
when "100" => op<= A and B;
when "101" => op<= A or B;
when "110" => op<= A nand B;
when others => op<= A xor B;
end case;
else
op <= (others =>'Z');
end if;
end process;
end Behavioral;

Verilog
// ALU 8 bit

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module alu8bit( en, opc, a_in, b_in, y_op );
input en;
input [3:0] opc;
input [7:0] a_in, b_in;
output [7:0] y_op;
reg [7:0] y_op;
always @ ( en, opc, a_in, b_in)
if (en == 1) // Active High Enabled
case (opc)
4'b0000 : y_op = a_in + b_in;
4'b0001 : y_op = a_in - b_in;
4'b0010 : y_op = ~ a_in;
4'b0011 : y_op = a_in * b_in;
4'b0100 : y_op = a_in & b_in;
4'b0101 : y_op = a_in | b_in;
4'b0110 : y_op = ~ (a_in & b_in);
4'b0111 : y_op = a_in ^ b_in;
default null;
endcase
else
y_op = 8'bZ;
endmodule

EXPERIMENT 6 FLIPFLOPS

AIM: Develop the HDL code for the following flip-flop: SR, JK, T, D.

## COMPONENTS REQUIRED:FPGA board, FRC’s and power supply.

THEORY :
SR flip-flop: A SR flip - flop is the simplest possible memory element. The SR flip flop has
two inputs Set and Reset. The SR flip-flop is a basic building block for other flip-flops.

D flip-flop: This is a flip - flop with a delay (D) equal to exactly equal to one cycle of the
clock. The defect with SR FF is the indeterminate output when the data inputs at S and R are
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1. In order to avoid this the input to R is through an inverter from S so that the input to R is
always the complement of S and never same. The S input is redesignated as D.

JK flip-flop: The JK flip flop is called a “universal flip flop” because the other flip flops like
D, SR, T can be derived from it. The “racing or race around condition” takes place in a JK FF
when J=1 and K=1 and clock=1.

T flip-flop: T stands for toggling. It is obtained from JK FF by tying both the inputs J and K.

a. SRFF

BLOCK DIAGRAM

TRUTH TABLE

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SRFF – VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity sr_ff is
Port ( s,r,rst,clk : in STD_LOGIC;
q,qb : out STD_LOGIC);
end sr_ff;
architecture Behavioral of sr_ff is
signal temp : std_logic := '0';
begin
process(clk,rst)
begin
if(rst = '1') then
temp <= '0';
elsif (clk'event and clk = '1') then
if(s = '0' and r ='0') then
temp <= temp;
elsif(s = '0' and r ='1') then
temp <= '0';
elsif(s = '1' and r ='0') then
temp <= '1';
elsif(s = '1' and r ='1') then
temp <= 'X';
end if;
end if;
end process;
q <= temp;
qb <= not temp;
end Behavioral;
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SRFF - VERILOG

## module sr_ff( sr , clk , reset , q ,qb );

input [1:0] sr;
input clk, reset ;
output q,qb;
reg q,qb;
always @ ( posedge clk or posedge reset)
if (reset)
begin
q = 1'b0;
qb = ~q;
end
else
begin
case (sr)
2'd0 : q = q;
2'd1 : q = 1'b0;
2'd2 : q = 1'b1;
2'd3 : q = 1'bX;
endcase
qb = ~q;
end
endmodule

b. JK Flipflop

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BLOCK DIAGRAM

Truth table

JKFF – VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity jk_ff is
Port ( j,k,rst,clk : in STD_LOGIC;
q,qb : out STD_LOGIC);
end jk_ff;
architecture Behavioral of jk_ff is
signal temp : std_logic := '0';
begin
process(clk,rst)
begin
if(rst = '1') then
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temp <= '0';
elsif(clk'event and clk = '1') then
if(j = '0' and k ='0') then
temp <= temp;
elsif(j = '0' and k ='1') then
temp <= '0';
elsif(j = '1' and k ='0') then
temp <= '1';
elsif(j = '1' and k ='1') then
temp <= not temp;
end if;
end if;
end process;
q <= temp;
qb <= not temp;
end Behavioral;

JKFF – Verilog

## module jk_ff( jk , clk , reset , q ,qb );

input [1:0] jk;
input clk, reset ;
output q,qb;
reg q,qb;
always @ ( posedge clk or posedge reset)
if (reset)
begin
q = 1'b0;
qb = ~q;
end
else
begin
case (jk)
2'd0 : q = q;
2'd1 : q = 1'b0;
2'd2 : q = 1'b1;
2'd3 : q = ~q;
endcase
qb = ~q;
end
endmodule

c. D Flipflop

BLOCK DIAGRAM

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Truth table

DFF – VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity d_ff is
Port ( d,clk,rst : in STD_LOGIC;
q,qb : out STD_LOGIC);
end d_ff;
architecture Behavioral of d_ff is
signal temp : std_logic := '0';
begin
process(clk,rst)
begin
if(rst = '1') then
temp <= '0';
elsif(clk'event and clk = '1') then
temp <= d;
end if;
end process;
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q <= temp;
qb <= not temp;
end Behavioral;

DFF – Verilog

## module d_ff( d , clk , reset , q ,qb );

input d, clk, reset ;
output q,qb;
reg q,qb;
always @ ( posedge clk or posedge reset)
if (reset)
begin
q = 1'b0;
qb=~q;
end
else
begin
q = d;
qb=~q;
end
endmodule

d. T Flipflop

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BLOCK DIAGRAM

Truth table

TFF – VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity t_ff is
Port ( t,clk,rst : in STD_LOGIC;
q,qb : out STD_LOGIC);
end t_ff;
architecture Behavioral of t_ff is
signal temp : std_logic := '0';
begin
process(clk,rst)
begin
if(rst = '1') then
temp <= '0';
elsif(clk'event and clk = '1' and t = '1') then
temp <= not temp;

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end if;
end process;
q <= temp;
qb <= not temp;
end Behavioral;

TFF – Verilog

## module t_ff( t, clk, reset, q, qb );

input t, clk, reset ;
output q,qb;
reg q,qb;
always @ ( posedge clk or posedge reset)
if (reset)
begin
q = 1'b0;
qb=~q;
end
else
if (t)
begin
q = ~q;
qb = ~q;
end
endmodule

EXPERIMENT 7 COUNTERS
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AIM: Design 4 bit Binary, BCD counter (Synchronous reset and Asynchronous reset and
any sequence counters.

Truth Table

## Clk Rst Qout

x 1 0000
1 0 0001
1 0 0010
1 0 0011
1 0 0100
1 0 0101
1 0 0110
1 0 0111
1 0 1000
1 0 1001
1 0 1010
1 0 1011
1 0 1100
1 0 1101
1 0 1110
1 0 1111

VHDL
-- Binary Synchronous reset 4bit counter

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity bin_counter_sync_4bit is
Port ( clk,rst : in STD_LOGIC;
bin_out : out STD_LOGIC_VECTOR (3 downto 0));
end bin_counter_sync_4bit;
architecture Behavioral of bin_counter_sync_4bit is
signal temp: std_logic_vector(3 downto 0) := “0000”;
begin
process(clk)
begin
if ( clk'event and clk='1') then
if(rst = '1') then
temp <= "0000";
else
temp <= temp+'1';
end if;
end if;
end process;
bin_out <= temp ;
end Behavioral;

Verilog
// Binary synchronous reset 4bit counter
module bin_sync_4bit ( rst, clk, count);
input rst,clk;
output [3:0] count;
reg [3:0] count;
initial
begin
count = 4'b0000;
end
always @(posedge clk)
if(rst)
count = 4'b0000;
else
count = count + 4'b0001;
endmodule

## a. Binary Asynchronous reset 4 bit counter

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Block Diagram

VHDL

## --Binary Asynchronous reset 4bit counter

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity bin_counter_async_4bit is
Port ( clk,rst : in STD_LOGIC;
bin_out : out STD_LOGIC_VECTOR (3 downto 0));
end bin_counter_async_4bit;

## architecture Behavioral of bin_counter_async_4bit is

signal temp: std_logic_vector(3 downto 0) := “0000”;
begin
process(clk,rst)
begin
if(rst = '1') then
temp <= "0000";
elsif ( clk'event and clk='1') then
temp <= temp+'1';
end if;
end process;
bin_out <= temp ;
end Behavioral;

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Verilog

## module bin_async_4bit ( rst, clk, count);

input rst,clk;
output [3:0] count;
reg [3:0] count;
initial
begin
count = 4'b0000;
end
always @(posedge clk or posedge rst)
if(rst)
count = 4'b0000;
else
count = count + 4'b0001;
endmodule

## c. BCD Synchronous Reset 4 bit Counter

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Block Diagram

VHDL

## --BCD Synchronous reset 4bit counter

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity bcd_counter_sync is
Port ( clk,rst : in STD_LOGIC;
bcd_out : out STD_LOGIC_VECTOR (3 downto 0));
end bcd_counter_sync;

## architecture Behavioral of bcd_counter_sync is

signal temp: std_logic_vector(3 downto 0) := “0000”;
begin
process(clk)
begin
if ( clk'event and clk='1') then
if(rst = '1' or temp = "1001") then
temp <= "0000";
else
temp <= temp+'1';
end if;
end if;
end process;
bcd_out <= temp ;
end Behavioral;

Verilog
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## module bcd_sync ( rst, clk, count);

input rst,clk;
output [3:0] count;
reg [3:0] count;
initial
begin
count = 4'd0;
end
always @(posedge clk)
if(rst)
count = 4'd0;
else if(count < 4'd9 )
count = count + 4'd1;
else
count = 4'd0;
endmodule

## d. BCD Asynchronous Reset 4 bit Counter

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Block Diagram

VHDL

## -- BCD asynchronous reset 4bit counter

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity bcd_counter_async is
Port ( clk,rst : in STD_LOGIC;
bcd_out : out STD_LOGIC_VECTOR (3 downto 0));
end bcd_counter_async;

## architecture Behavioral of bcd_counter_async is

signal temp: std_logic_vector(3 downto 0):= "0000";
begin
process(clk,rst)
begin
if(rst = '1' or temp = "1001") then
temp <= "0000";
elsif ( clk'event and clk='1') then
temp <= temp+'1';
end if;
end process;
bcd_out <= temp;
end Behavioral;

Verilog
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## module bcd_async ( rst, clk, count);

input rst,clk;
output [3:0] count;
reg [3:0] count;
initial
begin
count = 4'd0;
end
always @(posedge clk or posedge rst)
if(rst)
count = 4'd0;
else if(count < 4'd9 )
count = count + 4'd1;
else
count = 4'd0;
endmodule

## e. Binary Any Sequence Up Down 4 bit Counter

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Block Diagram

VHDL

## -- Binary Any Sequence up down 4bit counter

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity bin_counter_any_seq is
Port ( clk,rst,load,updown : in STD_LOGIC;
d_in :in STD_LOGIC_VECTOR( 3 downto 0);
bin_out : out STD_LOGIC_VECTOR (3 downto 0));
end bin_counter_any_seq;
architecture Behavioral of bin_counter_any_seq is
signal temp: std_logic_vector(3 downto 0):= "0000";
begin
process(clk, rst)
begin
if(rst = '1') then
temp <= "0000";
temp <= d_in;
elsif ( clk'event and clk='1' and load = '0') then
if ( updown = '1') then
temp <= temp+'1';
else
temp <= temp-'1';
end if;
end if;
end process;
bin_out <= temp;
end Behavioral;

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Verilog

## module any_seq_bin ( rst,load, clk,din,updown, count);

input [3:0] din;
output [3:0] count;
reg [3:0] count;
initial
begin
count = 4'b0000;
end
always @(posedge clk)
if(rst)
count = 4'b0000;
count = din;
else if (updown)
count = count + 4'b0001;
else
count = count - 4'b0001;
endmodule

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INTERFACING – PART B

Procedure to execute:

##  Create new source

 Implementation constraints file
 User constraints
 Create Timing constraints: Give the input and output ports from the port number
look up table(pin assignment) and then save.
 Edit constraints to check the specified ports

##  Click on the source file

 Implement design

##  Select the slave serial mode

 Select the source file
 Right click on xilinx and select program

Connect input port to dip switch and output port to led’s. Vary the inputs and view the
corresponding outputs.

INTERFACING PROGRAMS

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## 1. WRITE A HDL CODE TO CONTROL THE SPEED, DIRECTION OF

DC & STEPPER MOTOR

DC MOTOR
VHDL CODE:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity dcmotr is
Port ( dir,clk,rst : in std_logic;
pwm : out std_logic_vector(1 downto 0);
rly : out std_logic;
row : in std_logic_vector(0 to 3));
end dcmotr;

## architecture Behavioral of dcmotr is

signal countr: std_logic_vector(7 downto 0);
signal div_reg: std_logic_vector(16 downto 0);
signal ddclk,tick: std_logic;
signal duty_cycle:integer range 0 to 255;

begin
process(clk,div_reg)
begin
if(clk'event and clk='1') then
div_reg<=div_reg+'1';
end if;
end process;
ddclk<=div_reg(12);
tick<= row(0) and row(1) and row(2) and row(3);
process(tick)
begin
if falling_edge(tick) then
case row is

when"1110"=> duty_cycle<=255;
when"1101"=> duty_cycle<=200;
when"1011"=> duty_cycle<=150;
when"0111"=> duty_cycle<=100;
when others => duty_cycle<=100;
end case;
end if;
end process;

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process(ddclk, rst)
begin
if rst='0'then countr<=(others=>'0');
pwm<="01";
elsif(ddclk'event and ddclk='1') then
countr<= countr+1;
if countr>=duty_cycle then
pwm(1)<='0';
else pwm(1)<='1';
end if;
end if;
end process;
rly<='1' when dir='1' else '0';

end Behavioral;

PRODEDURE:1) Make connection between FRC 9 and FPGA board to the dc motor
connector of VTU card 2
2) Make the connection between FRC 7 of FPGA board to the K/B connector of VTU card 2
3) Make the connection between FRC 1 of FPGA board to the DIP switch connector of VTV
card 2.
4) Connect the down loading cable and power supply to FPGA board.
5) Then open xilinx impact s/w, select slave serial mode and select the respective bit file and
click program.
6) Make the reset switch on.
7) Press the Hex keys and analyze speed changes for dc motor.

RESULT: The DC motor runs when reset switch is on and with pressing of different keys
variation of DC motor speed was noticed.

STEPPER MOTOR
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity steppermt is
Port ( clk,dir,rst : in std_logic;
dout : out std_logic_vector(3 downto 0));
end steppermt;

## architecture Behavioral of steppermt is

signal clk_div:std_logic_vector(15 downto 0); -- speed is maximum at 15
signal shift_reg:std_logic_vector(3 downto 0);
begin
process(clk)
begin
if rising_edge (clk) then
clk_div <= clk_div+'1';
end if;
end process;
process(rst,clk_div(15)) -- speed is maximum at 15
begin
if rst='0' then shift_reg<="0001";
elsif rising_edge (clk_div(15)) then
if dir='1' then
shift_reg <= shift_reg(0) & shift_reg(3 downto 1);
else
shift_reg<= shift_reg ( 2 downto 0) & shift_reg(3);
end if;
end if;
end process;
dout<= shift_reg;

end Behavioral;

## NET "clk" LOC = "p18"; NET "dir" LOC = "p85";

NET "rst" LOC = "p84";
NET "dout<0>" LOC = "p7"; NET "dout<1>" LOC = "p5";
NET "dout<2>" LOC = "p3"; NET "dout<3>" LOC = "p141";

PROCEDURE:1) Make connection between FRC 9 and FPGA board to the stepper motor
connector of
VTU card 1
2) Make the connection between FRC 1 of FPGA board to the DIP switch connector of
VTU card 1.
3) Then open xilinx impact s/w, select slave serial mode and select the respective bit file
and click program.

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4) Make the reset switch on.
5) Visualize the speed variation of stepper motor by changing counter value in the
program.

RESULT: The stepper motor runs with varying speed by changing the counter value

## 2.WRITE A HDL CODE TO CONTROL EXTERNAL LIGHTS USING

RELAYS
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VHDL CODE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity extlight is
Port ( cntrl1,cntrl2 : in std_logic;
light : out std_logic);
end extlight;
architecture Behavioral of extlight is
begin
light<= cntrl1 OR cntrl2 ;
end Behavioral;

## NET "cntrl1" LOC = "P74";

NET "cntrl2" LOC = "P75";
NET "light" LOC = "P7";

PROCEDURE:
1.Make the connections b/w FRC9 of fpga board to external light connector of vtu card 2
2.Make connection b/w FRC1 of fpga board to the dip switch connector of vtucard2
1. Then open the xilinx impact software select the slave serial mode and select
respective bit file and click program
2. Make the reset switch on and listen to the tick sound.

RESULT: Once the pin p74 (reset) is switched on the tick sound is heard at the external light
junction.

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3. WRITE HDL CODE TO GENERATE DIFFERENT WAVEFORMS
(SAWTOOTH, SINE WAVE, SQUARE, TRIANGLE, RAMP ETC) USING
DAC CHANGE THE FREQUENCY AND AMPLITUDE.

SAWTOOTH

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity sawtooth is
Port ( clk,rst : in std_logic;
dac : out std_logic_vector(0 to 7));
end sawtooth;

## architecture Behavioral of sawtooth is

signal temp:std_logic_vector(3 downto 0);
signal cnt:std_logic_vector( 0 to 7);

begin
process(clk)
begin
if rising_edge(clk) then
temp<= temp+'1';
end if;
end process;
process (temp(3),cnt)
begin
if rst='1' then cnt<="00000000";
elsif rising_edge(temp(3)) then
cnt<= cnt+1;
end if;
end process;
dac<=cnt;
end Behavioral;

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SQUARE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity squarewg is
Port ( clk,rst : in std_logic;
dac : out std_logic_vector(0 to 7));
end squarewg;

## architecture Behavioral of squarewg is

signal temp:std_logic_vector(3 downto 0);
signal cnt:std_logic_vector(0 to 7);
signal en: std_logic;

begin
process(clk)
begin
if rising_edge(clk) then
temp<= temp+'1';
end if;
end process;

process(temp(3))
begin
if rst='1' then cnt<="00000000";
elsif rising_edge (temp(3)) then
if cnt< 255 and en='0' then
cnt<=cnt+1;
en<='0';
dac<="00000000";
elsif cnt=0 then en<='0';
else en<='1';
cnt<=cnt-1;
dac<="11111111";
end if;
end if;
end process;
end Behavioral;

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TRIANGLE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity triangwg is
Port ( clk,rst : in std_logic;
dac : out std_logic_vector(0 to 7));
end triangwg;

## architecture Behavioral of triangwg is

signal temp: std_logic_vector( 3 downto 0);
signal cnt: std_logic_vector(0 to 8);
signal en:std_logic;
begin
process(clk)
begin
if rising_edge(clk) then
temp<= temp+1;
end if;
end process;
process( temp(3))
begin
if rst='1' then cnt<="000000000";
elsif rising_edge(temp(3)) then
cnt<=cnt+1;
if cnt(0)='1' then
dac<=cnt(1 to 8);
else
dac<= not(cnt( 1 to 8));
end if;
end if;
end process;
end Behavioral;

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RAMP

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity rampwg is
Port ( clk,rst : in std_logic;
dac : out std_logic_vector(0 to 7));
end rampwg;

## architecture Behavioral of rampwg is

signal temp:std_logic_vector(3 downto 0);
signal cnt:std_logic_vector( 0 to 7);

begin
process(clk)
begin
if rising_edge(clk) then
temp<= temp+'1';
end if;
end process;
process (temp(3),cnt)
begin
if rst='1' then cnt<="00000000";
elsif rising_edge(temp(3)) then
cnt<= cnt+15;
end if;
end process;
dac<=cnt;

end Behavioral;

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SINE WAVE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity sinewave is
Port ( clk,rst : in std_logic;
dac_out : out std_logic_vector(0 to 7));
end sinewave;
architecture Behavioral of sinewave is
signal temp: std_logic_vector(3 downto 0);
signal counter: std_logic_vector(0 to 7);
signal en: std_logic;
begin
process(clk) is
begin
if rising_edge (clk) then
temp<= temp+'1';
end if;
end process;
process(temp(3)) is
begin
if rst='1' then counter<="00000000";
elsif rising_edge(temp(3)) then
if counter<255 and en='0' then
counter<= counter+31; en<='0';
elsif counter=0 then en<='0';
else en<='1';
counter<= counter-31;
end if;
end if;
end process;
dac_out<= counter;
end Behavioral;

PROCEDURE:
1) Make connection between FRC 5 and FPGA and DAC connector of VTU card 2.
2) Make the connection between FRC 1 of FPGA board to the DIP switch connector of VTU
card 2.
3) Then open xilinx impact s/w, select slave serial mode and select the respective bit file and
click program.
4) Make the reset switch on.

RESULT:The waveform obtained Ramp, Saw tooth, Triangular, Sine and Square waves are
as per the graph.

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## 4. WRITE A HDL CODE TO DISPLAY MESSAGES ON THE GIVEN

SEVEN SEGMENT DISPLAY

VHDL CODE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity sevkeybrd is
Port ( read : in std_logic_vector(3 downto 0);
clk : in std_logic;
scan : inout std_logic_vector(3 downto 0);
disp_cnt : out std_logic_vector(3 downto 0);
disp1 : out std_logic_vector(6 downto 0));
end sevkeybrd;

## architecture Behavioral of sevkeybrd is

signal cnt_2bit:std_logic_vector(1 downto 0);
begin
process(clk)
begin
if clk='1' and clk'event then
cnt_2bit<= cnt_2bit+1;
end if;
end process;
process(cnt_2bit)
begin
case cnt_2bit is
when "00" => scan<= "0001";
when "01"=> scan<="0010";
when "10"=>scan<="0100";
when "11"=>scan<="1000";
when others=> null;
end case;
end process;
disp_cnt<="1110";
begin
case scan is
when "0001"=>disp1<="1111110";
when "0010"=>disp1<="0110011";
when "0100"=>disp1<="1111111";
when "1000"=>disp1<="1001110";
when others =>disp1<="0000000";
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end case;

## when "0010"=> case read is

when "0001"=>disp1<="0110000";
when "0010"=>disp1<="1011011";
when "0100"=>disp1<="1111011";
when "1000"=>disp1<="0111101";
when others=>disp1<="0000000";
end case;

## when "0100"=> case read is

when "0001"=>disp1<="1101101";
when "0010"=>disp1<="1011111";
when "0100"=>disp1<="1110111";
when "1000"=>disp1<="1001111";
when others=>disp1<="0000000";
end case;

## when "1000"=> case read is

when "0001"=>disp1<="1111001";
when "0010"=>disp1<="1110000";
when "0100"=>disp1<="0011111";
when "1000"=>disp1<="1000111";
when others=>disp1<="0000000";
end case;
when others=> null;
end case;
end process;
end Behavioral;

PROCEDURE:
1) Make connection between FRC 5 and FPGA board to the seven segment connector of
VTU card 1.
2) Make the connection between FRC 4 to FPGA board to K/B connector of VTU card1.
3) Then open xilinx impact s/w, select slave serial mode and select the respective bit file
and click program.
4) Make the reset switch on.
5) Change the pressing of Hex Keys to watch the display on LCD’s ranging from 0000 to
FFFF.
RESULT:The values from 0 to F were displayed on all 4 LCD’s with the respective Hex Key
being pressed.

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I/O Pin Assignments

## FOR DC & Stepper

Xilinx FPGA MOTOR
FRC FRC1 FRC2 FRC3 FRC4 FRC6 FRC7 Xilinx FPGA
1 74 84 112 122 40 58 FRC FRC9
2 75 85 114 124 41 60 1 7
3 76 86 113 129 42 63 2 5
4 78 87 115 126 48 64 3 3
5 77 93 117 132 50 65 4 141
6 80 94 118 136 51 66 9 5V
7 79 95 121 134 56 67 10 GND
8 83 100 123 139 57 28
9 VCC VCC VCC VCC VCC VCC
10 GND GND GND GND GND GND
FOR LCD & DAC FOR ADC
FRC FRC5 FRC8 FRC10
1 4 96 62
2 20 99 59
3 19 101 49
4 21 102 47
5 23 103 46
6 22 116 4
7 26 120 43
8 27 131 13
9 30 133 12
10 29 137 11
11 31 138 10
12 38 140 6
13 5V 5V 5V
14 -5v -5v -5v
15 3.3 3.3 3.3
16 GND GND GND

Constraints file
1. External Light Controller
NET "cntrl" LOC="p74"; => FRC1
NET "light" LOC="p7"; => FRC9

2. DC MOTOR
NET "CLK" LOC="p18";

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NET "RESET" LOC="p74";
FRC1
NET "dir" LOC="p75";
NET "pwm<0>" LOC="p5";
NET "pwm<1>" LOC="p141"; FRC9
NET "rly" LOC="p3";
NET "ROW<0>" LOC="p64";
NET "ROW<1>" LOC="p63";
FRC7
NET "ROW<2>" LOC="p60";
NET "ROW<3>" LOC="p58";
3. STEPPER MOTOR
NET "CLK" LOC="p18";
NET "dout<0>" LOC="p7";
NET "dout<1>" LOC="p5";
FRC9
NET "dout<2>" LOC="p3";
NET "dout<3>" LOC="p141";
NET "RESET" LOC="p74";
FRC1
NET "dir" LOC="p75";
4.DAC
NET "CLK" LOC="p18";
NET "dac_out<0>" LOC="p27";
NET "dac_out<1>" LOC="p26";
NET "dac_out<2>" LOC="p22";
NET "dac_out<3>" LOC="p23"; FRC5
NET "dac_out<4>" LOC="p21";
NET "dac_out<5>" LOC="p19";
NET "dac_out<6>" LOC="p20";
NET "dac_out<7>" LOC="p4";
NET "rst" LOC="p74"; FRC1

## 5. KEY BOARD TO 7 SEGMENT DISPLAY

NET "CLK" LOC="p18";
NET "disp_cnt<0>" LOC="p30";
NET "disp_cnt<1>" LOC="p29";
NET "disp_cnt<2>" LOC="p31";
NET "disp_cnt<3>" LOC="p38";
NET "disp<0>" LOC="p26";
NET "disp<1>" LOC="p22"; FRC5
NET "disp<2>" LOC="p23";
NET "disp<3>" LOC="p21";
NET "disp<4>" LOC="p19";
NET "disp<5>" LOC="p20";
NET "disp<6>" LOC="p4";
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NET "scan_l<0>" LOC="p132";
NET "scan_l<1>" LOC="p136";
NET "scan_l<2>" LOC="p134";
NET "scan_l<3>" LOC="p139";

## POSSIBLE VIVA QUESTION & ANSWER

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1. What is HDL?
Hardware description language is a computer aided design(CAD). Tool to design and
synthesis of digital system. HDL language is similar to language.

## 2. HDL language is similar to which language?

It is similar to C Language.

## 3. Justify the statement "Debugging the design is easy " in HDL.

Yes, because HDL packages implementation simulator & test benches

VHDL & Verilog

## 5. What is the abbreviation of VHDL?

VHDL means Very High Speed Integrated Circuit(VHSIC) hardware description
language.

## 6. What is the VHDL standard ?

The updated standard in 1993 is IEEE standard 1076-1993.

## 7. Write the general structure of VHDL model?

entity entity_name is
port(define input and output port);
architecture architecture_name is
begin
statements;
end architecture_name;

## 8. Write the general structure for verilog?

module modulename(input and output variable);
input......;
output......;
statement;
endmodule;

## 9. Which package is attached with VHDL program?

std_logic_1164 package is attached with VHDL program.

10. What is the Verilog HDL standard and who is maintaining it?
IEEE standard 1364-1995 is the verilog HDL standard and it is maintain by verilog
international organization.

11. In VHDL, what are the modes that the ports can take?
in, out, buffer, inout.

## 12. Explain the function of the modes of the port.

in-The port is only an i/p and appears only on the right hand side of the statement.

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out-The port is only an o/p and appears only on the left and right hand side of the
statement.
buffer-The port can be used as both i/p & o/p but should have only one source.
inout-The port can be used as both an i/p & o/p.

## 13. Explain the structure of the verilog module.

The verilog module has two parts, Declaration & Body.
Declaration- name, inputs and outputs of the module are listed.
Body-shows the relationship between the inputs & outputs.

## 14. Which of two Hardware Description Language is case Sensitive?

Verilog is case Sensitive.

## 15. How should the module be terminated in verilog?

The module is terminated by the predefined word end module.

## 16. What are the modes that exists in verilog ports?

input : The port is only an i/p Port.
output : The port is only an o/p Port.
inout : The port can be used as both an i/p and o/p.

## 17. How are the operators broadly classified?

Logical- AND,OR,XOR.
Relational =,=,<,<,>,>
Arithmetic +,-,*,
Shift to move the bits of an objects in a certain direction right or left.

## 18. State the different types of Logical Operators.

Logical Operators are AND, OR, NAND, NOR, NOT and Exclusive-OR.

## 19. Write the verilog bitwise logical operators.

AND - &, OR - |, NAND - ~(&), NOR - ~(|), EX-OR - ^, EX-NOR - ~ ^, NOT- ~.

## 20. What are Boolean Logical Operators, Give example.

The Boolean Logical operators operate on 2 operands, the result is Boolean 0 or 1.
Verilog Boolean logical operators are &&-AND Operator, ||-OR Operator.

## 21. What are Reduction Operators. Give examples.

The Reduction Opetators operate on a single Operand and the result is Boolean.

## & Reduction AND

| Reduction OR
~& Reduction NAND
~| Reduction NOR
^ Reduction XOR

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~^ Reduction XNOR
! Negation.

## 22. What are relational Operators. Give example.

Relational Operators are used to compare the values of two objects and the result is
Boolean 0 or 1, the VHDL relational operators are:
= Equality
/= Inequality
< Less than
<= Less than or equal
> Greater than
>= Greater than or equal.

23. What are Arithmetic Operators. State few arithmetic Operators in HDL?
Arithmetic Operators performs various operators like.
VHDL Arithmetic Operators Verilog Arithmetic Operators

- Subtraction - Subtraction
* Multiplication * Multiplication
/ Division / Division
Mod Modulus % Modulus
rem Remainder ** Exponent
abs absolute {,} Concatenate
** Exponent

## 24. What are shift & rotate operators?

Shift Left represents multiplication by 2.
Shift Right represents division by 2.
Example of VHDL shift operators.
ASll 1 - Shift A one position left logical.
ASrl 2 - Shift A two position right logical.
ASla 1 - Shift A one position left arithmetic.
ASla 2 - Shift A two position right arithmetic.
A rol 1 - Rotate A one position left.
A rol 1 - Rotate A one position right.
Verilog Shift Operators.
A<<1 Shift a one position left logical
A>>2 Shift a two position right.

## 25. What are the different types of VHDL data types?

The VHDL data types are broadly classified into 5 types.
1) Scalar Type - Bit type
Boolean
Integer
Real
Character

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Physical
User defined type
Severity type
2) Composite Type-Bit vector type
Array type
Record
3) Access Type
4) File Type
5) Other Types - Std_logic_type
Std_logic_vector type
Signed
Unsigned

## 26. What are the different types of data types in Verilog?

Nets, Registers, Vectors, Integers, Parameters, Real, Array.

## 27. What are the different styles of writing the description?

Behavioral, Structural, Switch level, Data flow, Mixed language.

## 28. What is Behavioral Description?

Behavioral description models the system as to how the o/p's behave with the i/p's. In
behavioral description the architecture includes predefined word process in VHDL and
always/initial Verilog module.

## 29. What is Structural Description?

Structural description model the system as component or gates.
Key word component is used in the architecture(VHDL) if gate construct.
In Verilog and, or, not is included in the module.

## 30. Explain what is Switch level description?

The system is described using switches or transistors. The verilog key words nmos, pmos,
cmos, transistors describes the system.

## 31. Explain what is data flow?

The data flow describes how the systems signal flows from the inputs to the outputs. The
description is done by writing the Boolean functions of the outputs.

## 32. What are the advantages of using mixed type description?

Mixed type description use more than one type or style of the previously mentioned
descriptions.

## 33. What is the function of data flow descriptions?

Data flow descriptions simulates the system by showing how the signa flows system
inputs to outputs.

## 34. How is signal assignment done in HDL?

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In VHDL the signal assignment operator <= is used & in verilog, the predefined word
assign is used.

## 35. How do you declare a constant in HDL?

A constant is VHDL is declared by using the predefined word constant and in verilog it is
declared by its type like time or integer.
To assign a value to a constant assignment operator
:=is used in VHDL & = in verilog.
36. Write a time delay signed assignment statement.
To assign a delay time to a signed - assigned statement the predefined word after is used
in VHDL & in Verilog it is # (Delay time).
Ex : S1 - sel and b after 10 nsec - VHDL.
assign # 10 S1=sel & b // Verilog.

## 37. Define Vector data types.

A vector is a data type that declares an array of similar elements such as to declare an
object that has a width of more than 1 bit.

38. What is the difference between syntax error and semantic error?
Syntax error is those that result from not following the rules of the language. it
terminates compilation of the program.
A semantic error is an error in the mechanics of the statement. it may not terminate the
program, but the outcome of the program may not be as expected.

## 39. What is the function of Behavioral Description?

The behavioral description describes the system by showing how the outputs behave
according to changes in its inputs. In behavioral description one need not know the logic
diagram of the system but one should know how the output behaves in response to
change in the output.

## 40. What are the two phase of execution in HDL?

The two phases of execution in HDL are Calculation and Assignment.

## 41. What do you mean by Sequential Calculation?

Sequential calculation means the calculation of a statement will not wait until the
proceeding statement is assigned only until the calculation is done.

42. Which are the Sequential statements that are assigned with behavioral description?
If statement, else-if, loop statements, for loop, forever, report, repeat, next-exit.

## 43. State the difference between signal and variable assignment.

A process is written based on signal assignment statements and then another process is
written based on variable assignment statements. The difference can be observed by the
simulation wave forms.

## 44. When do use loop statements and what is its advantage?

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Loops is used to repeat the execution of statements written inside the body. The number
of repetitions is controlled by the range of an index parameter. The loop allows the code
to be shortened.

## 45. When is Structural Description best suited?

It is best suited when the digital logic of the system hardware components is known.

## 46. What type of components are used in structural description?

Components can be gate level: AND, OR, NOT, XOR, XNOR gates. Components can be
of higher logic level such as Register Transfer Level (RTL) or processor level.

47. What type of statements are written in Structural Description and why?
Statements are “Concurrent “ in nature. At any simulation time, all statements that have
an event are executed concurrently.

## 48. Difference between VHDL & Verilog structural description.

Verilog recognizes all the primitive gates such as AND, OR, NOT, XOR, XNOR. Basic
VHDL packages do not recognize any gates unless the package is limited to one more
libraries, packages that have gate description.

## 49. List the verilog built-in gates.

BUFFER, NOT, AND, NAND, OR, NOR, XOR, XNOR.

## 50. Does VHDL have built-in gates.

No, VHDL does not have built-in gates.

## 51. What is Binding?

Binding is linking segment 1 in the code to segment 2 in the same code which makes
information in segment 2 visible to segment 1.

## (i) Binding between Entry and component in VHDL

(ii) Binding between library and module in VHDL.
(iii) Binding between library and component in VHDL.
(iv) Binding between two modules in verilog.

## 53. What are State Machines?

Synchronous sequential circuits are called “State Machines”.

## 54. What are the main components of State Machines.

Latches and Flip Flops. Additional combinational components may also be present.

## 55. Which are the two types of synchronous Sequential Circuits.

Mealy and Moore Circuits.

## 56. What is a Mealy Circuit?

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The output or next state of Mealy circuit depends on the inputs and the present state of
flip flops/latches.

## 57. What is Moore Circuit?

The output or next state of Moore circuit depends only on the present state. Present and
next states for particular flip-flops are the same output pin.

## 58. Define state diagram.

A diagram which shows transition between states.

## 59. What is a ‘Generate’ statement?

It is mainly used for repetition of concurrent statement.

60. Name the keyword used to define global constants in VHDL and Verilog.
Generic in VHDL and parameter in Verilog.

## 61. Disadvantage of structural description in VHDL.

(i) Structural description VHDL code looks much longer than the Verilog
code as it dose not have built-in libraries or packages for logical gates.
(ii) The description is not suited when the number of gates becomes larger.

## 62. What is Switch Level Description?

Switch Level Description implements Switches (transistors) to describe
relatively small-scale digital systems.

## 63. Application Area of Switch level description.

Very Large Scale Integrated (VLSI) Circuit layouts.

## 64. Disadvantages of Switch Level description.

(i) Only small-scale systems can be simulated using pure switch level
description.
(ii) If the system is not small, huge number of switches are needed that
may render simulation impractical.

## 65. Are built-in-switches statements present in Verilog. If Yes? What are

they?
Yes. They are Nmos, Pmos and Cmos.

## 66. Built-in Switches statement present in VHDL?

No, but to use these statements, user built packages must be developed.

## 67. What are strong Outputs?

The o/p is either the ground or the Vdd.

## 68. What is pmos Switches?

For a strong signal it should Pass1.

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69. What is nmos Switches?
For a strong signal it should Pass0.

## 70. What is cmos Switches?

The Switch which can pass both strong 1 and strong 0 is a Cmos Switch.

## 71. What are Bi-directional Switches?

Bi-directional Switches conduct in both ways from drain to source from
source to drain.

## 72. Application of Bi-directional Switches

Used as Bi-directional buffer(bunes).

## 73. List the three types of Bi-directional switches in Verilog.

Tran, Tranif 0, Tranif 1.
74. Operation of three types of Bi-directional Switches.
(i) Switch ‘Tran’ has no control. It conducts all the time.
(ii) Switch ‘Tranif 1’ conducts if control is 1,otherwise the o/p is put on
high impedance.
(iii) Switch ‘Tranif 0’ conducts if control is 0,otherwise the o/p is put on
High impedance.

## 75. What is a procedure Task and functions?

Procedure and task can have more than one i/p and more than o/p,
function have a single o/p,but can have more than one i/p.

## 76. Where do procedures and functions exits in VHDL?

They can be called only from within the ‘Process’.

## 77. Where do Task and functions exits in Verilog?

Task and function in Verilog can be called only from within ‘always’
or ‘initial’.

## 79. Define Procedure.

Procedure are VHDL sub programs.

## 80. Define Functions.

Functions are behavioural statements which must be called inside process
for VHDL or always or initial for Verilog.

(i) They optimize the style of writing HDL Code.
(ii) They shorten the code.

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82. Difference between VHDL and Verilog with reference to pocedure.
VHDL allows procedure calls to be written inside functions. Verilog
does not allow such calls.

## 83. List some of the functions available in VHDL packages.

(i) Mod : Finds modulesof X mod Y.
(ii) Abs : Finds the absolute value of a signed number.
(iii) To-INTEGER : Which return an integer value of a signed input.
(iv) To-INTEGER : Which takes an integer and returns its signed binary equivalents.

## 84. List the main characteristics of Procedures, Tasks and Functions.

The body of the procedure cannot include behavioural statement 'Process'.
The body of the task cannot include 'Always' or 'Initial', functions return a single output
with 'Return', a predefined word.
85. What is the necessity of Mixed - Type Description?
For best implementation of code in both behavioral and structural description.
Explanation with examples.
86. Mention some VHDL Pre-defined types.
Bit, Std_logic, array and natural.

## 87. Give few examples of User-Defined types.

Week days, weather or grades or classes.

## 88. Which is Pre-defined word used to instantiate a user defined types?

Type; Ex : Type week days is (Mon, Tue,Fri);

## 90. What is the advantage of Packages?

Packages allow the usesd to access built-in constructs.

## 91. Write Syntax for Package.

Package<Package Name>is
---------------------------------------
---------------------------------------
---------------------------------------
End<Package name>
Package body <Package name>is
---------------------------------------
---------------------------------------
--------------------------------------
End <Package name>

## 92. What is described in the body of the package?

The body of the packages contains the code for all the identifiers listed in the
declaration.

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93. Tone/Falls: VHDL allows for multi dimensional arrays but Verilog only allows single
dimensional arrays.

## 94. Write VHDL syntax for single dimensional array.

Type data vector is array(3 downto 0) of word array;
Sub type word array is Std_Logic_Vector(1 downto 0).

## 95. Give Syntax for verilog single dimensional array.

Reg[1:0] data vector[0:3]

File.

## 97. What is Port Direction?

Port Direction or mode of the file is nothing but the purpose of file i.e. input file or
output file. They are declared as infile or outfile.

## 98. What is Textio?

It is an IEEE packages used with the file handling programs.

## 100. Give an Example for implementation of File- Open.

File_Open (F Status, infile, “testfile.txt”, read_mode);

## 101. Write syntax to open a text outfile by t e name of HDL.txt?

File_Open (F Status, outfile, “HDL.txt”, write_mode);

## 102. What is Write line?

Write Line is Pre-Defined procedure that writes a line into an outfile that is open for
write mode.
Ex: Writeline(outfile, temp)

## 103. Mention the Built-in tasks for accessing a file Verilog?

\$fopen, \$fdisplay, \$fmonitor, \$fclose.

## 104. Explain the statement \$monitor(ch1,”%”,quantity);

The above task monitors the variable quantity and records its value in binary in the file
testfile.txt, indicator by Ch1;

105. Give Escape characters which can be used with monitor statement?
\ n, \t, \\, \”,\.

## 106. What is Record type?

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Record type is a collection of elements, the elements of which can be of the same type
or different types.

## 107. Why Mixed – Language Description?

one module.
For example : VHDL has more – Extensive file operations than verilog, including write
and read. By writing mixed – language, we can use the VHDL file operations in verilog
module.

## 108. What are the Limitations of Mixed – Language Descriptions?

1. Not all VHDL data types are supported in MLD.
2. The VHDL port type buffer is not supported.
3. Only a VHDL components constructs can invoke a Verilog module. We cannot
invoke a verilog module from any other construct in the VHDL Module.

## 109. Which data types of VHDL are supported for MLD?

Bit, Bit_Vector. Std_logic, Std_ulogic _vector and Std_ulogic_vector.

## 110. Is it possible to invoke procedure or function by verilog module?

No, A Verilog module can only invoke VHDL entity.
111. What is Synthesis?
Synthesis maps between the simulation (Software) domain and the hardware domain.

## 112. What information is carried from Entity and Module?

Provides informations on i/ps and o/ps and their types.

## 113. Write the Entity for figure1

Entity system is
port(a, b: in unsigned(3 downto 0);
d: out integer range(-10 to 10));
end system;

## 114. Write the Verilog code for figure2

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always @(x)
begin y = x;
end
endmodule

## 115. Write the Verilog code for figure3

always @(a, x)
begin
if(a==1’b1)
y=x;
else
y=1’b0;
end

QUESTION BANK

1a. Write and execute an VHDL / Verilog code to realize all logic gates and download to

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FPGA / CPLD with logic diagram and truth-table.
b. Write and execute an VHDL code to control the speed and direction of DC Motor.

2a. Write and execute an VHDL / Verilog code to realize 2:4 decoder and download to
FPGA / CPLD with logic diagram and truth-table.
b. Write and execute an VHDL code to display message on the given seven segment
displays accepting Hex key pad input data.

3a. Write and execute an VHDL / Verilog code to realize 8:3 encoder and download to
FPGA / CPLD with logic diagram and truth-table.
b. Write and execute an VHDL code to generate square waveform using DAC for different
frequency.

4a. Write and execute an VHDL / Verilog code to realize 8:1 MUX and download to
FPGA / CPLD with logic diagram and truth-table.
b. Write and execute an VHDL code to generate square waveform using DAC for different
frequency.

5a. Write and execute an VHDL / Verilog code to realize 4-bit Binary to Gray code converter
b. Write and execute an VHDL code to control the speed and direction of Stepper Motor.

6a. Write and execute an VHDL / Verilog code to realize 1:8 DEMUX and download to
FPGA / CPLD with logic diagram and truth-table.
b. Write and execute an VHDL code to generate triangular waveform using DAC.

7a. Write and execute an VHDL / Verilog code to realize N bit comparator and download to
FPGA / CPLD with logic diagram and truth-table.
b. Write and execute an VHDL code to control the speed and direction of DC Motor.

8a. Write and execute an VHDL / Verilog code to realize Full Adder using Behavioral
modeling and download to FPGA / CPLD with logic diagram and truth-table.
b. Write and execute an VHDL code to control the external lights using relays.

9a. Write and execute an VHDL / Verilog code to realize Full Adder using Structural
modeling and download to FPGA / CPLD with logic diagram and truth-table.
b. Write and execute an VHDL code the external lights using relays.

10a. Write and execute an VHDL / Verilog code to realize Full Adder using Data Flow
modeling and download to FPGA / CPLD with logic diagram and truth-table.
b. Write and execute an VHDL code the external lights using relays.

11a. Write and execute an VHDL / Verilog code to realize SR & D-FF and download to
FPGA / CPLD with logic diagram and truth-table.
b. Write and execute an VHDL code to generate square waveform using DAC for different
frequency.

12a. Write and execute an VHDL / Verilog code to realize JK FF and download to
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FPGA / CPLD with logic diagram and truth-table.
b. Write and execute an VHDL code to generate square waveform using DAC for different
frequency.

13a. Write and execute an VHDL / Verilog code to realize 4-bit Synchronous counter and
b. Write and execute an VHDL code the external lights using relays.

14a. Write and execute an VHDL / Verilog code to realize 4-bit Binary counter and
b. Write and execute an VHDL code to display message on the given seven segment
displays accepting Hex key pad input data.

15a. Write and execute an VHDL / Verilog code to realize 4-bit BCD counter and download
to FPGA / CPLD with logic diagram and truth-table.
b. Write and execute an VHDL code to control the speed and direction of DC Motor.

16a. Write and execute an VHDL / Verilog code to realize 4-bit ALU and download to
FPGA / CPLD with logic diagram and truth-table.
b. Write and execute an VHDL code to generate triangular waveform using DAC for
different frequency.
=====

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