COL215

DIGITAL LOGIC AND

SYSTEM DESIGN
•  Transmission Gate
•  Programmable Logic
15 October 2019
 Using NMOS / PMOS transistors as
switches (without PU/PD)
VDD VDD

G VDD G VGS = VDD - VA

VA VA
D S D S
Transistor remains ON Transistor cuts off if
VA is 0 VA rises above VDD - VT

VDD
G G VGS = 0 - VB
VB VB
D S D S
Transistor remains ON Transistor cuts off if
VB equals VDD VB falls below VT
Transmission Gate

e Same truth table as

G tri-state buffer
S
x y
D
e
e G
x y
e
symbol
Multiplexer

x0
s y
x1
Ex-OR Gate

b y

8 Transistors
Ex-OR without transmission gates

a.b’ + a’.b

3 NANDs + 2 inverters = 16 transistors

4 NANDs = 16 transistors a.ab + ab.b

AND-OR network + 3 inverters = 14 transistors
Ex-OR Gate with fewer transistors

a y

a b y
0 0 0
0 1 1
1 0 1
1 1 0
Ex-OR Gate with fewer transistors

a y

a b y
0 0 0?
0 1 1
1 0 1?
1 1 0
Ex-OR Gate with fewer transistors

a y

a b y
0 0 0?
b 0 1 1
a y 1 0 1?
b 1 1 0
Ex-OR Gate with fewer transistors

a y

a b y y
0 0 0? 0
b 0 1 1 Z
a y 1 0 1? 1
b 1 1 0 Z
Ex-OR Gate with fewer transistors

a y

a b y
0 0 0
b 0 1 1
a 1 0 1
b 1 1 0
Ex-OR Gate with fewer transistors

a y

a b y
0 0 0
0 1 1
1 0 1
1 1 0
PROGRAMMABLE
LOGIC
What is a Programmable Logic Module?

•  One that can be ‘programmed’ or

‘configured’

•  Two aspects
–  Universal / general logic structure
–  Technology for programming / configuring
Universal Logic Module (ULM)
•  For a given n, a circuit that can implement
any logic function of up to n variables

•  This is different from universality of NAND

and NOR gates
Multiplexer as a ULM
•  A 2n:1 multiplexer can implement any logic
function of up to n variables

a0
a1
f ai = 1, if mi is
a minterm of f
ap-1 = 0, if mi is not
p = 2n n a minterm of
x0 x1 . . . xn-1
Example
multiplexer inputs are wired to
constant 1’s and 0’s
x0 a0
0 1 0
a1
1
00 0 1 a2
1
a3
01 1 0 0
x2 x1 a4 f
0
11 1 1 a5
0
a6
10 0 0 1
a7
1
3
x0 x1 x2
A simplification
x0
0 1
00 0 1 00
01 1 0 01
x2 x1 x2 x1
11 1 1 11
10 0 0 10
A simplification
x0
0 1
00 0 1 00 x0
01 1 0 01
x2 x1 x2 x1
11 1 1 11
10 0 0 10
A simplification
x0
0 1
00 0 1 00 x0
01 1 0 01 x0
x2 x1 x2 x1
11 1 1 11
10 0 0 10
A simplification
x0
0 1
00 0 1 00 x0
01 1 0 01 x0
x2 x1 x2 x1
11 1 1 11 1
10 0 0 10
A simplification
x0
0 1
00 0 1 00 x0
01 1 0 01 x0
x2 x1 x2 x1
11 1 1 11 1
10 0 0 10 0
 A simplification
a0
x0

00 x0 a1
x0
01 x0 f
x2 x1 a2
11 1 0
10 0 a3
1
2
x2 x1
•  A 2n:1 multiplexer plus an inverter can implement
any logic function of up to n+1 variables
Another way
x0 x0
0 1 0 1
00 0 1
01 1 0
x2 x1
11 1 1
10 0 0
Another way
x0 x0
0 1 0 1
00 0 1 x1
01 1 0
x2 x1
11 1 1
10 0 0
Another way
x0 x0
0 1 0 1
00 0 1 x1 x1+ x2
01 1 0
x2 x1
11 1 1
10 0 0
 Another way

a0
x1
x0 a1 f
0 1 x1+ x2

x1 x1+ x2 x0

•  A 2n:1 multiplexer plus 2-input gates can

implement any logic function of up to n+2 variables
Shannon’s expansion
f (x0, x1, . . ,xi, . . , xn-1) =
xi .f (x0,x1, . . ,0, . . ,xn-1) + xi .f (x0,x1, . . ,1, . . ,xn-1)
= xi .fxi + xi .fxi


Co-factors of f w.r.t. xi and xi

This expansion can be repeated over the co-

factors using other variables

Limitations of multiplexer as a ULM
•  Number of inputs grows as 2n

•  For multiple output circuits, a separate

multiplexer is required for each output
Multiple output circuit
(2 input, 3 output)
a00 a10 a20
a01 a11 a21
f0 f1 f2
a02 a12 a22
a03 a13 a23
2 2 2
x1 x0 x1 x0 x1 x0
Simplification for multiple outputs
fi = (x1’. x0’. ai0) + (x1’. x0 . ai1) + (x1 . x0’. ai2) + (x1 . x0 . ai3)
= (d0 . ai0) + (d1 . ai1) + (d2 . ai2) + (d3 . ai3)

use a decoder with inputs x0, x1 and outputs d0, d1, d2, d3

Multiple outputs can share the decoder

f0 = (d0 . a00) + (d1 . a10) + (d2 . a20) + (d3 . a30)
f1 = (d0 . a01) + (d1 . a11) + (d2 . a21) + (d3 . a31)
f2 = (d0 . a02) + (d1 . a12) + (d2 . a22) + (d3 . a32)
Simplified multiple output circuit
(2 input, 3 output)
a00 a10 a20
a01 a11 a21
f0 f1 f2
a02 a12 a22
a03 a13 a23
Decoder d0
d1
d2
2 d3
x1 x0
Storing mux inputs in ‘Memory’

0
a0
1
a1
Memory with a2
1
fixed contents a3
0
or a4 f
Read Only Memory 0
a5
(ROM) 0
a6
1 a7
1 3
x2 x1 x0 address
Memory locations with multiple bits
Truth table
x2 x1 x0 f3 f2 f1 f0 4 a0
0 1 0 1
0 0 0 0 1 0 1 4 a1
1 1 0 1
4 a2
0 0 1 1 1 0 1 1 0 1 0
4 a3
0 1 0 1 0 1 0 0 0 0 1 4
4 a4 f
0 1 1 0 0 0 1 0 1 1 0
4 a5
1 0 0 0 1 1 0 0 1 0 1
4 a6
1 0 1 0 1 0 1 1 1 1 1 4 a
7
1 1 0 1 1 1 1 1 0 1 0 3
1 1 1 1 0 1 0 Look-up table x2 x1 x0
Scalability of mux / LUT approach
Having 2n min-terms / memory locations is
wasteful
n = 2 3 4 5 6 7 8 9
2n = 4 8 16 32 64 128 256 512

Solution : Have ‘product terms’, not min-terms
Question : Which product terms? How to keep
it universal?
Programmable Logic Array (PLA)

AND-plane product OR-plane

terms

a b c d x y z
Programmable Logic Array (PLA)

AND-plane product OR-plane

terms

a b c d x y z
Programmable Logic Array (PLA)
x = a’b’ + bc’d
y = a’c + b’d’
AND-plane z = a + bc’d OR-plane

a’b’
bc’d
a’c
a
b’d’

a b c d x’ y’ z’
Programmable Logic Array (PLA)
x = a’b’ + bc’d
y = a’c + b’d’
AND-plane z = a + bc’d OR-plane

a’b’
bc’d
a’c
a
b’d’

a b c d x’ y’ z’
Pull-up networks not shown
THANKS