DATASHEET

CA3240, CA3240A FN1050

Dual, 4.5MHz, BiMOS Operational Amplifier with MOSFET Input/Bipolar Output Rev 6.00
March 4, 2005

The CA3240A and CA3240 are dual versions of the popular Features
CA3140 series integrated circuit operational amplifiers. They
combine the advantages of MOS and bipolar transistors on • Dual Version of CA3140
the same monolithic chip. The gate-protected MOSFET • Internally Compensated
(PMOS) input transistors provide high input impedance and
• MOSFET Input Stage
a wide common-mode input voltage range (typically to 0.5V
- Very High Input Impedance (ZIN) 1.5T (Typ)
below the negative supply rail). The bipolar output
transistors allow a wide output voltage swing and provide a - Very Low Input Current (II) 10pA (Typ) at 15V
high output current capability. - Wide Common-Mode Input Voltage Range (VICR): Can
Be Swung 0.5V Below Negative Supply Voltage Rail
The CA3240A and CA3240 are compatible with the industry
• Directly Replaces Industry Type 741 in Most Applications
standard 1458 operational amplifiers in similar packages.
• Pb-Free Available (RoHS Compliant)
Ordering Information
TEMP. PKG. Applications
PART NUMBER RANGE (oC) PACKAGE DWG. #
• Ground Referenced Single Amplifiers in Automobile and
CA3240AE -40 to 85 8 Ld PDIP E8.3 Portable Instrumentation
CA3240AEZ -40 to 85 8 Ld PDIP E8.3 • Sample and Hold Amplifiers
(See Note) (Pb-free)
• Long Duration Timers/Multivibrators (Microseconds-
CA3240E -40 to 85 8 Ld PDIP E8.3 Minutes-Hours)
CA3240EZ -40 to 85 8 Ld PDIP E8.3 • Photocurrent Instrumentation
(See Note) (Pb-free)
• Intrusion Alarm System • Active Filters
Pb-free PDIPs can be used for through hole wave solder processing only.
They are not intended for use in Reflow solder processing applications. • Comparators • Function Generators
NOTE: Intersil Pb-free products employ special Pb-free material sets; • Instrumentation Amplifiers • Power Supplies
molding compounds/die attach materials and 100% matte tin plate termination
finish, which are RoHS compliant and compatible with both SnPb and Pb-free
soldering operations. Intersil Pb-free products are MSL classified at Pb-free
peak reflow temperatures that meet or exceed the Pb-free requirements of Pinout
IPC/JEDEC J STD-020.
CA3240, CA3240A (PDIP)
TOP VIEW
Functional Diagram
OUTPUT (A) 1 8 V+
2mA 4mA V+ INV.
INPUT (A) 2 7 OUTPUT
NON-INV. INV.
3 6 INPUT (B)
INPUT (A)
BIAS CIRCUIT
CURRENT SOURCES V- 4 5 NON-INV.
INPUT (B)
AND REGULATOR

200A 1.6mA 200A 2A 2mA

+
OUT-
PUT
IN- A  10 A  10,000 A1
PUT

-
C1

12pF V-

FN1050 Rev 6.00 Page 1 of 15

March 4, 2005
CA3240, CA3240A

Absolute Maximum Ratings Thermal Information

Supply Voltage (Between V+ and V-). . . . . . . . . . . . . . . . . . . . . 36V
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . (V+ +8V) to (V- -0.5V)
Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1mA
Output Short Circuit Duration (Note 1). . . . . . . . . . . . . . . . Indefinite
Thermal Resistance (Typical, Note 2) JA (oC/W)
8 Lead PDIP Package* . . . . . . . . . . . . . . . . . . . . . . 100
Maximum Junction Temperature (Plastic Package) . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC

Operating Conditions *Pb-free PDIPs can be used for through hole wave solder process-
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC ing only. They are not intended for use in Reflow solder processing
applications.
Voltage Range . . . . . . . . . . . . . . . . . . . . . 4V to 36V or 2V to 18V
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:
1. Short circuit may be applied to ground or to either supply. Temperatures and/or supply voltages must be limited to keep dissipation within max-
imum rating.
2. JA is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications For Equipment Design, VSUPPLY = 15V, TA = 25oC, Unless Otherwise Specified
CA3240 CA3240A
PARAMETER SYMBOL MIN TYP MAX MIN TYP MAX UNITS
Input Offset Voltage VIO - 5 15 - 2 5 mV
Input Offset Current IIO - 0.5 30 - 0.5 20 pA
Input Current II - 10 50 - 10 40 pA
Large-Signal Voltage Gain AOL 20 100 - 20 100 - kV/V
(See Figures 12, 27) (Note 3)
86 100 - 86 100 - dB
Common Mode Rejection CMRR - 32 320 - 32 320 V/V
Ratio (See Figure 17) 70 90 - 70 90 - dB
Common Mode Input Voltage Range VICR -15 -15.5 to 11 -15 -15.5 to 12 V
(See Figure24) +12.5 +12.5
Power Supply Rejection Ratio PSRR - 100 150 - 100 150 V/V
(See Figure 19) (VIO/V
76 80 - 76 80 - dB
Maximum Output Voltage (Note 4) VOM+ 12 13 - 12 13 - V
(See Figures 23, 24)
VOM- -14 -14.4 - -14 -14.4 - V
Maximum Output Voltage (Note 5) VOM- 0.4 0.13 - 0.4 0.13 - V
Total Supply Current I+ - 8 12 - 8 12 mA
(See Figure 15) For Both Amps
Total Device Dissipation PD - 240 360 - 240 360 mW
NOTES:
3. At VO = 26VP-P, +12V, -14V and RL = 2k.
4. At RL = 2k.
5. At V+ = 5V, V- = GND, ISINK = 200A.

Electrical Specifications For Equipment Design, VSUPPLY = 15V, TA = 25oC, Unless Otherwise Specified
TYPICAL VALUES
PARAMETER SYMBOL TEST CONDITIONS CA3240A CA3240 UNITS
Input Resistance RI 1.5 1.5 T
Input Capacitance CI 4 4 pF
Output Resistance RO 60 60 
Equivalent Wideband Input Noise Voltage eN BW = 140kHz, RS = 1M 48 48 V
(See Figure 2)

FN1050 Rev 6.00 Page 2 of 15

March 4, 2005
CA3240, CA3240A

Electrical Specifications For Equipment Design, VSUPPLY = 15V, TA = 25oC, Unless Otherwise Specified (Continued)
TYPICAL VALUES
PARAMETER SYMBOL TEST CONDITIONS CA3240A CA3240 UNITS
Equivalent Input Noise Voltage eN f = 1kHz, RS = 100 40 40 nV/Hz
(See Figure 18)
f = 10kHz, RS = 100 12 12 nV/Hz
Short-Circuit Current to Opposite Supply IOM+ Source 40 40 mA
IOM- Sink 11 11 mA
Gain Bandwidth Product (See Figures 13, 27) fT 4.5 4.5 MHz
Slew Rate (See Figure 14) SR 9 9 V/s
Transient Response (See Figure 1) tr RL = 2k, CL = 100pF Rise Time 0.08 0.08 s
OS RL = 2k, CL = 100pF Overshoot 10 10 %
Settling Time at 10VP-P (See Figure 25) tS AV = +1, RL = 2k, CL = 100pF, To 1mV 4.5 4.5 s
Voltage Follower
To 10mV 1.4 1.4 s
Crosstalk (See Figure 22) f = 1kHz 120 120 dB

Electrical Specifications For Equipment Design, at VSUPPLY = 15V, TA = -40 to 85oC, Unless Otherwise Specified
TYPICAL VALUES
PARAMETER SYMBOL CA3240A CA3240 UNITS
Input Offset Voltage |VIO| 3 10 mV
Input Offset Current (Note 8) |IIO| 32 32 pA
Input Current (Note 8) II 640 640 pA
Large Signal Voltage Gain (See Figures 12, 27), (Note 6) AOL 63 63 kV/V
96 96 dB
Common Mode Rejection Ratio (See Figure 17) CMRR 32 32 V/V
90 90 dB
Common Mode Input Voltage Range (See Figure 24) VICR -15 to +12.3 -15 to +12.3 V
Power Supply Rejection Ratio (See Figure 19) PSRR 150 150 V/V
(VIO/V) 76 76 dB
Maximum Output Voltage (Note 7) (See Figures 23, 24) VOM+ 12.4 12.4 V
VOM- -14.2 -14.2 V
Supply Current (See Figure 15) Total For Both Amps I+ 8.4 8.4 mA
Total Device Dissipation PD 252 252 mW
Temperature Coefficient of Input Offset Voltage VIO/T 15 15 V/oC
NOTES:
6. At VO = 26VP-P, +12V, -14V and RL = 2k.
7. At RL = 2k.
8. At TA = 85oC.

Electrical Specifications For Equipment Design, at V+ = 5V, V- = 0V, TA = 25oC, Unless Otherwise Specified
TYPICAL VALUES
PARAMETER SYMBOL CA3240A CA3240 UNITS
Input Offset Voltage |VIO| 2 5 mV
Input Offset Current |IIO| 0.1 0.1 pA
Input Current II 2 2 pA
Input Resistance RIN 1 1 T
Large Signal Voltage Gain (See Figures 12, 27) AOL 100 100 kV/V
100 100 dB

FN1050 Rev 6.00 Page 3 of 15

March 4, 2005
CA3240, CA3240A

Electrical Specifications For Equipment Design, at V+ = 5V, V- = 0V, TA = 25oC, Unless Otherwise Specified (Continued)
TYPICAL VALUES
PARAMETER SYMBOL CA3240A CA3240 UNITS
Common-Mode Rejection Ratio CMRR 32 32 V/V
90 90 dB
Common-Mode Input Voltage Range (See Figure 24) VICR -0.5 -0.5 V
2.6 2.6 V
Power Supply Rejection Ratio PSRR 31.6 31.6 V/V
90 90 dB
Maximum Output Voltage (See Figures 23, 24) VOM+ 3 3 V
VOM- 0.3 0.3 V
Maximum Output Current Source IOM+ 20 20 mA
Sink IOM- 1 1 mA
Slew Rate (See Figure14) SR 7 7 V/s
Gain Bandwidth Product (See Figure 13) fT 4.5 4.5 MHz
Supply Current (See Figure 15) I+ 4 4 mA
Device Dissipation PD 20 20 mW

Test Circuits and Waveforms

50mV/Div., 200ns/Div. 5V/Div., 1s/Div.

Top Trace: Input, Bottom Trace: Output Top Trace: Input, Bottom Trace: Output

FIGURE 1A. SMALL SIGNAL RESPONSE FIGURE 1B. LARGE SIGNAL RESPONSE

+15V

10k 0.1F
SIMULATED
+
LOAD
CA3240
- 2k
100pF
0.1F

-15V

2k BW (-3dB) = 4.5MHz

SR = 9V/s
0.05F

FIGURE 1C. TEST CIRCUIT

FIGURE 1. SPLIT-SUPPLY VOLTAGE FOLLOWER TEST CIRCUIT AND ASSOCIATED WAVEFORMS

FN1050 Rev 6.00 Page 4 of 15

March 4, 2005
CA3240, CA3240A

Test Circuits and Waveforms (Continued)

+15V

0.01F

RS
+
1M CA3240 NOISE
VOLTAGE
- OUTPUT

30.1k

0.01F
-15V

BW (-3dB) = 140kHz 1k

TOTAL NOISE VOLTAGE
(REFERRED TO INPUT) = 48V (TYP)

FIGURE 2. TEST CIRCUIT AMPLIFIER (30dB GAIN) USED FOR WIDEBAND NOISE MEASUREMENT

Schematic Diagram (One Amplifier of Two)

BIAS CIRCUIT INPUT STAGE SECOND STAGE OUTPUT STAGE DYNAMIC CURRENT SINK
V+

D1 D7 R13
15K
R9
Q2 Q20
Q1 Q3 50
R10 D8
Q19 1K
Q6 Q5 Q4 R12 R14
20K
R11 12K
20
Q7 Q17
Q21

R8
R1 Q8
8K 1K
OUTPUT
Q18
D2 D3 D4

D5

INVERTING
INPUT - Q9 Q10 C1
NON-INVERTING 12pF
INPUT + R3
R2 500
500 Q13 Q14 Q15 Q16

Q11 Q12 D6

R4 R5 R6 R7
500 500 50 30

V-

NOTES:
9. All resistance values are in ohms.

FN1050 Rev 6.00 Page 5 of 15

March 4, 2005
CA3240, CA3240A

Application Information
Circuit Description
The schematic diagram details one amplifier section of the
CA3240. It consists of a differential amplifier stage using PMOS
transistors (Q9 and Q10) with gate-to-source protection against
static discharge damage provided by zener diodes D3, D4, and
D5. Constant current bias is applied to the differential amplifier
from transistors Q2 and Q5 connected as a constant current
source. This assures a high common-mode rejection ratio. The
output of the differential amplifier is coupled to the base of gain
stage transistor Q13 by means of an NPN current mirror that
supplies the required differential-to-single-ended conversion.
The gain stage transistor Q13 has a high impedance active
load (Q3 and Q4) to provide maximum open-loop gain. The
collector of Q13 directly drives the base of the compound
emitter-follower output stage. Pulldown for the output stage is
provided by two independent circuits: (1) constant-current-
connected transistors Q14 and Q15 and (2) dynamic current-
sink transistor Q16 and its associated circuitry. The level of
pulldown current is constant at about 1mA for Q15 and varies
from 0 to 18mA for Q16 depending on the magnitude of the
voltage between the output terminal and V+. The dynamic
current sink becomes active whenever the output terminal is
more negative than V+ by about 15V. When this condition
exists, transistors Q21 and Q16 are turned on causing Q16 to
sink current from the output terminal to V-. This current always
flows when the output is in the linear region, either from the
load resistor or from the emitter of Q18 if no load resistor is
Input Circuit Considerations
As indicated by the typical VICR, this device will accept
inputs as low as 0.5V below V-. However, a series current-
limiting resistor is recommended to limit the maximum input
terminal current to less than 1mA to prevent damage to the
input protection circuitry.
Moreover, some current-limiting resistance should be
provided between the inverting input and the output when
the CA3240 is used as a unity-gain voltage follower. This
resistance prevents the possibility of extremely large input-
signal transients from forcing a signal through the input-
protection network and directly driving the internal constant-
current source which could result in positive feedback via the
output terminal. A 3.9k resistor is sufficient.
The typical input current is on the order of 10pA when the
inputs are centered at nominal device dissipation. As the
output supplies load current, device dissipation will increase,
raising the chip temperature and resulting in increased input
current. Figure 4 shows typical input-terminal current versus
ambient temperature for the CA3240.
V+ +HV
LOAD
CA3240
RL

present. The purpose of this dynamic sink is to permit the

output to go within 0.2V (VCE (sat)) of V- with a 2k load to
ground. When the load is returned to V+, it may be necessary
to supplement the 1mA of current from Q15 in order to turn on
RS
the dynamic current sink (Q16). This may be accomplished by LOAD
placing a resistor (Approx. 2k) between the output and V-. 120VAC
30V NO LOAD MT2
Output Circuit Considerations
Figure 23 shows output current-sinking capabilities of the
CA3240 at various supply voltages. Output voltage swing to
CA3240
the negative supply rail permits this device to operate both RL
MT1
power transistors and thyristors directly without the need for
level-shifting circuitry usually associated with the 741 series
of operational amplifiers.

Figure 3 shows some typical configurations. Note that a series FIGURE 3. METHODS OF UTILIZING THE VCE (SAT) SINKING
resistor, RL, is used in both cases to limit the drive available to CURRENT CAPABILITY OF THE CA3240 SERIES
the driven device. Moreover, it is recommended that a series
diode and shunt diode be used at the thyristor input to prevent
large negative transient surges that can appear at the gate of
thyristors, from damaging the integrated circuit.

FN1050 Rev 6.00 Page 6 of 15

March 4, 2005
CA3240, CA3240A
10K
VS =15V
INPUT CURRENT (pA)
1K
100
10
-60 -40 -20 0 20 40 60
TEMPERATURE (oC)
FIGURE 4. INPUT CURRENT vs TEMPERATURE
It is well known that MOSFET devices can exhibit slight
changes in characteristics (for example, small changes in
input offset voltage) due to the application of large
differential input voltages that are sustained over long
periods at elevated temperatures.
Both applied voltage and temperature accelerate these
changes. The process is reversible and offset voltage shifts
of the opposite polarity reverse the offset. In typical linear
applications, where the differential voltage is small and
symmetrical, these incremental changes are of about the
same magnitude as those encountered in an operational
amplifier employing a bipolar transistor input stage.
Typical Applications
On/Off Touch Switch
The on/off touch switch shown in Figure 5 uses the
CA3240E to sense small currents flowing between two
contact points on a touch plate consisting of a PC board
metallization “grid”. When the “on” plate is touched, current
flows between the two halves of the grid causing a positive
shift in the output voltage (Terminal 7) of the CA3240E.
These positive transitions are fed into the CA3059, which is
used as a latching circuit and zero-crossing TRIAC driver.
When a positive pulse occurs at Terminal 7 of the CA3240E,
the TRIAC is turned on and held on by the CA3059 and its
associated positive feedback circuitry (51k resistor and
36k/42k voltage divider). When the positive pulse occurs
at Terminal 1 (CA3240E), the TRIAC is turned off and held
off in a similar manner. Note that power for the CA3240E is
supplied by the CA3059 internal power supply.
The advantage of using the CA3240E in this circuit is that it
can sense the small currents associated with skin
conduction while allowing sufficiently high circuit impedance
to provide protection against electrical shock.
FN1050 Rev 6.00
March 4, 2005
Dual Level Detector (Window Comparator)
Figure 6 illustrates a simple dual liquid level detector using
the CA3240E as the sensing amplifier. This circuit operates
on the principle that most liquids contain enough ions in
solution to sustain a small amount of current flow between
two electrodes submersed in the liquid. The current, induced
by an 0.5V potential applied between two halves of a PC
board grid, is converted to a voltage level by the CA3240E in
a circuit similar to that of the on/off touch switch shown in
Figure 5. The changes in voltage for both the upper and
lower level sensors are processed by the CA3140 to activate
an LED whenever the liquid level is above the upper sensor
or below the lower sensor.
80 100 120 140
Constant-Voltage/Constant-Current Power Supply
The constant-voltage/constant-current power supply shown
in Figure 7 uses the CA3240E as a voltage-error and
current-sensing amplifier. The CA3240E is ideal for this
application because its input common-mode voltage range
includes ground, allowing the supply to adjust from 20mV to
25V without requiring a negative supply voltage. Also, the
ground reference capability of the CA3240E allows it to
sense the voltage across the 1 current-sensing resistor in
the negative output lead of the power supply. The CA3086
transistor array functions as a reference for both constant-
voltage and constant-current limiting. The 2N6385 power
Darlington is used as the pass element and may be required
to dissipate as much as 40W. Figure 8 shows the transient
response of the supply during a 100mA to 1A load transition.
Precision Differential Amplifier
Figure 9 shows the CA3240E in the classical precision
differential amplifier circuit. The CA3240E is ideally suited for
biomedical applications because of its extremely high input
impedance. To insure patient safety, an extremely high
electrode series resistance is required to limit any current
that might result in patient discomfort in the event of a fault
condition. In this case, 10M resistors have been used to
limit the current to less than 2A without affecting the
performance of the circuit. Figure 10 shows a typical
electrocardiogram waveform obtained with this circuit.
Page 7 of 15
CA3240, CA3240A

44M 10K (2W)

+6V 120V/220V
+6V RS (NOTE 10) AC
“ON” 51K 60Hz/50Hz
8
1M 36K 40W
5 12K
6 - 120V LIGHT
1/2 MT2
0.01F +6V CA3240 7 13 8
T2300B (NOTE 12)
5 + 1N914 9
5.1M CA3059
42K 10 G MT1

1M 11 4
“OFF” 3 + COMMON
1/2 7
CA3240 1
2
2 - 1N914
0.01F 1M +
4 +6V SOURCE 100F (16V)
-

44M

NOTE:
10. At 220V operation, TRIAC should be T2300D, RS = 18K, 5W.

FIGURE 5. ON/OFF TOUCH SWITCH

12M

+15V

8 0.1F
100K +15V
2 - 1/2
CA3240 1
+15V
3 + 7 0.1F
33K
240K 3 +
HIGH 160K
LEVEL (0.5V) CA3140 6
100K -
8.2K 680
2
5 + 100K 4 LED
1/2
100K CA3240 7
6 -
4
LED ON WHEN
LIQUID OUTSIDE
OF LIMITS
LOW
LEVEL 12M

FIGURE 6. DUAL LEVEL DETECTER

FN1050 Rev 6.00 Page 8 of 15

March 4, 2005
CA3240, CA3240A

VO
V+ IO
2N6385 2
10K
DARLINGTON 3 8

75
1/2
- 2
1 CA3240E 180K
3K
+ 3

1 4 + 500
100 - F
1N914
VI = 30V 2.7K
+ 100K
2000F 0.056F
- 50V 2.2K
82K
V+
10
2 + 5F 8
11 - 16V
1 100K 6 -
14 1/2
CA3240E 7
100K
CA3086E 9 12 5 +
3
TRANSISTOR 8
ARRAY 5 13
7 820 680K
1K 50K

4
6

6.2K

1
CHASSIS GROUND 100K
1W

VO RANGE = 20mV TO 25V OUTPUT HUM AND NOISE 150VRMS

LOAD REGULATION: (10MHz BANDWIDTH)
VOLTAGE <0.08% SINE REGULATION  0.1%/VO
CURRENT <0.05% IO RANGE = 10mA - 1.3A

FIGURE 7. CONSTANT-VOLTAGE/CONSTANT-CURRENT POWER SUPPLY

Top Trace: Output Voltage;

500mV/Div., 5s/Div.

Bottom Trace: Collector Of Load Switching Transistor

Load = 100mA to 1A; 5V/Div., 5s/Div.

FIGURE 8. TRANSIENT RESPONSE

FN1050 Rev 6.00 Page 9 of 15

March 4, 2005
CA3240, CA3240A

+15V

8 0.1F 100K 1%
10M
3 +
1/2
CA3240 1 2000pF
2 -
2000pF +15V

GAIN 1% 0.1F
7
CONTROL 100K 1% 5.1K
100K 2 OUTPUT
CA3140 6
3.9K 3 2K
100K 1% 5.1K
1% 4

TWO COND.
SHIELDED 2000pF 0.1F
CABLE 6 - -15V
1/2
CA3240 7
+ FREQUENCY RESPONSE (-3dB) DC TO 1MHz
5
SLEW RATE = 1.5V/s
10M
COMMON MODE REJ: 86dB
4
GAIN RANGE: 35dB TO 60dB

0.1F
-15V

FIGURE 9. PRECISION DIFFERENTIAL AMPLIFIER

Vertical: 1.0mV/Div.
Amplifier Gain = 100X
Scope Sensitivity = 0.1V/Div.

Horizontal: >0.2s/Div. (Uncal)

FIGURE 10. TYPICAL ELECTROCARDIOGRAM WAVEFORM

FN1050 Rev 6.00 Page 10 of 15

March 4, 2005
CA3240, CA3240A

0.015F

100K
+15V

8 +15V
2 -
+15V
1/2
CA3240E 1 2K 7
C30809 5.1K + 3
3 +
PHOTO 200K
DIODE 1.3 CA3140 6 OUTPUT
K
5
-
+ 2
13K 1/2 2K 4
CA3240E 7
6 -
-15V
4

C30809 -15V 200k

PHOTO
DIODE 100K

0.015F

FIGURE 11. DIFFERENTIAL LIGHT DETECTOR

Differential Light Detector

In the circuit shown in Figure 11, the CA3240E converts the
current from two photo diodes to voltage, and applies 1V of
reverse bias to the diodes. The voltages from the CA3240E
outputs are subtracted in the second stage (CA3140) so that
only the difference is amplified. In this manner, the circuit
can be used over a wide range of ambient light conditions
without circuit component adjustment. Also, when used with
a light source, the circuit will not be sensitive to changes in
light level as the source ages.

FN1050 Rev 6.00 Page 11 of 15

March 4, 2005
CA3240, CA3240A

Typical Performance Curves

RL = 2k RL = 2k

GAIN BANDWIDTH PRODUCT (MHz)

CL = 100pF
OPEN LOOP VOLTAGE GAIN (dB)

20
10

125
TA = -40oC TA = -40oC
100
25oC 25oC
75
85oC
85oC
50

25

1
0 5 10 15 20 25 0 5 10 15 20 25
SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V)

FIGURE 12. OPEN LOOP VOLTAGE GAIN vs SUPPLY VOLTAGE FIGURE 13. GAIN BANDWIDTH PRODUCT vs SUPPLY VOLT-
AGE

20 10
RL = 2k RL = 
CL = 100pF TOTAL SUPPLY CURRENT (mA) 9
25oC
15 8 TA = -40oC
SLEW RATE (V/s)

FOR BOTH AMPS

25oC 7 85oC

10 TA = -40oC 6

5
85oC
5 4

2
0
0 5 10 15 20 25 0 5 10 15 20 25
SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V)

FIGURE 14. SLEW RATE vs SUPPLY VOLTAGE FIGURE 15. QUIESCENT SUPPLY CURRENT vs SUPPLY VOLT-
AGE

120
SUPPLY VOLTAGE: VS = 15V
COMMON MODE REJECTION RATIO (dB)

SUPPLY VOLTAGE: VS = 15V

TA = 25oC TA = 25oC
25 100
OUTPUT VOLTAGE (VP-P)

20 80

15 60

10 40

5 20

0 0
10K 100K 1M 4M 101 102 103 104 105 106 107
FREQUENCY (Hz) FREQUENCY (Hz)

FIGURE 16. MAXIMUM OUTPUT VOLTAGE SWING vs FIGURE 17. COMMON MODE REJECTION RATIO vs
FREQUENCY FREQUENCY

FN1050 Rev 6.00 Page 12 of 15

March 4, 2005
CA3240, CA3240A

Typical Performance Curves (Continued)

1000
EQUIVALENT INPUT NOISE VOLTAGE (nV/Hz)

SUPPLY VOLTAGE: VS = 15V

POWER SUPPLY REJECTION RATIO (dB)

SUPPLY VOLTAGE: VS = 15V
TA = 25oC
TA = 25oC
100 POWER SUPPLY
REJECTION RATIO = VIO/ VS
RS = 100
100 80
+PSRR

60
-PSRR

10 40

20

1
1 101 102 103 104 105 101 102 103 104 105 106 107
FREQUENCY (Hz) FREQUENCY (Hz)

FIGURE 18. EQUIVALENT INPUT NOISE VOLTAGE vs FIGURE 19. POWER SUPPLY REJECTION RATIO vs
FREQUENCY FREQUENCY

TA = 25oC TA = 25oC
12 17.5
VS = 15V PER AMP (DOUBLE FOR BOTH) VS = 15V
OUTPUT SINK CURRENT (mA)

10 ONE AMPLIFIER OPERATING 15 RL = 

SUPPLY CURRENT (mA)

8 12.5
PER AMP

6 10

4 7.5

2 5

0 2.5
-15 -10 -5 0 5 10 15 -15 -10 -5 0 5 10 15
OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V)

FIGURE 20. OUTPUT SINK CURRENT vs OUTPUT VOLTAGE FIGURE 21. SUPPLY CURRENT vs OUTPUT VOLTAGE

1000
V- = 0V
OUTPUT STAGE TRANSISTOR (Q15, Q16)

TA = 25oC
TA = 25oC
140 AMP A  AMP B
AMP B  AMP A
SATURATION VOLTAGE (mV)

VS = 15V
130
VO = 5VRMS V+ = +5V
CROSSTALK (dB)

100 +15V
120 +30V

110

100 10

90

80 1.0
0.1 1 101 102 103 0.01 0.1 1.0 10
FREQUENCY (Hz) LOAD (SINKING) CURRENT (mA)

FIGURE 22. CROSSTALK vs FREQUENCY FIGURE 23. VOLTAGE ACROSS OUTPUT TRANSISTORS Q15
AND Q16 vs LOAD CURRENT

FN1050 Rev 6.00 Page 13 of 15

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CA3240, CA3240A

Typical Performance Curves (Continued)

RL = 
RL = 
0
REFERENCED TO TERMINAL V+(V)

REFERENCED TO TERMINAL V- (V)

OUTPUT VOLTAGE (+VO) 1.5
INPUT AND OUTPUT VOLTAGE

INPUT AND OUTPUT VOLTAGE

COMMON MODE VOLTAGE (+VICR) OUTPUT VOLTAGE (-VO)
-0.5 1.0 COMMON MODE VOLTAGE (-VICR)
-1 TA = 25oC 0.5
TA = -40oC TO 85oC
-1.5 TA = 85oC 0
TA = 85oC
TA = 85oC
-2 -0.5

-2.5 -1.0 TA = -40oC

TA = 25oC
-3 TA = 25oC -1.5
TA = -40oC TA = -40oC

0 5 10 15 20 25 0 5 10 15 20 25
SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V)

FIGURE 24A. FIGURE 24B.

FIGURE 24. OUTPUT VOLTAGE SWING CAPABILITY AND COMMON MODE INPUT VOLTAGE RANGE vs SUPPLY VOLTAGE

SUPPLY VOLTAGE: VS = 15V

TA = 25oC, RL = 2k, CL = 100pF
+15V
10
1mV 1mV
8 0.1F
10mV 10mV SIMULATED
INPUT VOLTAGE (V)

6 +
LOAD
10k CA3240
4
2
-
100pF 2k
FOLLOWER
0
INVERTING 0.1F
-2
-15V
-4
-6 1mV 1mV
2k
-8 10mV 10mV
-10 0.05F
2 4 6 8 2 4 6 8
0.1 1.0 10
TIME (s)

FIGURE 25A. SETTLING TIME vs INPUT VOLTAGE FIGURE 25B. TEST CIRCUIT (FOLLOWER)

5k

+15V

5k 0.1F
- SIMULATED
LOAD
CA3240
200 +
100pF 2k

0.1F
4.99k -15V 5.11k

SETTLING POINT
D1 D2
1N914 1N914

FIGURE 25C. TEST CIRCUIT (INVERTING)

FIGURE 25. INPUT VOLTAGE vs SETTLING TIME

FN1050 Rev 6.00 Page 14 of 15

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CA3240, CA3240A

Typical Performance Curves (Continued)

10K VS = 15V -75

VS = 15V TA = 25oC -90
RL = 2k,

OPEN LOOP VOLTAGE GAIN (dB)

OPEN LOOP PHASE (DEGREES)

100 CL = 0pF -105
PHASE
1K -120
INPUT CURRENT (pA)

80 -135
RL = 2k,
CL = 100pF -150
100 60
GAIN

40
10
20

1 0
-60 -40 -20 0 20 40 60 80 100 120 140 101 102 103 104 105 106 107 108
TEMPERATURE (oC) FREQUENCY (Hz)

FIGURE 26. INPUT CURRENT vs TEMPERATURE FIGURE 27. OPEN LOOP VOLTAGE GAIN AND PHASE vs
FREQUENCY

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FN1050 Rev 6.00 Page 15 of 15

March 4, 2005