Nvis-8085-V1mp Kit

Nvis 5585 8085 Microprocessor Trainer
8085 Microprocessor Trainer

Nvis 5585
Learning Material
Ver 1.2
Nvis 5585
8085 Microprocessor Trainer
Table of Contents
1. Introduction 3
2. Technical Specifications 4
3. Safety Instructions 5
4. Theory 6
5. Capabilities 22
6. Installation 23
7. Hardware Description 24
8. Keyboard Command Description 26
9. Microprocessor Lab Software 40
10. Serial Command Description 46
11. Xassembler 52
12. 8085 Instruction Set 58
13. Hardware Interrupt 64
14. Software Interrupt 66
15. Memory/IO Mapping 67
16. Subroutines 77
17. Sample Programs 79
18. Connectors Details 104
19. Jumper Details 107
20. Frequently Asked Questions 108
21. Warranty & Check list 117
22. References 118
2
Introduction
General Description:
Nvis 5585 is a single board Microprocessor Training based on 8085
Microprocessor, which is widely used to train engineers to develop
software/hardware for any industrial process & control.
Nvis 5585 provides powerful monitor EPROM & user's RAM. The trainer has 28
keys Hexadecimal Keyboard and six digit seven segment display for any data entry
display. The trainer also has the capability of interacting with PC (COMPUTER)
through RS-232C Serial Communication Link.
The Input /Output structure of Nvis 5585 provides 24 programmable I/O lines using
8255 and 22 Programmable I/O lines using 8155. It has got 16 bit 3 channel
programmable Timer/Counter using 8253.
The on board residents system monitor software is very powerful and provides
various software utilities like INSERT, DELETE, BLOCK MOVE, RELOCATE,
FILL & MEMORY COMPARE etc. which are very helpful in debugging/developing
the software.
The bus of the CPU is available on 50 pin FRC connector which can be used to
connect other systems through bus.
3
Technical Specifications
CPU : 8 bit Microprocessor, the 8085.
Monitor EPROM : 8K bytes of EPROM loaded with powerful monitor
program.
RAM : 8K bytes of user's RAM using 6264 expandable up
to 64K.
Timer : 16 bit programmable timer/counter using 8253.
I/O : 24 I/O lines using 8255 22 I/O lines using 8155
Keyboard : 8 Hex Key pad consist of 10 keys for command 16
keys for hexadecimal data entry 1 key for Reset & 1
key for RST 7.5 VCT.
Display : 6 Digit Seven Segment Displays (4 for address field
& 2 for data field)
Bus : All data address and control signals (TTL
compatible) available at 50 Pin FRC connector
Serial Interface : RS-232C serial interface through SID/SOD line.
Power Supply : +5V/1A & ±12V/250mA.
Physical Size : 32.7cm x 25.33cm.
Operating Temperature : 0 to 50°C.
Included Accessories
26 Pin FRC Cable……………………………………………………2 Nos.
50 Pin FRC Cable …………………………………………………...1 No.
10 Pin FRC Cable……………………………………………………1 No.
RS232 Cable…………………………………………………………1 No.
Mains Cord…………………………………………………………...1 No.
Jumper………………………………………………………………..1 No.
Phoenix Cable………………………………………………………..1 No
4
Safety Instructions
Read the following safety instructions carefully before operating the instrument. To
avoid any personal injury or damage to the instrument or any product connected to
the instrument.
Do not operate the instrument if suspect any damage to it.
The instrument should be serviced by qualified personnel only.
For your safety:
Use proper Mains cord : Use only the mains cord designed for this
instrument Ensure that the mains cord is suitable for
your country.
Ground the Instrument : This instrument is grounded through the
protective earth conductor of the mains cord. To
avoid electric shock, the grounding conductor
must be connected to the earth ground. Before
making connections to the input terminals,
ensure that the instrument is properly grounded..
Use in proper Atmosphere : Please refer to operating conditions given in the
manual.
1. Do not operate in wet / damp conditions.
2. Do not operate in an explosive atmosphere.
3. Keep the product dust free, clean and dry
5
Theory
The 8085 microprocessor is an eight bit general purpose processor. It is a
conventional Von Neumann type computer design that uses binary numbers as
information storage. A binary number consists only as ones and zero. A bit 1 is
represented by about +5 volts at about
0.02 watt, and a binary zero is represented by a voltage of less than +0.8 volt. It was
first made by Intel in 1977. Its main advantages are its small size, fast calculation
speed, relatively low electrical power consumption, requires less hardware, has only
about 256 instructions for easier assembler construction, and low cost. It has a 16 bit
address bus. The circuit uses miniature electronic components called transistors
(metal-oxide semiconductor), diodes and resistors to form logic gates. Logic gates
can be combined to form electronic temporary memory circuits called registers in the
8085. There are advantages of making your own operating system software; these are:
full and guaranteed control of your computer system, less software crashes (failures),
no back doors to possible malware, high speed calculations, and better security for
safety.
The main features of 8085 microprocessor are:

· It is an 8 bit microprocessor.
· It is manufactured with N-MOS technology.
· It has 16-bit address bus and hence can address up to 2 = 65536 bytes (64KB)
memory locations through A -A .0 15
· The first 8 lines of address bus and 8 lines of data bus are multiplexed AD0 –D7
· Data bus is a group of 8 lines D0 – D7 . It supports external interrupt request. A

16 bit program counter (PC)
· A 16 bit stack pointer (SP)
· Six 8-bit general purpose register arranged in pairs: BC, DE, HL.
· It requires a signal +5V power supply and operates at 3.2 MHZ single phase
clock. It is enclosed with 40 pins DIP (Dual in line package).
· Single + 5V Supply
· 4 Vectored Interrupts (One is Non Maskable) Serial In/Serial Out Port
· Decimal, Binary, and Double Precision Arithmetic
6
8085 Architecture
Control Unit
Generates signals within microprocessor to carry out the instruction, which has been
decoded. In reality causes certain connections between blocks of the microprocessor
to be opened or closed, so that data goes where it is required, and so that ALU
operations occur.
Arithmetic Logic Unit
The ALU performs the actual numerical and logic operation such as „add‟,
„subtract‟, „AND‟, „OR‟, etc. The ALU uses data from memory and from
Accumulator to perform arithmetic. Always stores result of operation in Accumulator
7
Registers
The 8085/8080A-programming model includes six registers, one accumulator, and
one flag register, as shown in Figure. In addition, it has two 16-bit registers: the stack
pointer and the program counter. They are described briefly as follows. The
8085/8080A has six general-purpose registers to store 8-bit data; these are identified
as B, C, D, E, H and L as shown in the figure. They can be combined as register pairs
- BC, DE, and HL - to perform some 16-bit operations. The programmer can use
these registers to store or copy data into the registers by using data copy instructions
Accumulator
The accumulator is an 8-bit register that is a part of arithmetic/logic unit (ALU). This
register is used to store 8-bit data and to perform arithmetic and logical operations.
The result of an operation is stored in the accumulator. The accumulator is also
identified as register A.
Flags
The ALU includes five flip-flops, which are set or reset after an operation according
to data conditions of the result in the accumulator and other registers. They are called
Zero (Z), Carry (CY), Sign (S), Parity (P), and Auxiliary Carry (AC) flags; their bit
positions in the flag register are shown in the Figure below. The most commonly used
flags are Zero, Carry, and Sign. The microprocessor uses these flags to test data
conditions. For example, after an addition of two numbers, if the sum in the
accumulator id larger than eight bits, the flip-flop uses to indicate a carry, called the
Carry flag (CY), is set to one. When an arithmetic operation results in zero, the flip-
flop called the Zero (Z) flag is set to one. However, it is not used as a register; five bit
positions out of eight are used to store the outputs of the five flip-flops. The flags are
stored in the 8-bit register so that the programmer can examine these flags (data
conditions) by accessing the register through an instruction. These flags have critical
importance in the decision-making process of the microprocessor. The conditions (set
or reset) of the flags are tested through the software instructions. For example, the
instruction JC (Jump on Carry) is implemented to change the sequence of a program
when CY flag is set. The thorough understanding of flag is essential in writing
assembly language programs.
8
Flag Register
Program Counter (PC)
This 16-bit register deals with sequencing the execution of instructions. This register
is a memory pointer. Memory locations have 16-bit addresses, and that is why this is
a 16-bit register. The microprocessor uses this register to sequence the execution of
the instructions. The function of the program counter is to point to the memory
address from which the next byte is to be fetched. When a byte (machine code) is
being fetched, the program counter is incremented by one to point to the next memory
location
Stack Pointer (SP)
The stack pointer is also a 16-bit register used as a memory pointer. It points to a
memory location in R/W memory, called the stack. The beginning of the stack is
defined by loading 16-bit address in the stack pointer.
Instruction Register/Decoder
Temporary store for the current instruction of a program. Latest instruction sent here
from memory prior to execution. Decoder then takes instruction and „decodes or
interprets the instruction. Decoded instruction then passed to next stage.
8085 System Bus
Typical system uses a number of busses, collection of wires, which transmit binary
numbers, one bit per wire. A typical microprocessor communicates with memory and
other devices (input and output) using three busses: Address Bus, Data Bus and
Control Bus.
9
Address Bus
One line for each bit, therefore 16 bits = 16 lines. Binary number carried alerts
memory to open the designated box. Data (binary) can then be put in or taken out.
The Address Bus consists of 16 lines, therefore 16 bits. Its "width" is 16 bits. A 16 bit
binary number allows addressing from 0000000000000000 to 1111111111111111.
To communicate with memory the microprocessor sends an address on the address
bus, e.g. 0000000000000011 (3 in decimal), to the memory. The memory selects that
address location for reading or writing data. Address bus is unidirectional, i.e.
numbers only sent from microprocessor to memory, not other way.
Data Bus
The Data bus is a group of eight lines used for data transfer. These lines are
bidirectional. The eight data lines enable the microprocessor unit to manipulate 8-bit
data ranging from 00 to FF (28 = 256 numbers).
Data Bus carries data, in binary form, between microprocessor and other external
units, such as memory. Data bus used to transmit "data", i.e. information, results of
arithmetic, etc, between memory and the microprocessor. Size of the data bus
determines what arithmetic can be done. If only 8 bits wide then largest number is
11111111 (255 in decimal). Therefore, larger number has to be broken down into
chunks of 255. This slows microprocessor. Data Bus also carries instructions from
memory to the microprocessor. Size of the bus therefore limits the number of possible
instructions to 256, each specified by a separate number.
Control Bus
The Control Bus is comprised of various single lines that carry synchronization
signals. The microprocessor uses such lines to perform the third function: providing
timing signals. The microprocessor generates specific control signals for every
operation it performs. These signals are used to identify a device type with which the
microprocessor intends to communicate.
To communicate with a memory: for example, to read an instruction from a memory
location- the microprocessor places the 16-bit address on the address bus. The address
on the bus is decoded by an external logic circuit and the memory location is
identified. The microprocessor sends a pulse called Memory Read as the control
signal. The pulse activates the memory chip, and the contents of the memory location
(8-bit data) are placed on the data bus and brought inside the microprocessor.
8085 Pin Description
The Intel 8085A is a new generation, complete 8 bit parallel central processing unit
(CPU). The 8085A uses a multiplexed data bus. The address is split between the 8bit
address bus and the 8bit data bus
10
The following describes the function of each pin:

A6 - A15 (Output 3 States) Address Bus:
The most significant 8 bits of the memory address or the 8 bits of the I/O address, 3
stated during Hold and Halt modes.
AD0 - 7 (Input/output 3 States) Multiplexed Address/Data Bus:
Lower 8 bits of the memory address (or I/O address) appear on the bus during the first
clock cycle of a machine state. It then becomes the data bus during the second and
third clock cycles. 3 stated during Hold and Halt modes
ALE (Output) Address Latch Enable:
It occurs during the first clock cycle of a machine state and enables the address to get
latched into the on chip latch of peripherals. The falling edge of ALE is set to
guarantee setup and hold times for the address information. ALE can also be used to
strobe the status information. ALE is never 3stated.
11
S0, S1 (Output) Data Bus Status:
Encoded status of the bus cycle:
S1 S0
0 0 Halt
0 1 Write
1 0 Read
1 1 Fetch
S1 can be used as an advanced R/W status.

RD (Output 3state) Read:
It indicates the selected memory or 1/0 device is to be read and that the Data Bus is
available for the data transfer.
WR (Output 3state) Write:
It indicates the data on the Data Bus is to be written into the selected memory or I/O
location. Data is set up at the trailing edge of WR. 3 stated during Hold and Halt
modes.
READY (Input):
If Ready is high during a read or write cycle, it indicates that the memory or
peripheral is ready to send or receive data. If Ready is low, the CPU will wait for
Ready to go high before completing the read or write cycle.
HOLD (Input) Hold:
It indicates that another Master is requesting the use of the Address and Data Buses.
The CPU, upon receiving the Hold request, will relinquish the use of buses as soon as
the completion of the current machine cycle. Internal processing can continue. The
processor can regain the buses only after the Hold is removed. When the Hold is
acknowledged, the Address, Data, RD, WR, and IO/M lines are 3stated.
HLDA (Output) Hold Acknowledge:
It indicates that the CPU has received the Hold request and that it will relinquish the
buses in the next clock cycle. HLDA goes low after the Hold request is removed. The
CPU takes the buses one half clock cycle after HLDA goes low.
INTR (Input) Interrupt Request:
It is used as a general purpose interrupt. It is sampled only during the next to the last
clock cycle of the instruction. If it is active, the Program Counter (PC) will be
inhibited from incrementing and an INTA will be issued. During this cycle a
RESTART or CALL instruction can be inserted to jump to the interrupt service
routine. The INTR is enabled and disabled by software. It is disabled by Reset and
immediately after an interrupt is accepted.
12
INTA (Output) Interrupt Acknowledge:
It is used instead of (and has the same timing as) RD during the Instruction cycle after
an INTR is accepted. It can be used to activate the 8259 Interrupt chip or some other
interrupt port.
Restart Interrupts (RST 5.5, RST 6.5 - (Inputs), RST 7.5):
These three inputs have the same timing as INTR except they cause an internal
RESTART to be automatically inserted.
RST 7.5 (Highest Priority) RST 6.5
RST 5.5 (Lowest Priority)
The priority of these interrupts is ordered as shown above. These interrupts have a
higher priority than the INTR.
TRAP (Input):
Trap interrupt is a non-maskable restart interrupt. It is recognized at the same time as
INTR. It is unaffected by any mask or Interrupt Enable. It has the highest priority of
any interrupt.
RESET IN (Input):
Reset sets the Program Counter to zero and resets the Interrupt Enable and HLDA
flip- flops. None of the other flags or registers (except the instruction register) are
affected The CPU is held in the reset condition as long as Reset is applied.
RESET OUT (Output):
It can be used as a system RESET. The signal is synchronized to the processor clock.
X1, X2 (Input):
Crystal or R/C network connections to set the internal clock generator X1 can also be
an external clock input instead of a crystal. The input frequency is divided by 2 to
give the internal operating frequency.
CLK (Output):
Clock Output for use as a system clock when a crystal or RC network is used as an
input to the CPU. The period of CLK is twice the X1, X2 input period.
IO/M (Output):
IO/M indicates whether the Read/Write is to memory or I/O Tristated during Hold
and Halt modes.
SID (Input) Serial input data line:
The data on this line is loaded into accumulator bit 7 whenever a RIM instruction is
executed.
13
SOD (Output) Serial output data line:
The output SOD is set or reset as specified by the SIM instruction
Vcc: +5 volt supply
Vss: Ground Reference
8085 Functional Description
The 8085A is a complete 8-bit parallel central processor. It requires a single +5 volt
supply. Its basic clock speed is 3 MHz thus improving on the present 8080's
performance with higher system speed. Also it is designed to fit into a minimum
system of three IC's: The CPU, a RAM/ IO, and a ROM or PROM/IO chip. The
8085A uses a multiplexed Data Bus. The address is split between the higher 8-bit
Address Bus and the lower 8-bit Address/Data Bus. During the first cycle the address
is sent out. The lower 8-bits are latched into the peripherals by the Address Latch
Enable (ALE). During the rest of the machine cycle the Data Bus is used for memory
or l/O data.
The 8085A provides RD, WR, and IO/Memory signals for bus control. An Interrupt
Acknowledge signal (INTA) is also provided. Hold, Ready, and all Interrupts are
synchronized. The 8085A also provides serial input data (SID) and serial output data
(SOD) lines for simple serial interface.
In addition to these features, the 8085A has three maskable, restart interrupts and one
non- maskable trap interrupt. The 8085A provides RD, WR and IO/M signals for Bus
control.
Status Information
Status information is directly available from the 8085A. ALE serves as a status
strobe. The status is partially encoded, and provides the user with advanced timing of
the type of bus transfer being done. IO/M cycle status signal is provided directly also.
Decoded So, S1 Carries the following status information:
HALT, WRITE, READ, FETCH
S1 can be interpreted as R/W in all bus transfers. In the 8085A the 8 LSB of address
are multiplexed with the data instead of status. The ALE line is used as a strobe to
enter the lower half of the address into the memory or peripheral address latch. This
also frees extra pins for expanded interrupt capability.
Interrupt and Serial l/O
The 8085A has 5 interrupt inputs: INTR, RST5.5, RST6.5, RST 7.5, and TRAP.
INTR is identical in function to the 8080 INT. Each of the three RESTART inputs,
5.5, 6.5. 7.5, has a programmable mask. TRAP is also a RESTART interrupt except it
is non-maskable. The three RESTART interrupts cause the internal execution of RST
(saving the program counter in the stack and branching to the RESTART address) if
the interrupts are enabled and if the interrupt mask is not set. The non-maskable
TRAP causes the internal execution of a RST independent of the state of the interrupt
enable or masks.
14
The interrupts are arranged in a fixed priority that determines which interrupt is to be
recognized if more than one is pending as follows: TRAP highest priority, RST 7.5,
RST 6.5, RST 5.5, INTR lowest priority. This priority scheme does not take into
account the priority of a routine that was started by a higher priority interrupt. RST
5.5 can interrupt a RST 7.5 routine if the interrupts were re-enabled before the end of
the RST 7.5 routine. The TRAP interrupt is useful for catastrophic errors such as
power failure or bus error. The TRAP input is recognized just as any other interrupt
but has the highest priority. It is not affected by any flag or mask. The TRAP input is
both edge and level sensitive.
Basic System Timing
The 8085A has a multiplexed Data Bus. ALE is used as a strobe to sample the lower
8-bits of address on the Data Bus. Note that during the l/O write and read cycle that
the I/O port address is copied on both the upper and lower half of the address. As in
the 8080, the READY line is used to extend the read and write pulse lengths so that
the 8085A can be used with slow memory. Hold causes the CPU to relinquish the bus
when it is through with it by floating the Address and Data Buses.
System Interface
8085A family includes memory components, which are directly compatible to the
8085A CPU. For example, a system consisting of the three chips, 8085A, 8156, and
8355 will have the following features:
2K Bytes ROM 256 Bytes RAM
1 Timer/Counter Four 8-bit l/O Ports 16-bit l/O Port
4 Interrupt Levels
Serial In/Serial Out Ports
In addition to standard I/O, the memory mapped I/O offers an efficient I/O addressing
technique. With this technique, an area of memory address space is assigned for I/O
address, thereby, using the memory address for I/O manipulation. The 8085A CPU
can also interface with the standard memory that does not have the multiplexed
address/data bus.
The 8085 Programming Model
The 8085 programming model includes six registers, one accumulator, and one flag
register, as shown in Figure. In addition, it has two 16-bit registers: the stack pointer
and the program counter. They are described briefly as follows.
Registers
The 8085 has six general-purpose registers to store 8-bit data; these are identified as
B, C, D, E, H, and L. They can be combined as register pairs - BC, DE, and HL - to
perform some 16-bit operations. The programmer can use these registers to store or
copy data into the registers by using data copy instructions.
15
Accumulator
The accumulator is an 8-bit register that is a part of arithmetic/logic unit (ALU). This
register is used to store 8-bit data and to perform arithmetic and logical operations.
The result of an operation is stored in the accumulator. The accumulator is also
identified as register A. The ALU includes five flip-flops, which are set or reset after
an operation according to data conditions of the result in the accumulator and other
registers. They are called Zero (Z), Carry (CY), Sign (S), Parity (P), and Auxiliary
Carry (AC) flags; their bit positions in the flag register are shown in the Figure below.
The most commonly used flags are Zero, Carry, and Sign. The microprocessor uses
these flags to test data conditions.
For example, after an addition of two numbers, if the sum in the accumulator id larger
than eight bits, the flip-flop uses to indicate a carry, called the Carry flag (CY) is set
to one
When an arithmetic operation results in zero, the flip-flop called the Zero (Z) flag is
set to one. The first Figure shows an 8-bit register, called the flag register, adjacent to
the accumulator. However, it is not used as a register; five bit positions out of eight
are used to store the outputs of the five flip-flops. The flags are stored in the 8-bit
register so that the programmer can examine these flags (data conditions) by
accessing the register through an instruction. These flags have critical importance in
the decision-making process of the microprocessor. The conditions (set or reset) of
the flags are tested through the software instructions. For example, the instruction JC
(Jump on Carry) is implemented to change the sequence of a program when CY flag
is set. The thorough understanding of flag is essential in writing assembly language
programs. Program Counter (PC) This 16-bit register deals with sequencing the
execution of instructions. This register is a memory pointer. Memory locations have
16-bit addresses, and that is why this is a 16-bit register.
The microprocessor uses this register to sequence the execution of the instructions.
The function of the program counter is to point to the memory address from which
the next byte is to be fetched. When a byte (machine code) is being fetched, the
program counter is incremented by one to point to the next memory location Stack
Pointer (SP) The stack pointer is also a 16-bit register used as a memory pointer. It
points to a memory location in R/W memory, called the stack. The beginning of the
stack is defined by loading 16-bit address in the stack pointer.
The 8085 Addressing Modes
The instructions MOV B, A or MVI A, 82H are to copy data from a source into a
destination. In these instructions the source can be a register, an input port, or an 8-bit
number (00H to FFH). Similarly, a destination can be a register or an output port. The
sources and destination are operands. Addressing modes are the manner of specifying
effective address. 8085 Addressing mode can be classified into:
1. Immediate addressing
2. Register addressing
3. Direct addressing
4. Indirect addressing
16
Immediate addressing:
The instruction contains the data itself. Load the immediate data to the destination
provided. This is either an 8 bit quantity or 16 bit (the LSB first and the MSB is the
second) Example:
MVI A, 28H LXI H, 2000H
First instruction loads the Accumulator with the 8-bit immediate data 28H Second
instruction loads the HL register pair with 16-bit immediate data 2000H
Register addressing:
Data is provided through the registers. The instruction specifies the register or register
pair in which the data is located.
Ex:
MOV Rd, Rs
MOV A, B Here the content of B register is copied to the Accumulator
Direct addressing:
It is used to accept data from outside devices to store in the accumulator or send the
data stored in the accumulator to the outside device. The instruction consist of three
byte, byte for the Opcode of the instruction followed by two bytes represent the
address of the operand Low order bits of the address are in byte 2 High order bits of
the address are in byte 3.
Example:
LDA 2000H
This instruction load the Accumulator is loaded with the 8-bit content of memory
location [2000H].
IN 00H or OUT 01H
Accept the data from the port 00H and store them into the accumulator or Send the
data from the accumulator to the port 01H.
Indirect Addressing:
The instruction specifies a register pair which contains the memory address where the
data is located. Ex. MOV M, A Here the HL register pair is used as a pointer to
memory location. The content of Accumulator is copied to that location. This means
that the Effective Address is calculated by the processor. And the contents of the
address (and the one following) are used to form a second address. The second
address is where the data is stored. Note that this requires several memory accesses;
two accesses to retrieve the 16-bit address and a further access (or accesses) to
retrieve the data which is to be loaded into the register.
17
Instruction Set Classification
An instruction is a binary pattern designed inside a microprocessor to perform a
specific function. The entire group of instructions, called the instruction set,
determines what functions the microprocessor can perform. These instructions can be
classified into the following five functional categories: data transfer (copy)
operations, arithmetic operations, logical operations, branching operations, and
machine-control operations.
1. Data Transfer (Copy) Operations
This group of instructions copy data from a location called a source to another
location called a destination, without modifying the contents of the source. In
technical manuals, the term data transfer is used for this copying function.
However, the term transfer is misleading; it creates the impression that the
contents of the source are destroyed when, in fact, the contents are retained
without any modification.
The various types of data transfer (copy) are listed below together with
examples of each type:
Types
1. Between Registers.
Copy the contents of the register B into register D.
2. Specific data byte to a register or a memory location. Loads register B with the
data byte 32H.
Between a memory location and a register. From a memory location 2000H to
register B.
3. Between an I/O device and the accumulator. From an input keyboard to the
accumulator.
2. Arithmetic Operations
These instructions perform arithmetic operations such as addition, subtraction,
increment, and decrement.
Addition: Any 8-bit number, or the contents of a register or the contents of a
memory location can be added to the contents of the accumulator and the sum is
stored in the accumulator. No two other 8-bit registers can be added directly
(e.g., the contents of register B cannot be added directly to the contents of the
register C). The instruction DAD is an exception; it adds 16-bit data directly in
register pairs.
Subtraction: Any 8-bit number, or the contents of a register, or the contents of
a memory location can be subtracted from the contents of the accumulator and
the results stored in the accumulator. The subtraction is performed in 2's
compliment, and the results if negative, are expressed in 2's complement. No
two other registers can be subtracted directly.
Increment/Decrement: The 8-bit contents of a register or a memory location
can be incremented or decrement by 1. Similarly, the 16-bit contents of a
register pair (such as BC) can be incremented or decrement by 1. These
increment and decrement operations differ from addition and subtraction in an
important way; i.e. they can be performed in any one of the registers or in a
memory location.
18
3. Logical Operations
These instructions perform various logical operations with the contents of the
accumulator.
AND, OR Exclusive-OR: Any 8-bit number, or the contents of a register, or of
a memory location can be logically ANDed, ORed, or Exclusive-ORed with the
contents of the accumulator. The results are stored in the accumulator.
Rotate: Each bit in the accumulator can be shifted either left or right to the next
position.
Compare: Any 8-bit number or the contents of a register, or a memory location
can be compared for equality, greater than, or less than, with the contents of the
accumulator.
Complement: The contents of the accumulator can be complemented. All 0s
are replaced by 1s and all 1s are replaced by 0s.
4. Branching Operations
This group of instructions alters the sequence of program execution either
conditionally or unconditionally.
Jump - Conditional jumps are an important aspect of the decision-making
process in the programming. These instructions test for a certain conditions
(e.g., Zero or Carry flag) and alter the program sequence when the condition is
met. In addition, the instruction set includes an instruction called unconditional
jump.
Call, Return, and Restart - These instructions change the sequence of a
program either by calling a subroutine or returning from a subroutine. The
conditional Call and Return instructions also can test condition flags.
5. Machine Control Operations
These instructions control machine functions such as Halt, Interrupt, or do
nothing. The microprocessor operations related to data manipulation can be
summarized in four functions:
1. Copying data
2. Performing arithmetic operations
3. Performing logical operations
Testing for a given condition and alerting the program sequence Some important
aspects of the instruction set are noted below:
1. In data transfer, the contents of the source are not destroyed; only the contents
of the destination are changed. The data copy instructions do not affect the
flags.
2. Arithmetic and Logical operations are performed with the contents of the
accumulator, and the results are stored in the accumulator. The flags are
affected according to the results.
3. Any register including the memory can be used for increment and decrement.
4. A program sequence can be changed either conditionally or by testing for a
given data condition.
19
Instruction Format
An instruction is a command to the microprocessor to perform a given task on a
specified data. Each instruction has two parts: one is task to be performed, called the
operation code (opcode), and the second is the data to be operated on, called the
operand. The operand (or data) can be specified in various ways. It may include 8-bit
(or 16-bit) data, an internal register, a memory location, or 8-bit (or 16-bit) address. In
some instructions, the operand is implicit.
Instruction word size
The 8085 instruction set is classified into the following three groups according to
word size:
1. One-word or 1-byte instructions
2. Two-word or 2-byte instructions
3. Three-word or 3-byte instructions
In the 8085, "byte" and "word" are synonymous because it is an 8-bit microprocessor.
However, instructions are commonly referred to in terms of bytes rather than words.
One-Byte Instructions
A 1-byte instruction includes the opcode and operand in the same byte. Operand(s)
are internal register and are coded into the instruction.
For example:
Task
Copy the contents of the accumulator in the register C.
Mnemonic Hex code
MOV C, A 4FH
Add the contents of register B to the contents of the accumulator.
Mnemonic Hex code
ADD B 80H
Invert (compliment) each bit in the accumulator
Mnemonic Hex code
CMA 2FH
These instructions are 1-byte instructions performing three different tasks. In the first
instruction, both operand registers are specified. In the second instruction, the
operand B is specified and the accumulator is assumed. Similarly, in the third
instruction, the accumulator is assumed to be the implicit operand. These instructions
are stored in 8- bit binary format in memory; each requires one memory location.
MOV Rd, Rs
Rd ß Rs copies contents of Rs into Rd. Example: MOV A, B
Coded as 01111000 = 78H = 170 octal (octal was used extensively in instruction
design of such processors).
ADD R
AßA+R
20
Two-Byte Instructions
In a two-byte instruction, the first byte specifies the operation code and the second
byte specifies the operand. Source operand is a data byte immediately following the
opcode. For example:
Task
Load an 8-bit data byte in the accumulator.
Assume that the data byte is 32H. The assembly language instruction is written as
Mnemonic Hex code
MVI A, 32H 3E 32H
The instruction would require two memory locations to store in memory. MVI R, data
R ß data
Example: MVI A, 30H coded as 3EH 30H as two contiguous bytes. This is an
example of immediate addressing.
ADI data
A ß A + data
Where port is an 8-bit device address. (Port) ß A. Since the byte is not the data but
points directly to where it is located this is called direct addressing.
Three-Byte Instructions
In a three-byte instruction, the first byte specifies the opcode, and the following two
bytes specify the 16-bit address. Note that the second byte is the low-order address
and the third byte is the high-order address.
Opcode + Data byte + Data byte For example:
Task
Transfer the program sequence to the memory location 2085H.
Mnemonic Hex code
JMP 2085H C38520
This instruction would require three memory locations to store in memory. Three byte
instructions: opcode + data byte + data byte
LXI Rp, data16
Rp is one of the pairs of registers BC, DE, HL used as 16-bit registers. The two data
bytes are 16-bit data in L H order of significance.
Rp ß data16 Example:
LXI H, 0520H coded as 21H 20H 50H in three bytes. This is also immediate
addressing. LDA Addr
A ß (Addr) Addr is a 16-bit address in L H order.
Example: LDA 2134H coded as 3AH 34H 21H. This is also an example of direct
addressing
21
Capabilities
1. Examine the contents of any memory location.
2. Examine/Modify the contents of any of the up internal register.
3. Modify the contents of any of the RAM location.
4. Move a block of data from one location to another location.
5. Insert one or more instructions in the user program.
6. Delete one or more instructions from the user program.
7. Relocate a program written for some memory area to some other memory
area.
8. Fill a particular memory area with a constant.
9. Compare two block of memory.
10. Insert one or more data bytes in the user’s program/data area.
11. Delete one or more data bytes from the user’s program/data area.
12. Execute a program at full clock speed.
13. Execute a program in single step i.e. instruction by instruction.
Note: All the above commands can be operated through Serial mode provided
22
Installation
Keyboard Mode:
To install Nvis 5585 in keyboard mode, the following additional things are required.
1. Connect the AC Power Supply through AC Power Chord provided to the Nvis
5585 Trainer.
2. Switch on the Power Supply from Rocker switch.
3. A message −Nvis 85 will come on display (Press Reset if you do not get −Nvis
85.
4. Now Nvis 5585 trainer is ready for the user's experiments for Keyboard Mode
commands.
Serial Mode:
To install Nvis 5585 in serial mode, the following additional things are required.
1. Steps 1, 2 and 3 will remain same for Serial Mode.
2. Connect RS-232C Cable between PC Serial Port (Com-1 OR Com-2) to the
connector CN5 of the Nvis 5585 trainer.
3. Open the Hyper Terminal of Win95/98 and set the Baud rate at 4800bps.
4. Press `SER' Key on Nvis 5585 trainer and press Ènter' key on PC keyboard. A
message `.*' will be displayed on the PC screen. It is indicating that now the
command can be entered from the PC terminal.
Now Nvis 5585 trainer is ready for the user's experiments for Serial Mode commands
23
Hardware Description
CPU:
The system has got 8085 as the Central Processing Unit. The clock frequency for the
system is 3.07 MHz and is generated from a crystal of 6.14 MHz.
8085 has got 8 data lines and 16 address lines. The lower 8 address lines and 8 bit
data lines are multiplexed. Since the lower 8 address bits appear on the bus during the
first clock cycle of a machine cycle and the 8 bit data appears on the bus during the
2nd and 3rd clock cycle, it becomes necessary to latch the lower 8 address bits during
the first clock cycle so that the 16 bit address remains available in subsequent cycles.
This is achieved using a latch 74-LS-373.
Memory:
Nvis 5585 provides 8K bytes of CMOS RAM using 6264 chip and 8K bytes of
Powerful Monitor EPROM. This trainer has the facility for expanding RAM/ROM in
the expansion socket. Total on board memory can be expanded up to 64K bytes.
I/O Devices:
The various I/O chips used in Nvis 5585 are 8279, 8255, 8155 & 8253. The
functional role of all these chips is given below:
8279 (Keyboard & Display Controller):
8279 is a general purpose programmable keyboard and display I/O interface device
designed for use with the 8085 microprocessor. It provides a scanned interface to 28
contact key matrix provided in Nvis 5585 and scanned interface for the six seven
segment displays. 8279 has got 16 x 8 display RAM which can be loaded or
interrogated by the CPU. When a key is pressed, its corresponding code is entered in
the FIFO queue of 8279 and can now be read by the microprocessor. 8279 also
refreshes the display RAM automatically.
8255 (Programmable Peripheral Interface):
8255 is a programmable peripheral interface (PPI) designed to use with 8085
Microprocessor. This basically acts as a general purpose I/O device to interface
peripheral equipments to the system bus. It is not necessary to have an external logic
to interface with peripheral devices since the functional configuration of 8255 is
programmed by the system software. It has got three Input/ Output ports of 8 lines
each (PORT-A, PORT-B & PORT- C). Port C can be divided into two ports of 4 lines
each named as Port C upper and Port C lower. Any Input/ Output combination of Port
A, Port B, Port C upper and lower can be defined using the appropriate software
commands.
24
8155 (Programmable I/O Port & Timer Interface):
8155 is a programmable I/O ports and timer interface designed to use with 8085
Microprocessor. The 8155 includes 256 bytes of R/W memory, three I/O ports and a
Timer. This basically acts as a general purpose I/O device to interface peripheral
equipments to the system bus. It is not necessary to have an external logic to interface
with peripheral devices since the functional configuration of 8155 is programmed by
the system software. It has got two 8-bit parallel I/O port (Port-A, Port-B) and one 6-
bit (Port-C). Ports A & B also can be programmed in the handshake mode, each port
using three signals as handshake signals from Port-C. The timer is a 14 bit down
counter and has four modes
8253 (Programmable Internal Timer):
This chip is a programmable internal Timer/Counter and can be used for the
generation of accurate time delays under software control. Various other functions
that can be implemented with this chip are programmable rate generator, Even
Counter, Binary rate Multiplier, Real Time Clock etc. This chip has got three in
dependent 16 bit counters each having a count rate of up to 2KHz. The first
Timer/Counter (i.e. Counter 0) is being used for Single Step operation. However, its
connection is also brought at connector. For single step operation CLK0 signal of
Counter 0 is getting a clock frequency of 1.535 MHz.
Display:
Nvis 5585 provides six digits of seven segment display. Four digits are for displaying
the address of any location or name of any register, whereas the rest of the two digits
are meant for displaying the contents of a memory location or of a register. All the six
digits of the display are in hexadecimal notation
25
Keyboard Command Description
Nvis 5585 has 28 keys and six-seven segment display to communicate with the
outside world. As Nvis 5585 is switches on, a message „−NVS 85’ is displayed on the
display and all keys are in command mode. The key board is as shown below.
Reset the system.
Hardware interrupts via keyboard, RST 7.5.
Provides a second level command to all keys. To execute the program.
To execute the program in single step mode
Examine Register; allows user to examine and modify the contents of

different registers.
Examine Memory; allows user to examine any memory location and
modify any RAM location.
Previous is used as an intermediate terminator in case of Examine
Memory. It decrements the PC contents and writes the contents of data
field to the address displayed in the address location
26
Increment(Next) is used as an intermediate terminator in case of
Examine Memory, Examine Register etc. It increments the PC Contents
and writes the data lying in data field at the location displayed at address
field.
Terminator is used to terminate the command and write the data in data
field at the location displayed in address field.
Delete the part of program or data, with relocation by one or more bytes.
Inserts the part of the program or data with relocation, by one or more
bytes.
Allows user to move a block of memory to any RAM area.
Allows user to fill RAM area with a constant.
Relocates a program written for some memory area and to be transferred

to other memory area.
Inserts one or more data bytes in the user’s program/data area.
All commands are followed by a set of numeric parameters separated by PREV, NEXT
& ‘.’ (Execute) to work as delimiters.
A ‘−’ on the MSD of address display indicates that system is waiting for a command. If,
instead of a valid command, the user gives a data, the system will display “−Err”. A dot
on the LSD of address field indicates that the system expects an address. Whenever the
data of any memory location is changed, a dot is displayed on the LSD of Data Field.
27
The Nvis 5585 accepts all data and address in hexadecimal form as given in the table 1
Hexadecimal Decimal Binary LED Display
0 0 0000 0
1 1 0001 1
2 2 0010 2
3 3 0011 3
4 4 0100 4
5 5 0101 5
6 6 0110 6
7 7 0111 7
8 8 1000 8
9 9 1001 9
A 10 1010 A
B 11 1011 B
C 12 1100 C
D 13 1101 D
E 14 1110 E
F 15 1111 F
28
List of Commands:
1. Reset
2. Examine/Modify Register
3. Examine/Modify Memory
4. Go
5. Single Instruction
6. Block Move
7. Delete
8. Insert
9. Relocate
10. Fill
11. Memory compare
12. Insert data
13. Delete data
Reset:
This key initializes the Nvis 5585 trainer and displays „−NVS 85’ on the display. A
„−‘ on the left most end of display indicates that the system is expecting a valid
command.
Examine/Modify Register:
This command is used to examine/modify any internal register of the CPU. If one
wants to examine the contents of all the registers, one can start from À' Reg. and
examine all the registers by pressing next key. Whereas if some specific registers is to
be examined, then the key for that register can be entered directly. The contents of
any register can be changed.
29
Exercise:
Examine the contents of A Reg. and B Reg. and change the contents of B Reg. to 02
Hex Key Pad Address Field Data Field
On pressing SHIFT and REG key, a dot is displayed in the address field. Enter the
reg. identifier i.e. A. The contents of A reg. is displayed. Press NEXT to see the
content of B Reg. E2 is displayed. Press 0 Key and 2 key and then NEXT to enter 02
in B Register. Terminate the command by pressing “.” key.
Note: The data CC and E2 displayed for A and B Registers are just some arbitrary
data and taken for example only.
Examine/Modify Memory:
This command is used to examine the contents of any memory location and modify
the contents of the RAM area.
On pressing this key, a dot is displayed in the end of address field. On can now enter
the address of any location one wants to examine. Enter the desired address and press
NEXT. The contents of this location are displayed in the data field. If one wants to
examine the contents of next location, just press NEXT and the address in the address
field will be incremented by one and its contents will be displayed in the data field.
Same way if one wants to examine the content of previous location just press PRE
key and the address in the address field will be decremented by one and its contents
will be displayed in the data field If one wants to modify the contents of any RAM
location, then enter the data and press NEXT. The data field will be written in the
address displayed in the address field and simultaneously the contents of next location
will be displayed.
30
Exercise:
Enter the following program:
Address Opcode Mnemonic
2000 AF XRA, A
2001 C3 JMP 2000
2002 00
2003 20
31
Verify that the program using the same EXMEM Key so that data is entered properly
Note: Please note that data displayed on pressing NEXT i.e. 1A, 02, 50, 25 and C2 is
some arbitrary data and need not be same, every time the process is repeated.
GO:
This command is used to execute the program in full clock speed. On pressing this
key, the program counter contents are displayed in the address field with the data in
the data field. A dot in the address field indicates that the address can be changed, if
so desired. Enter the starting address of the program. On entering this address, the
data field gets blanked out. Press Terminate (.) key. The CPU will start executing the
program and E will be displayed in the address field.
Exercise
Execute the program entered earlier using examine memory command.
Single Instructions:
This command is used to execute the program instruction by instruction. On pressing
SI, the program counter content is displayed on the address field and its data in the
data field. If one wants to modify the address, one can do that. After entering the
address, press NEXT, the contents of the entered address is displayed. On pressing
NEXT, one instruction will be executed and the address of the next instruction will be
displayed with its data in the data field. Each time NEXT is pressed, one instruction is
executed. If one wants to watch registers contents at any stage, one can do that using
(.) key. On pressing (.) key, a „- is displayed in the address field. One can now
examine any internal register of CPU or any memory location and modify it if
desired.
Exercise
Enter the following program than run in SI Mode and watch register contents.
Address Opcode Mnemonic Comments
2000 3E 22 MVI A, 22 Move 22 in a Register
Move the Contents of A Value into

2002 47 MOV A, B
A Register
2003 EF RST 5 Software Breakpoint
32
Note: Enter the above program using examine memory command. The following is the
procedure of executing in SI mode.
The first command is executed i.e. A Register has been loaded with 22. Let us examine the
content of A Register. For this we will have to terminate the command here.
Terminate the command again.
To run the program further presses SHIFT and SI.
The program came back at the same address where we left it.
The program after completing may jump to some other location as it may take next location
data as an executing instruction. User has to remember end address of program.
Block Move:
This command allows the user to move the block of data from one memory location to
another memory location. On pressing this key a dot is displayed at the end of address field.
Enter the starting address of the block to be moved and press NEXT. Again a dot is displayed.
Now enter the end address of the block and press NEXT. Again a dot is displayed. Now enter
the destination address and press Terminate (.) key. A „-; is displayed in the display.
33
Exercise
Block Move the program lying from 2000 to 2003 (in the earlier exercise) to 2100.
Verify that the program has moved to 2100 using examine memory command.
Delete:
This command allows the user to delete one or more instructions from the user’s program. In
this command all the memory referenced instructions also get modified accordingly to keep
the logic of the program same. The following information is to be entered:
1. Starting address of the user program.
2. End address of the user program.
3. Address of the location from where onwards the bytes are to be deleted.
4. Address of the location till where the bytes are to be deleted.
Exercise
Take the program of Sample program 9 i.e. flashing „ABCDEF;. In this program the word
„ABCDEF’ is displayed for 0.5 Sec., the display is cleared for 0.5 Sec. and the logic is
repeated. In this program, if the clear routine is deleted, the word „ABCDEF’ will remain
permanently displayed.
Enter this program from 2000 to 2029 using Examine/Modify memory command and delete
the data from 201E to 2026.
Run this program using GO command before deleting the data. You will see that „ABCDEF’
is being flashed on the display. To delete the clear routine do the following: On pressing DEL
DATA Key, some address is displayed. Enter the starting address of the program and press
NEXT. Now enter the end address and press NEXT. A dot is displayed at the end of the
Address field. Now enter the starting address from where the bytes are to be deleted and press
NEXT. Again a dot is displayed at the end of address field. Enter the end address till where
the bytes are to be deleted and press Terminator (.) key. A „-; will be displayed in the address
field indicating that the system is ready to accept the new command.
34
Verify that the program from 201E to 2026 has been deleted. Execute the program and see
that the word „ABCDEF’ is displayed permanently.
Insert:
This command allows the user to insert one or more instructions in the user’s program with
automatic modification of the memory referenced instructions. This following information is
required to be entered.
1. Starting address of the program.
2. End address of the program.
3. Address from where the bytes are to be entered.
4. No. of bytes to be entered.
5. Data.
Exercise
Insert the bytes again, which are deleted in the above exercise of flashing „ABCDEF On
pressing INS DATA Key, an address is displayed on the address field. Enter the starting
address of the program and press Next. Again an address is displayed. Now enter the end
address of the program and press Next. A dot is displayed at the end of the address field. Enter
the address at which the bytes are to be entered and press NEXT. A dot is displayed again.
Now enter the number of bytes to be entered and press NEXT. The system will display the
address where you wish to enter the bytes with its current data in the data field. Enter the
bytes you want to insert using NEXT key. When all the bytes are entered, a „-‘ will be
displayed indicating that the system is ready to accept a new command.
35
Since we have just executed this program, the program address is not disturbed. So we
directly press NEXT.
Our last address is also 2020, as in previous command in Delete we have deleted 9 bytes
therefore End address become 2020 so we just press NEXT.
Since 9 bytes have to be entered,
The contents of 20 1E is displayed.
Verify that the bytes have been inserted and execute the program from 2000 to note the
flashing ‘ABCDEF’ on the display
Relocate: This command allows the user to relocate program written for some memory area,
to some other memory area. The information required to be entered are:
1. Starting address of the program.
2. End address of the program.
3. Destination address where the program has to be relocated.
The relocate command can be best understood with the earlier example of flashing
„ABCDEF’. This program is written for 2000 memory area. So that jump instruction for
looping at the end is with reference to 2000 only. Suppose you want this program to be
executable for 2100 area, then this cannot be done by Block Move because when we Block
Move the program from 2000-2029 to 2100, the contents of 2127 onwards will be 2127 - C3,
2128 - 06, 2129 - 20. Where as in order to execute this program from 2100, the content of
2129 should be 21.
36
This can be done using Relocate command.
Exercise
On pressing SHIFT and Relocate, a dot is displayed in the address field. Enter the starting
address of the program i.e. 2000 and press NEXT. A dot is displayed again. Now enter the
end address of the program i.e. 2029 and press NEXT. Again a dot is displayed. Now enter
the destination address i.e. 2100 and press (.).
Now verify that 2129 has got 21. Execute the program from 2100 and note that the
„ABCDEF' will be flashing on the display.
Fill:
This command allows the user to fill a memory area (RAM) with a constant. The following
information is required to be entered.
1. Starting address of the memory area from where the data should be stored.
End address of the memory area till was the data should be stored
2. The constant with which the data should be done i.e. 22.
Exercise
Fill the RAM area from 2000 to 2050 with 22.
Press SHIFT and FILL. A dot will be displayed at the end of the address field. Enter the
starting address and press NEXT. Again a dot will be displayed. Now enter the end address
and press NEXT. The present contents of end address will be displayed. Enter the content and
press (.).
37
05 is just some random data which was lying at 2000. Press „2’ key twice and press Terminate
(.) key.
Verify that 22 is filled from 2000 to 2050.

Memory Compare:
This command allows the user to compare two blocks of memory for equality. If they are not
equal, the address of the first block at which there is a discrepancy will be displayed. The
flowing information needs to be entered.
1. Starting address of the first Block.
2. End address of the first Block.
3. Starting address of the second Block.
Exercise
Enter the following Data using Examine Memory command:
2000 - 00 2005 - 55
2001 - 11 2006 - 66
2002 - 22 2007 - 77
2003 - 33 2008 - 88
2004 - 44 2009 - 99
38
Now Block Move this block to 2100 using B.M command. Now use Memory
Compare command as follows:
Press SHIFT and Memory Compare. A dot is displayed at the end of address field.
Enter the starting address of the first block and press NEXT. Again a dot is displayed.
Enter the end address of the first block and press NEXT. A dot is displayed. Now
enter the starting address of the second block and press Terminate (.) key.
Since the two blocks are identical a „-‘ will be displayed.

Now change the content of 2005 to 50 and that of 2008 to 68. Again use the Memory
Compare command as mentioned above. You will see that an address 2005 will be
displayed on the address field and its contents in the data field. Press NEXT and now
2008 will be displayed with the contents. On pressing NEXT, „-“ will be displayed
indicating that the two blocks are identical
Microprocessor Lab Software
Microprocessor lab software is used to interface Nvis 5585 trainer with PC by serial
port. The user can communicate Nvis 5585 trainer with PC as below procedure
mentioned
First run the microprocessor lab software setup.
40
First close all programs (e.g. hyper terminal) which use same port.
After the installation is complete above window is appear on screen.
For selecting the com port of PC use selection button “Select Com Port” as
shown in above figure.
For connecting the Nvis 5585 use button “Connect to port”, and that particular
button become red. For disconnect click on same button.
41
For selecting the trainer click button “Connect Nvis 5585” and it change to
“Disconnect Nvis 5585”.For disconnect the trainer click on same button.
And follow the procedure given below:
1. Click on send data text bar on the screen (Cursor must be on the send data
text bar for starting the commutation)
2. Press `SER' key on trainer keyboard.
3. Now Press ÈNTER' Key on PC keyboard you will see below character on
the PC Screen.
*
.
42
Now you can use all serial commands
For sending command to trainer click on text bar name “Send Data” on screen
and write command.
All the send command and response from trainer appear on “Response” window
For refreshing the screen click button “Refresh”
For sending any file form PC to trainer, first send „T” command to trainer by
using „Send Data ‘text bar.
Then click on ‘Send File’ button as show in below figure
Then window appear is shown on below figure. Select the file to be send (to
trainer) and click on open button. No need to press any key.
When transfer complete, a star and dot appear on response window
43
For uploading the file press “Capture text” button on lower right of window as
shown in above figure and another window shown below.
44
This is for saving incoming file form trainer to PC. And then follow the
procedure given in section Uploading.
After file transfer complete click on button “Save File” as shown above.
45
Serial Command Description
List of Serial Commands:
1. L List a memory block
2. M Examine/Modify Memory
3. E Enter a memory block
4. R Examine/Modify Register
5. S Single Step
6. G Go
7. B Block Move
8. I Insert
9. D,O Delete
10. N Insert Data
11. F Fill
12. H Relocate
13. J Memory Compare
List a Memory Block
L command outputs on the SIOD device a formatted listing of memory block.
Format
L <Low Address> , <High Address> $
Type L followed by the starting address of the memory block to be listed, followed
by a comma (,) and then the end address of the memory block followed by $.
The outputting format will be as given below:
Example
Suppose you want to list the data from 2000 to 2018.
L : 2000, 2018 $
2000: AB AE CD BC AA BB BC AF CD DE
2001: AB CD DC DD EE AA BC AF BB AA
2014: BC CD AA AB FC $
Examine/Modify Memory
The M command allows you to examine and modify memory locations individually.
The command functions as follows:
Format
M <Address> , (Data) , ............... $
1. Type M, followed by the hexadecimal address of the first memory location you
wish to examine, followed by a space or comma.
2. The contents of the location are displayed followed by a dash ‘-’.
3. To modify the contents of the location displayed, type the new data, followed by
a comma. If you do not wish to modify the location, type only the comma. The
higher memory location will automatically be displayed as the step (s).
4. A $ at any stage terminates the command.
46
Example
M 2000, C3-00, 23-11, FC-22, 3E, 21-44 <$>
The contents of 2000 to 2002 and 2004 are changed from C3 to 00, 23 to 11 and FC
to 22 & 21 to 44, respectively whereas the data at 2003 remains as it is.
Location Old Contents New Contents
2000 C3 00
2001 23 11
2002 FC 22
2003 3E 3E
2004 21 44
Enter a Memory Block

E command allows user to enter a program or a block of data in the RAM.
Format:
E <Address> : <data>, <data>, ............... $
1. Type E followed by the starting address of the memory block to be entered,
followed by a colon (:).
2. Each byte followed by a comma as it is entered from the SIOD is deposited in
the consecutive location in the memory.
3. In case the terminator is colon (:) the proceeding parameter is taken as a fresh
address and the subsequent data bytes are stored in memory location starting
from the fresh address.
4. A $ terminates the command.
Example
E 2000: 3E, 11, 11, 08, FC $.
The memory contents as stored are shown below: 2000 3E, 11, 11, 08, FC.
Examine/Modify Register
Display & modification of CPU register is accomplished via R command
47
Format:
R <Register identifier>, $
Type R followed by a single alphabet register identifier. The contents may now be
changed if so desired. In case you do not want to modify the contents, just enter a
comma. The contents of the next register will be printed. The register identifiers for
various CPU registers are given below:
Register Identifier Register
A Register A
B Register B
C Register C
D Register D
E Register E
F Flag byte
Register Identifier Register
I Interrupt Mask
H Register H
L Register L
S Stack Point MSB & LSB
P Program Counter MSB & LSB
Single Instructions
This command allows to execute the program one instruction at a time.
Format
S <Starting Address>, ...... $
Pressing of S key will list the PC and first byte of the program. In case one want to
modify it, one has to enter the new address and then press comma. The new address
will be entered and pressing of comma again will execute on instruction. The new PC
and the next instruction will be listed. In this way one can execute the program in
single instruction mode.
Example
The following program is to be executed in single instruction mode:
Address Op Code Mnemonic
2000 11 50 20 LXI D, 2050
2003 3E 27 MVI A, 27
2005 21 70 20 LXI H, 2070
2008 77 MOV M, A
On executing S command S 2000 : 11/, 2003 : 3E/, 2005 : 21/. If one wants to execute
further, one presses otherwise one presses $.
48
Go Command
This command executes the program.
Format
G <Starting address> $
Pressing of G key will display the PC content and the first byte of the instruction. To
modify it, enter the desired address & then press comma, the PC will be modified
with new contents & the corresponding data will be listed. When $ key is pressed,
CPU starts executing the program. Suppose the program starts from 2000 then the
format will be G 2000 $.
Block Move Command
This command has the same functions as explained in BLOCK MOVE under
keyboard description.
Format
B <Starting address of the source>, <End address of the source>, <Starting address of
the destination> $
Insert Command
This command has the same functions as explained in INSERT under key board
description.
Format
I <Starting address of the program>, <End address of the program>, <Address from
where the byte or bytes are to be entered>, <No. of bytes>, <Data bytes separated by>
$
Delete Command
This command has the same function as explained in DELETE under key board
description.
Format
D <Starting address of the program>, <End address of the program>, <Starting
address from where the bytes are to be deleted>, <End address till where the bytes are
to be deleted> $1
Insert Data
This command has the same function as explained in INSERT DATA under key
board description.
Format
N <Starting address of the program/data area>, <End address of the program>,
<Starting address at which the bytes are to be entered>, <No. of bytes>, <Data bytes
separated by>$
49
Example
Suppose the RAM area 2000 to 2007 has the following data.
2000 : AF 02 00 25 57 DE 47 BC and we need to insert AA BB at 2002 onwards then
the format will be N XXXX-2000, XXXX-2007, 2002 ,2, 00-AA, 25-BB, On
pressing the last the command is executed and a prompt character again appear
indicating that the new command can be entered.
Delete Data
This command has the same function as explained in DELETE DATA under key
board description.
Format
O <Starting address of the program/Data area>, <End address of the program/data
area>, <Starting address from where the deletion should start>, <End address till
where bytes are to be deleted> $p
Example
Suppose the bytes inserted in the above example are now to be deleted. Then the
format will be:
O XXXX - 2000, XXXX - 2009, 2002, 2003 $
One can verify that the bytes have been deleted.
Fill
This command has the same function as explained for Trainer.
Format
F <Starting address of area>, <End address> , Data to be filled $ Example
Suppose the RAM area, from 2000 to 2010 is to be filled with FF. The format will be:
F 2000, 2010, XX - FF $
XX is some random data displayed at that stage.
Relocate
The command has the same function as explained for Trainer.
Format
H <Starting address of the program>, <End address of the program>, <Destination
address of the program> $
Example
Suppose the program relocated in Chapter-4 under RELOCATE is to be relocated in
serial mode, the format for this will be:
H 2000, 2029, 2100 $
50
Memory Compare Format
J <Starting Address of first block>, <End address of first block>, <Starting address of
second block> $
If the example explained earlier in Chapter-4 for RELOCATE is to be executed in
serial mode. The format will be:
J 2000, 2009, 2100 $
Down Loading (T):
This command allows user to download any .HEX file from PC to the trainer. Down
Loading the .KIT or .TXT from PC to Nvis 5585 trainer.
The following procedure is to be adopted for downloading the file from PC to
Trainer. The ‘T’ command loads the data from your diskette/PC to the memory of the
trainer.
1. Press To key of the PC keyboard.
2. Follow the procedure given in Microprocessor Software.
3. Choose File Name i.e. ABC.KIT or ABC.TXT and Click it.
4. The program stored in the file will be loaded in memory of Trainer at the
address specified in the program.
Uploading (L):
This command allows user to store any particular block of data from trainer to the PC.
Uploading the ABC.HEX from Nvis 5585 trainer to PC.
The following procedure is to be adopted for uploading the file from Trainer to PC.
1. Press ‘L’ key of the PC keyboard
2. Write Start Address and End Address in below mention format for e.g. L2000,
20FF
and use procedure given in Microprocessor Lab Software.
3. Press ‘$’ Key on Nvis 5585 trainer. Address and Data will see on PC Screen.
4. Data captured will be stored in the file as defined by the file name
Downloading of Intel Hex File
To download HEX file created by Cross Assembler, one has to first convert HEX file
to Kit format for downloading. HEX Kit Software is used for converting HEX File to
KIT format.
51
Xassembler
To use MASM Software and download generated file to Trainer please follow these
steps.
Write any Program in following format for Nvis 5585
; Fibonacci Series Generation
To run the Program simply load at memory location 2050=01, 2051=01
CPU 8085
ORG 2000H
Address Opcode Mnemonic Comment
2000 0E 09 Start : MVI C,09 ;Counter Loaded
H,205 ;Memory Pointer(Load 2050h In Register

2002 21 50 20 LXI
0 Pair)
2005 7E MOV A,M ; Move Content of Memory To Acc
2006 23 INX H ; Increment Hl Register Pair By 1
2007 46 MOV B,M ; Move Content of Memory To B Register
2009 80 ADD B ;ACC=ACC+B
200A 27 DAA ;Decimal Adjust ACC
200B 77 MOV M,A ; Move Content of ACC to memory
200C 2B DCX H ; Decrement Hl Register Pair By 1
200D 0D DCR C ;Content Of Register C Is Decremented By 1
200E C2 05 20 JNZ 2005 ;Jump To 2005 Memory Location If No Zero
2011 CF RST 1 ;Reset
END
52
Note: Starting CPU 8085 & ORG 2000H in every program should be their along with
end command also.
a. Write above program in any Word pad/Note pad/any editor.(DOS/WINDOW)
save this program suppose ABC.ASM
b. Extension .ASM should be there.
c. Open assembler file i.e. where assembler is saved. You will find file
NVIS8085.COM
d. Open this file with command mode, to do this
e. Save above file suppose file name ABC.ASM in same folder where the
assembler is saved.
f. Now do the following steps
Open command prompt window by typing cmd in run command
· A window appears as shown below
53
· Now enter into the cross assembler directory for my system it is in C: drive
· Run MASM file in below mention format
Now enter into the cross assembler directory for my system it is in C: drive
54
· Then press “ENTER” key of PC keyboard. The PC screen will display Now it is
waiting for input file
· Now it is waiting for input file

Note: The ASM file should be in same folder where MASM assembler is placed,
while giving file name it should not be greater than 6 characters and at time of file
name input while compiler is waiting never give extension .ASM on type file name as
shown
55
· Press enter it will display a message
· Step4>Run NVISHEXKIT.exe as shown
56
· It will display a window as shown
· At right side it is showing all HEX files currently present in the directory of X
Assembler select 8255 by up down arrow key and press Enter
· It will ask for displaying output on screen press y
· It will generate kit file format which is supported by our Trainer

Connect hyper terminal with kit then select transfer then send text file Our file
will be down loaded into kit
57
8085 Instruction Set
Hex Code Mnemonic
52 MOV D,D
71 MOV M,C
53 MOV D,E
72 MOV M,D
54 MOV D,H
73 MOV M,E
55 MOV D,L
74 MOV M,H
56 MOV D,M
75 MOV M,L
5F MOV E,A
3E MVI A, 8-Bit
58 MOV E,B
06 MVI B, 8-Bit
59 MOV E,C
0E MVI C, 8-Bit
5A MOV E,D
16 MVI D, 8-Bit
5B MOV E,E
1E MVI E, 8-Bit
5C MOV E,H
26 MVI H, 8-Bit
5D MOV E,L
2E MVI L, 8-Bit
5E MOV E,M
36 MVI M, 8-Bit
67 MOV H,A
00 NOP
60 MOV H,B
B7 ORA A
61 MOV H,C
B0 ORA B
62 MOV H,D
B1 ORA C
58
63 MOV H,E
B2 ORA D
64 MOV H,H
B3 ORA E
65 MOV H,L
B4 ORA H
B5 ORA L
6F MOV L,A
66 MOV H,M
B6 ORA M
68 MOV L,B
F6 ORI 8-Bit
69 MOV L,C
D3 OUT 8-Bit
82 ADD D
E9 PCHL
6B MOV L,E
C1 POP B
6C MOV L,H
D1 POP D
6D MOV L,L
E1 POP H
6E MOV L,M
F1 POP PSW
77 MOV M,A
C5 PUSH B
70 MOV M,B
D5 PUSH D
E5 PUSH H
9D SBB L
F5 PUSH PSW
9E SBB M
DE SBI 8-Bit
1F RAR
22 SHLD 16-Bit
D8 RC
30 SIM
59
C9 RET
F9 SPHL
20 RIM
32 STA 16-Bit
07 RLC
02 STAX B
F8 RM
12 STAX D
D0 RNC
37 STC
C0 RNZ
97 SUB A
F0 RP
17 RAL
90 SUB B
E8 RPE
91 SUB C
E0 RPO
92 SUB D
0F RRC
93 SUB E
C7 RST 0
94 SUB H
CF RST 1
95 SUB L
D7 RST 2
96 SUB M
EB XCHG
DF RST 3
D6 SUI 8-Bit
E7 RST 4
EF RST 5
AF XRA A
F7 RST 6
A8 XRA B
BF CMP A
FF RST 7
A9 XRA C
C8 RZ
AA XRA D
98 SBB B
9F SBB A
60
AB XRA E
EE XRI 8-Bit
E3 XTHL
CE ACI 8-Bit
3F CMC
8F ADC A
AC XRA H
99 SBB C
AD XRA L
9A SBB D
AE XRA MX
9B SBB E
89 ADC C
88 ADC B
F4 CP 16-Bit
EC CPE 16-Bit
83 ADD E
FE CPI 8-Bit
84 ADD H
E4 CPO 16-Bit
85 ADD L
CC CZ 16-Bit
86 ADD M
27 DAA
C6 ADI 8-Bit
09 DAD B
A7 ANA A
19 DAD D
A0 ANA B
29 DAD H
A1 ANA C
39 DAD SP
A2 ANA D
3D DCR A
A3 ANA E
05 DCR B
A4 ANA H
0D DCR C
A5 ANA L
15 DCR D
A6 ANA M
1D DCR E
61
E6 ANI 8-Bit
25 DCR H
CD CALL 16-Bit
2D DCR L
0B DCX B
2F CMA
1B DCX D
2B DCX H
01 LXI B, 16-Bit
3B DCX SP
11 LXI D, 16-Bit
F3 DI
21 LXI H, 16-Bit
FB EI
31 LXI SP, 16-Bit
76 HLT
7F MOV A,A
DB IN 8-Bit
78 MOV A,B
3C INR A
79 MOV A,C
04 INR B
7A MOV A,D
0C INR C
7B MOV A,E
14 INR D
7C MOV A,H
1C INR E
7D MOV A,L
24 INR H
7E MOV A,M
2C INR L
47 MOV B,A
34 INR M
40 MOV B,B
03 INX BX
03 INX B
41 MOV B,C
13 INX D
42 MOV B,D
23 INX H
44 MOV B,H
62
DA JC 16-Bit
43 MOV B,E
33 INX SP
35 DCR M
DC CC 16-Bit
FC CM 16-Bit
45 MOV B,L
FA JM 16-Bit
46 MOV B,M
C3 JMP 16-Bit
4F MOV C,A
D2 JNC 16-Bit
48 MOV C,B
C2 JNZ 16-Bit
E2 JPO 16-Bit
4C MOV C,H
49 MOV C,C
F2 JP 16-Bit
4A MOV C,D
CA JZ 16-Bit
4D MOV C,L
3A LDA 16-Bit
4E MOV C,M
0A LDAX B
57 MOV D,A
EA JPE 16-Bit
4B MOV C,E
1A LDAX D
50 MOV D,B
2A LHLD 16-Bit
51 MOV D,C
9C SBB H
6A MOV L,D
Note:
1. Byte Instructions: Operand R,M or implicit
2. Byte Instructions: Operand 8-Bit
Byte Instructions: Operand 16-Bit
63
Hardware Interrupts
Interrupts In Nvis 5585 Trainer:
The 8085 has 5 interrupt inputs: INTR, RST 5.5, RST 6.5, RST 7.5, and TRAP. Each
of three RESTART inputs, 5.5, 6.5, 7.5, has a programmable mask. TRAP is also a
RESTART interrupt except it is non-maskable.
The three RESTART interrupts cause the internal execution of RST (saving the
program counter in the stack and branching to the RESTART address) if the
interrupts are enabled and if the interrupt mask is not set. The non-maskable TRAP
causes the internal execution of a RST independent of the state of the interrupt enable
or masks.
Name Restart Address (Hex)
TRAP 2416 (used in 8253 timer for Single Step Instruction execution)
RST 5.5 2C16 (used in keyboard controller 8279)
RST 6.5 3416 (Free for the user and its address is in RAM location is 27B7 to
27B9)
RST 7.5 3C16 (used in keyboard and address is 27BD to 27BF)
There are two different types of inputs in the restart interrupts. RST 5.5 and RST 6.5
are high level-sensitive like INTR (and INT on the 8080) and are recognized with the
same timing as INTR.RST 7.5 is rising edge-sensitive. For RST 7.5, only a pulse is
required to set an internal flip flop which generates the internal interrupt request. The
RST 7.5 request flip flop remains set until the request is serviced. Then it is reset
automatically.
The status of the three RST interrupt masks can only be affected by the SIM
instruction and RESET IN.
The interrupts are arranged in a fixed priority that determines which interrupt is to be
recognized if more than one is pending as follows: TRAP - highest priority. RST 7.5,
RST 6.5, RST 5.5, INTR - lowest priority. This priority scheme does not take into
account the priority of a routine that was started by a higher priority interrupt RST 5.5
can interrupt a RST 7.5 routine if the interrupts were re-enabled before the end of the
RST 7.5 routine.
The TRAP interrupt is useful for catastrophic errors such as power failure or bus
error. The TRAP input is recognized just as any other interrupt but has the highest
priority. It is not affected by any flag or mask. The TRAP input is both edge and level
sensitive. The TRAP input must go high and remain high to be acknowledged, but
will not be recognized again until it goes low, then high again. This avoids any false
triggering due to noise or logic glitches
Example-1
The following examples illustrate the use of RST 5.5 used in keyboard controller
8279 to get the scan code and display in the data field.
64
2000 3E 0E MVI A,0E Initialize RST 5.5
2002 30 SIM Set Interrupt Mask
2003 FB EI Enable Interrupt
2004 CD 29 06 CALL RD KB Read Keyboard
2007 32 F6 27 STA 27F6 Store Current Data
Display The Scan Code On Data

200A CD FA 06 CALL Moddt
Field
200D C3 00 20 JMP 2000 Loop
Execute from 2000 location. Whenever any key is pressed, it displays the scan code
of that particular key
Example-2
The following program will be demonstrating the use of RST 7.5 as VTC INT key on
the keyboard. The program will display ‘Err’ whenever the vector interrupt key is
pressed.
2000 3E 0B MVI A,0B Initialize RST 7.5
2002 30 SIM Set Interrupt MASK
2003 FB EI Enable Interrupt
2004 C3 04 20 JMP 2004 Loop
65
Now write the program for interrupt service routine at 2100 location
2100 CD 55 04 Call ERR Initialize RST 7.5
This Displays Err On The

2103 76 HLT
DISPLAY FIELD
Now enter the jump address of interrupt service routine at 27BD.
Jump To Interrupt Service

27BD C3 00 21 JMP 2100
Routine.
Execute the program from 2000 and press vector interrupt (VEC INT) key and
displays the service routine Err
Software Interrupt
During this process of debugging some time one might just like to examine the status
of the program at a particular point. If this point is near the beginning of the program,
one can reach this point by single instruction facility. But, if this point is quite far off
from the beginning of the program, it is time saving to make use of break point
facility. For this introduce a RST5 instruction (EF) at the point to be examined and
run the program at full speed using GO Command. When, during the execution of the
program, this instruction is encountered, the control of the processor is transferred to
the monitor. The monitor saves the user registers and displays a sign −NVIS 85 on
the display. One can examine the status of any memory location or any internal
register. One can change the content of memory location or register if necessary.
Note: While debugging the program, do not press reset Key
66
Memory / IO Mapping
Memory Mapping:
Nvis 5585 provides 8K byte of RAM and 8K byte of EPROM.
ROM is dedicated for Monitor Program having 8K Bytes of Powerful Monitor
Program is embedded in the 27C512 EPROM. For the system operation the monitor
should start from address 0000. The Memory address is from `0000 to 1FFF'.
RAM is dedicated for user Memory of 8K bytes (6264). The address is from `2000 to
3FFF' for the user RAM. The monitor program uses certain portion of this RAM for
temporary use i.e. scratch pad area. This area is from 2770 to 27FF. The user is
advised not to use this area for storing program.
The detail of Scratch Pad RAM area is given here
Location Contents
2770 - 277D For Kit Expansion
277E Shift
2780 Flag
27BD - 27BF RST 7.5
27BA -27BC RST 7
27B7 - 27B9 RST 6.5
27B4 - 27B6 RST 6
27B1-27B3 RST 4.0
27AE-27B0 RST 2.0
27AB-27AD RST 1.0
27AA-2781 Stack
27DA E Register
27DB D Register
27DC C Register
27DD B Register
27DE Flags
27DF A Register
27E0 L Register
27E1 H Register
27E2 Interrupt Mask
27E3 Program Counter LSB
27E4 Program Counter MSB
27E5 Stack Pointer LSB
67
27E6 Stack Pointer MSB

27E7 SP Shift
27E8-27E9 No. of bytes
27EA-27EB Source Address I
27EC-27ED Destination Address I
27EE-27EF Offset Address
27F0-27F1 Lower Limit
27F2-27F3 Higher Limit
27F4-27F5 Current Address
27F6 Current Data
27F7-27FA Output Buffer
27FB Input Buffer
27FC Temporary Location
27FD-27FE Half Bit Time
27FF System Mode
68
I/O Mapping
Various Chips used in I/O mapped mode in Nvis 5585 are 8255, 8155, 8253 & 8279.
The addresses for these I/O devices are given below:
Device/ Model Port numbers/ Port addresses Selected device

8255 00-07 PPI
00 and 04 Port A
01 and 05 Port B
02 and 06 Port C
03 and 07 Control Word
8155 08-0F PPI & Timer
08 Control Word
09 Port A
0A Port B
0B Port C
0C LSB Timer
0D MSB Timer
8253 10-17 PIT
10 and 14 Counter 0
11 and 15 Counter 1
12 and 16 Counter 2
13 and 17 Control word
8279 18-1F Keyboard/Display Controller
18 and 1C Mode Selector
19 and 1D Control Word
69
Subroutines
Nvis 5585 monitor program needs various utility functions while using the onboard
keyboard and display PC Terminals as a console. These utility functions (routines) reside
in the 8K Bytes of Monitor and so can also be used by the user to simplify his
programming task. Some of these utilities are given here.
Address of Registers
Label Description
Routine Affected
Character Input
This routine takes one 8 bit byte from The
serial i/o port and return it to the Calling A, B, C, D,
030B CH INP routine in a register. The 16 bit Number stored E, H, L &
in 27fd (LSB) nd 27fe (MSB) Decides the baud F/FS
rate. The number Decides the half bit time and
is the Argument of subroutine delay.
This routine is for keyboard only. Input: b-dot, flat A, B, C, D,

032F Clear = 1 for a dot 8 in address field.0 for not dot. E, H, L &
output: F/FS
This Routine Clears The Display And Terminate

033F Clear All Display Command. The Inputs And Outputs In
This Routine Are None.
This routine converts a hex nibble to ASCII. The

various inputs and outputs in this routine are: A, B, C,
0366 CNASC
input: c-HEXCODE to be converted to ASCII. H&L
Output: c-ASCII code
This routine converts an ASCII character to its
binary value. The various inputs and outputs
required are reg. A-7 bit ASCII code with parity
bit = 0, output reg. A: 4 bit hex nibble when input
CNAB is any hex numeric 0-f.
036E ALL
N Reg. A: 10 when input is $
reg. A: 11 when input is sp/ cr
reg a: 3a when input is, for any other input it
jumps to error.
70
Address Label Registers

of routine Affected
038A Chout Character Output A,B,C,D,E,
This routine takes one byte (8 bit) passed on
by the calling routine in register c on the serial
i/o port. the baud rate is decided by the 16 bit
number stored in 27fd (LSB) and 27FE H,L & F/FS
(MSB). The number determines the half bit
time and is the argument of the subroutine
delay.
Decrements A Byte
This Routine Decrements A Byte And If The
03B0 DCRNB Decremented Value Is Zero It Sets The Zero Flag. A & F/FS
Input: None
Output: The Zero Flag Gets Set If The
Decremented Value= 0 Otherwise It Is Reset.
This routine is used to provide delays. It stores
the number in FS register pair d, counts it down
to zero and comes back to the calling routine.
03BC Delay Total time delay introduced by the routine is (24n A,D,E & F/
+ 17) x basic machine cycle.
N # 0.
Display PC Content: This routine displays the
pc content and the first byte of the instruction
03C3 DISPLPC ALL
stored. The inputs and outputs in this case are
none.
Display/Modify Data
This routine display/modify the data. The inputs
and outputs in this routine are:
A, B, C, D,
03E2 DMDT Input: E
Hl – 1 if a memory address was received.- 0 If no
data was received a – termination Character de -
the data received hl – same AS Input
71
Address Registers
Label Description
of routine Affected
This routine is used in SIOD mode, when the

keyboard is inactive. this routine outputs a single
character to the user on siod. The inputs and A, B, D &
03FA ECHO outputs are reg. C. Character to echo to the E
terminal.
Output: reg. c: same as input.
This routine examine/modify a memory block.

EMM The inputs for this routine are hl- first memory A,B,C,H,L
0417
(Common) location to be examined. & F/FS
Outputs: none.
This routine displays an error on the Display if
the system is in key board mode.
And if the system is in siod mode, it lists a * And
goes to command recognizer.
0455 ERROR The various inputs and outputs are: All
Input: none
Output: none
Receive Hex digits:
If the system is in keyboard mode, this routine
accepts, a hexadecimal number from it, displays it
on the display and returns it as a 16 bit number.
The routine displays error in case of an invalid
terminator. The valid terminators are executing,
next and previous. RST 5.5 should be unmasked
first in this operation. The various inputs and
outputs are reg.
All
0468 RECHEX Reg. B: 0 - Use Address Field.
Reg. B: 1 - Use Data Field.
Outputs: a - the last character received From the
keyboard. D, E - last 4 hex digits Received from
the keyboard. Carry - set if At least one valid hex
digit was Received else reset. if the system is in
siod mode then the number is received from the
appropriate siod and the number is displayed.
Valid terminators are $,’.’ space and ‘.’
72
Label Description
routine Affected
DE = DE - HL:
HILO In this routine de reg. Contents become equal to
04C5
(Common) de reg. Content - hl reg. Contents. Cry set if de A,D,E,F/ FS
was < hl and reset if de was > HL.
Receive A Character From SIOD

This routine waits for a character to be typed
on the siod. When the character is typed, it
sends it back to the siod and returns the ASCII
code value to the Calling routine in register a.
Selection of any of the device can be done by
changing the content of the location - 27FF.
27FF Mode A,B,C,D,E,
04EE RCVCHR
00 Invalid H, & F/FS
01 TTY
02 CRT
If The Ms Bit of This Code Is Set, Ten There
Will Not Be Any Echo Of The Character,
Location 27FD Stores Half Bit Time For Proper
Baud Rate Output - Ascii Code Received From
SIOD.
Insert Hex Digit:

This routine allows inserting hex digit.
A,D,E,
0519 INSDG The inputs and outputs in this routine are Input: H,L& F/FS
reg. A - hex digit to be inserted. Reg. De - hex
:
value. Output: reg. De - hex value with digit
Inserted.
List A Byte On SIOD

This routine takes a byte from siod and converts
it into two hexadecimal digits for listing on siod.
0552 LSTBTE The byte to be listed is stored in reg. A and the A,B,C,D,
siod is selected by changing the contents of the E&F/FS
location 27ff. Contents of location (mode) 27ff =
00 invalid 01 TTY 02 CRT location 27ff stores
half bit time for proper baud rate.
73
Address of Label Description Registers

routine Affected
Read New Address
This routine reads keyboard/siod to find Out if there is a
new address. If the Terminator is exec, it jumps to clear
New Display. In case of any terminator other Than exec it All
05AF
ADD gives error. The various Inputs and outputs are:
Input : hl - old address.
Output cry: 01 if no new value is received Else cry is
reset. Hl: new value of address if received Otherwise 00.
Display The Character
This routine is used to display a Character on the
display. If the system is in siod mode, the routine
returns without any operation. The various inputs to this
routine are given below:
Reg. a: 0 - use address field. 1-use data Field.
Reg. B: 0 - no dot to be displayed 1 - dot at The right
edge of the field. Reg H.l.- starting address of the
Character code.
Character character
Displayed code
0 00
1 01
2 02
3 03
4 04
5 05 A,B,C,D,E,
05D0 Output 6 06 L&F/FS
7 07
8 08
9 09
A 0A
B 0B
C 0C
D 0D
E 0E
F 0F
H 10
L 11
P 12
I 13
R 14
U 15
BLANK 16
74
Address of Label Description Registers

routine Affected
Read The Keyboard

This routine scans the key board for any key to be
0629 RD KB pressed. When a key is pressed, its value is A,H,L & F/FS
returned to the calling routine in register a RST 5.5
should be first un-masked for the proper operation.
Search A Table
This routine searches a table for a byte and if the
search fails, it gives error.
Input : a - the byte to be searched.
De - no. Of bytes is in each entry.
06D0 TSRCH C,H,L & F/ FS
Hl - starting address of the table.
C - no. Of entries in the table.
Output: hl- address where the Comparison was
made.
C - Decremented value of the counter.
Modify Address
If the system is under the control of key board, it
displays 16 bit number stored in 27f4 and 27f5. A,B,C,D,E,
06E3 MOD AD
Input : reg. b - 0 no dot. H,L
1 dot at the right edge of the field. If the system is
in siod mode, 4 hex digits are listed on siod.
Modify Data
If the system is under the control of keyboard, it
displays 8 bit number stored in 27f6. Input: reg. b - A,B,C,D,E,H,L
06FA MODDT
0 no dot. & F/FS
1 dot at the right edge of the field. If the system is
in siod mode, 2 hex digits are listed on the siod.
75
Label Description
routine Affected
Read hi and lo this routine reads the lower limit

and higher limit of addresses from the keyboard.
If no new address is entered, then the lower and
0639 RD HILO higher limit address are not disturbed. ALL
Input: None
Output: None
Relocate A Program This Routine Relocates A

Program Written for one memory Area To
Another Memory Area By Adding A Fixed 16
Bit Number To All The Address References
0653 REL Between And Including (27EA, 27EB) and All
(27EC, 27ED). Lower Limit (27F0, 27F1)
should point to the starting address of the
routine to be relocated and the higher limit
(27f2, 27f3) should point to the last location.
Read two addresses this routine reads two

addresses from key board or siod. The inputs and
outputs are:
Input : none A,B,C,D,E,H,L
06CB RD2AD
, F/FS
Output : reg. bc - IST address reg.
De - IIND address reg. a - terminator of the IIND
address
76
Examples of Subroutines
For subroutine 033F:
This subroutine clears the display.
2000 CD 3F 03 Call 033F ;Subroutine Call

2003 76 HLT ;Halt
For subroutine 06CB:

This routine reads two addresses from key board.
2000 3E 0E MVI A, 0E ; move 0EH in ACC
2002 30 SIM ; UNMASK RST 5.5
2003 CD CB 06 Call 06CB ;Subroutine Call
2006 EF RST5 ; Reset
For subroutine 03E2:
This routine displays the data reside on memory (HL register).
2000 CD E2 03 CALL 03E2 ;Subroutine Call

2003 76 HLT ;Halt
For subroutine 0417
This routine displays a memory address (HL register) with data reside on it.

2000 CD 17 04 Call 0417 ;Subroutine Call
2003 76 HLT ;Halt
For subroutine 0519
This routine allows inserting hex digit in register E which we pass in register A.

2000 3E 19 MVI A, 19 ; move 19H in ACC
2002 CD 19 05 call 0519 ;Subroutine Call
2005 EF RST5 ;Reset
77
For subroutine 0455
This routine displays an error on the display if the system is in key board mode.

2000 CD 55 04 Call 0455 ;Subroutine Call
2003 76 HLT ;Halt
For subroutine 0468

If the system is in keyboard mode, this routine accepts a hexadecimal number from it
and displays it on the display.

2000 3E 0E MVI A, 0E ; Move 0EH IN ACC
2003 06 00 MVI B, 00
2005 CD 68 04 CALL 0468
2008 76 HLT ;Halt
For subroutine 0639
This routine reads the lower limit and higher limit of addresses from the keyboard.
2000 3E 0E MVI A, 0E ; Move 0EH IN ACC
2003 CD 39 06 CALL 0639
2006 76 RST5 ; Halt
78
Sample Programs
Program-1:
Hexadecimal addition of two numbers.
The program takes the content of 2009, adds it to 200A and stores the result back at
200B.
Steps:
1. Initialize HL Reg. pair with address where the first number is lying.
2. Store the number in accumulator.
3. Get the second number.
4. Add the two numbers and store the result in 200B.
5. Go back to Monitor.
Address Opcode Label Mnemonic Comment
2000 21 09 20 Start: LXI H, 2009 Point To 1st no
Load the
2003 7E MOV A,M
Accumulator
2004 23 INX H Advance Pointer
2005 86 ADD M ADD IIND

Number
2006 23 INX H Advance Pointer
2007 77 MOV M,A Store Result

2008 EF RST 5
Example:
Before Execution Address Data
2009 1A First operand 200A 18 Second operand After Execution
Address Data
200B 32 Result in Hex Number
79
Program-2:
The decimal addition of two decimal numbers. The result should not be greater than
199.
The program will add two decimal numbers lying at 200A and 200B. The result will
be stored (in decimal) at 200C.
Steps:
1. Load the contents of first location in Acc.
2. Add it with the contents of second location.
3. Adjust the decimal.
4. Store the result and go back to monitor.
2000 21 0A 20 Start: LXI H, 200A Point To First No.
2003 7E MOV A,M Load It To Accumulator
2004 23 INX H Point to the 2nd No

2005 86 ADD M Add the two nos
2006 27 DAA Convert to Decimal
2007 23 INX H Point to Storage
2008 77 MOV M,A
2009 EF RST 5
Example:
200A 23 Data in decimal 200B 32 Data in decimal After Execution
Address Data
200C 55 Answer in decimal
80
Program-3:
Add two sixteen bit numbers.
This program will add two sixteen bit numbers lying at 200C, 200D, 200E and 200F.
The result is stored at 2010 and 2011. Carry is neglected.
Steps:
1. Load the first number in HL.
2. Load the second number.
3. Add the two and store result.
4. Go back to monitor.
Load the Hi Reg With

2000 2A 2C 20 START: LHLD 200C
First No
Exchange the Hl And

2003 EB XCHG
De Reg
Load the Hl Reg with

2004 2A 0E 20 LHLD 200E
2nd No
Add Hl and De
2007 19 DAD D
Register
Store the Result On

2008 22 10 20 SHLD 2010
2010
200B EF RST 5
Example:
200C CA LSB1
200D A7 MSB1
200E 6B LSB2
200F B9 MSB2
After Execution Address Data
2010 35 LSB1 + LSB2 (CA + 6B)
2011 61 MSB1 + MSB2 (A7 + B9
81
Program-4:
Addition of an 8 bit number series neglecting the carry generated.
This program adds ‘N’ No. of hexadecimal numbers lying from 2101 onwards. The
2100 has the number of hexadecimal bytes to be added. The result is stored at 2100
location.
Steps:
1. Load the contents from 2100 location; give how many bytes are to be added.
2. Initialize Acc. as the result will be stored in Acc.
3. Let the memory to point the number of the bytes to be added into partial
register Acc.
4. Decrement the counter having no. of bytes.
5. Check if zero - No. repeat from point 3.
6. Store the result at 2100 location.
Go back to monitor.
2000 21 00 21 Start: LXI H,2100 Point To First No
2003 46 MOV B,M Load Count In To B Register
2004 AF XRA A Clear A Register
2005 23 INX H Point to the First Location
2006 86 ADD M Add Memory to Total
2007 05 DCR B Subtract From Count
2008 C2 05 20 JNZ 2005 Test to See If Done
200B 32 00 01 STA 2100 Save The Result
200E EF RST 5
82
Example:
Before Execution
Address Data
2100 04 The no. of hexadecimal no. to be added
2101 10 First Hex No.
2102 02 Second Hex No.
2103 08 Third Hex No.
2104 04 Fourth Hex No.
After Execution Address Data

2100 1E Answer is in Hexadecimal
83
Program-5:
Separation of hexadecimal number into two digits.
This program breaks the byte of data stored at 2100 into two nibbles. The MS nibble
and LS nibble are stored at 2102 and 2101 location respectively.
Steps:
1. Load the byte into Acc.
2. Clear the MS nibble and store it at 2101.
3. Load the byte from 2100.
4. Clear the LS nibble and store it at 2102.
5. Go Back To Monitor.
2000 3A 00 21 Start: LDA 2100 Get the Number
2003 E6 0F ANI 0F Mask off The First Four Bits
2005 32 01 21 STA 2101 Store Result 1
2008 3A 00 21 LDA 2100 Get the Number
200B E6 F0 ANI F0
200D 32 02 21 STA 2102 Store Result 2
2010 EF RST 5
Example:
2100 AF Number stored
2101 00 Memory before program execution
After Execution
Address Data
2100 AF Number stored
2101 0F LSB separated from AF
2102 A0 MSB separated from AF
84
Program-6:
Combination of two hex nibbles to from one byte number.
The program takes two nibbles from 2100, 2101 and combines to form a byte. The
nibbles from 2100 are taken as MS nibble of the byte to be formed.
Steps:
1. Initialize memory pointer with 2100 and load MS nibble into Acc.
2. Shift the four bits towards the left, the shifted information is stored in Acc.
3. Point to next location 2101 and „OR its contents with the contents of Acc.
4. Increment the memory pointer to store the result at 2102.
5. Go back to Monitor.
2000 21 00 21 Start: LXI H,2100 Point To 1st Number
2003 7E MOV A,M

2004 07 RLC Move To MSB
2005 07 RLC
2006 07 RLC
2007 07 RLC
2008 23 INX H
2009 B6 ORA M Or The Two Numbers
200A 23 INX H
200B 77 MOV M, A Store The Result
200C EF RST 5
Example:
Before Execution
Address Data
2100 04 MSB
2101 05 LSB
After Execution
Address Data
2100 04 MSB
2101 05 LSB
2102 45 Memory after program execution
85
Program 7:
Multiplication by two, employing bit rotation.
The program multiplies a hex number stored in location 200A with two and stores the
result in location 200B. It uses the bit rotation technique.
Steps:
1. Load the data of location 200A in the Acc.
2. Set the carry flag to zero.
3. Rotate the Acc. through carry.
4. Store the contents of Acc. in 200B.
5. Go back to monitor.
2000 3A 0A 20 Start: LDA 200A
2003 37 STC Set the Carry flag to 1
2004 3F CMC Complement The Carry
2005 17 RAL Rotate acc. To left
2006 32 0B 20 STA 200B Store The Result at 200B
2009 EF RST 5 Go To Monitor
Example:
Before Execution After Execution
Address Data Address Data
200A 1A 200B 34
86
Program-8:
1's Complement of a 16-Bit Number
The 16bit number is stored in 2050, 2051 The answer is stored in 2052, 2053
2000 21 50 20 LXI H,2050 ;Index For Data Source
2003 7E MOV A,M ;Load Register A With Data On 2050
2004 2F CMA ;Complement Accumulator
2005 32 52 20 STA 2052 ;Store The Accumulator Data On 2052 Location
2008 23 INX H ;Increment Register H By 1
;Load Data In To Accumulator Form Memory

2009 7E MOV A,M
Location 2052
200A 2F CMA ;Complement Accumulator
200B 32 53 20 STA 2053 ;Load Accumulator Data On 2053 Location
200E 76 HLT ;Halt

Example:

2050 85 2052 7A
2051 54 2053 AB
87
Program-9:
1's Complement of an 8-Bit Number
The number to be complemented is stored in 2050
2000 3A 50 20 LDA 2050 ;Load The Accumulator By Data On 2050
2003 2F CMA ;Complement Accumulator
2004 32 51 20 STA 2051 ;Store The Content Of Accumulator On Location 2051
2007 76 HLT ;Halt
Example:
2050 85 2051 7A
Answer is stored in 2051
88
Program-10:
2's Complement of a 16-Bit Number
2000 21 50 20 LXI H,2050 ;Load The Address 2050 In Register H
2003 06 00 MVI B,00 ;Load Register B With 00
2005 7E MOV A,M ;Load The Accumulator By Data On

2050
;Complement The Content Of
2006 2F CMA
Accumulator
2007 C6 01 ADI 01 ;Add 1 To Accumulator
2009 32 52 20 STA 2052 ;store the content of accumulator on

2052
;Jump On Location 2010 If No Carrey
200C D2 10 20 JNC 2010
Flag Is Set
;Increment The Content Of Memory

200F 04 INR B
Register B
2010 23 INX H ;Increment The H Register By 1
2011 7E MOV A,M ;Load Accumulator By Data On 2053
2012 2F CMA ;Complement The Accumulator
;Move The Content Of Accumulator On

2013 32 53 20 STA 2053
2053 Location
2016 76 HLT ;Halt
The 16-bit number is stored in 2050, 2051. The answer is stored in 2052, 2053.
Example:

2050 8C (MSB) 2052 74
2051 5B (LSB) 2053 A4
89
Program-11:
2's Complement of an 8-Bit Number
The number to be complemented is stored in 2050. Answer is stored in 2051.
2000 3A 50 20 LDA 2050 ;Load Accumulator By 2050 Location Data
2003 2F CMA ;Complement The Accumulator
2004 3C INR A ;Increment The Content Of Accumulator
2005 32 51 20 STA 2051 ;Move Content Of Accumulator On 2051 Location
2008 76 HLT ;Halt
Example:
2050 96 2052 6A
90
Program-12:
8 Bit Decimal Subtraction
If 2nd no is greater than 1st no then the answer will in 2's complement Manually store
1st 8 bit no in the memory location 2050.
Manually store 2nd 8 bit no in the memory location 2051. Result is stored in 2052.
2000 21 51 20 LXI H,2051 ;Load The Content of Accumulator 2051
2003 3E 99 MVI A,99 ; Move 99H to ACC
2005 96 SUB M ;Subtract Memory Content From Acc Content
2006 3C INR A ;Increment Acc Content By 1
2007 2B DCX H ;Decrement Hl Register Pair By 1
2008 86 ADD M ; Add Memory Content With Acc Content
2009 27 DAA ;Decimal Adjust ACC
200A 32 52 20 STA 2052 ; Move Content of Accumulator On 2052 Location
200D 76 HLT ; Halt
Example:
99-48=51
2050 99 2052 51
2051 48
91
Program-13:
Addition of two 8-bit numbers
Manually store 1st no in the memory location 2050. Manually store 2nd no in the
memory location 2051. Result is stored in 2053
2000 21 50 20 LXI H,2050 ;Load 2050 To Hl Register Pair
2003 7E MOV A,M ;Move Content Of Memory To ACC
2004 23 INX H ;Increment Hl Register Pair By 1
2005 86 ADD M ;Add Content of Memory To Acc
;Content of Acc Are Copied To 2052

2006 32 52 20 STA 2052
Memory Location
2009 76 HLT ; Halt
Example:

2050 10 2052 20
2051 10
92
Program-14:
Fibonacci Series Generation
2000 0E 09 Start : MVI C,09 ;Counter Loaded
21 50 H,205 ;Memory Pointer(Load 2050h In Register

2002 LXI
20 0 Pair)
2005 7E MOV A,M ; Move Content Of Memory To ACC
2007 46 MOV B,M ; Move Content Of Memory To B Register
2009 80 ADD B ;ACC=ACC+B
200A 27 DAA ;Decimal Adjust ACC
200B 77 MOV M,A ; Move Content Of Acc To Memory
200C 2B DCX H ; Decrement Hl Register Pair By 1
200D 0D DCR C ;Content Of Register C Is Decremented By 1
200E C2 05 JNZ 2005 ;Jump To 2005 Memory Location If No Zero

20
2011 CF RST 1 ;Reset
To run the Program simply load at memory location 2050=01, 2051=01
93

2050 01 2050 01
2051 01 2051 01
2052 02
2053 03
2054 05
2055 08
2056 13
2057 21
2058 34
2059 55
205A 89
94
Program 15:
Addition of two 16-bit numbers; Sum: 16 bits or more
Manually store 1st 16 bit no in the memory location 2050 & 2051 in reverse order
Manually store 2nd 16 bit no in the memory location 2052 & 2053 in reverse order
Result is stored in 2053, 2054 & 2055 in reverse order
2000 2A 50 LHLD 2050 ;Load H & L Registers Direct

20
2003 EB XCHG ;Exchange H & L with D & E
2004 2A 52 LHLD 2052 ; Load H & L Registers Direct

20
2007 0E 00 MVI C.00 ;Copy 00H to Reg C
2009 19 D2 DAD D ;Add De Register Pair To Hl Register Pair
200A D2 0C JNC 200C ;JMP To 200C If No Carry

20
200D 0C INR C ;Increment The Content of Register C
200E 22 54 20 SHLD 2054 ;Store H & L Registers Direct
2011 79 MOV A,C ; Copy Reg C Content to Acc
2012 32 56 20 STA 2056 ; Copy Acc Content to Memory Location 2056
2015 76 HLT ; Halt
Example: A645+9B23=014168
2050 45 2054 68
2051 A6 2055 41
2052 23 2056 01
2053 9B
95
Program 16:
Mask off Least Significant 4 Bits of an 8-Bit Number.
The number to be masked is stored in 2050. Answer is stored in 2051.
3A 50 ;Load Acc Direct With The Content of Memory

2000 LDA 2050
20 Location 2050
;Logical ANDING F0h With Acc Content &

2003 E6 F0 ANI F0
Store Result In Acc
2005 32 51 20 STA 2051 ; Store Acc Content To Memory Location 2051
2008 76 HLT ; Halt

Example:
2050 96 2051 90
96
Program 17:
Mask off Most Significant 4 Bits of an 8-Bit Number
The number to be masked is stored in 2050. Answer is stored in 2051.
;Load Acc With The Content of Memory

2000 3A 50 20 LDA 2050
Location 2050H
;Logical Anding F0h With Acc Content & Store

2003 E6 0F ANI 0F
Result In Acc
2005 32 51 20 STA 2051 ;Store Acc Content To Memory Location 2051
2006 76 HLT ; Halt
Example:
2050 96 2051 06
97
Program 18:
Shift an 8-Bit Number Left by 1 Bit The number to be shifted is stored in 2050
3A 50 ;l Load Acc With The Content of Memory Location

2000 LDA 2050
20 2050H
2003 87 ADD A ;This Cannot Be Achieved By RLC
2004 32 51 20 STA 2051 ;Copy Acc Content To Memory Location 2051

2007 76 HLT ; Halt
Example:
2050 65 2051 CA
98
Program 19:
Shift an 8-Bit Number Left by 2 Bits The number to be shifted is stored in 2050
;Load Acc Direct with Content of Memory

2000 3A 50 20 LDA 2050
Location 2050H
2004 87 ADD A
;Copy Acc Content To Memory Location

2005 32 51 20 STA 2051
2051
2008 76 HLT ; HALT
Example:
2050 15 2051 54
99
Program 19:
Shift an 8-Bit Number Left by 2 Bits The number to be shifted is stored in 2050
;Load Acc Direct With Content Of Memory

2000 3A 50 20 LDA 2050
Location 2050H
2004 87 ADD A
;Copy Acc Content To Memory Location

2005 32 51 20 STA 2051
2051
2008 76 HLT ; Halt

Example:
2050 15 2051 54
100
Program 20:
Shift a 16-Bit Number Left by 1 Bit
The number to be shifted is stored in 2050 & 2051 Answer is stored in 2052 & 2053
2000 2A 50 20 LHLD 2050 ;Load H & L Registers Direct
2003 29 DAD H ;This Cannot Be Achieved By RLC
2004 22 52 20 SHLD 2052 ; Store H & L Registers Direct
2007 76 HLT ; Halt
Example:

2050 96 2052 2C
2051 75 2053 EB
101
Program 21:
Shift a 16-Bit Number Left by 2 Bits
The number to be shifted is stored in 2050 & 2051. Answer is stored in 2052 & 2053.
2000 2A 50 20 LHLD 2050 ;;Load H & L Registers Direct
2003 29 DAD H ;This Cannot Be Achieved By RLC
;Multiply The Contents Of Hl Register Pair By

2004 29 DAD H
2
2005 22 52 20 SHLD 2052 ; Store H & L Registers Direct
2008 76 HLT ;Halt
Example:

2050 96(MSB) 2052 58
2051 15(LSB) 2053 56
102
Program 22:
Subtraction of two 8bit numbers
Store 1st no in the memory location 2050. Store 2nd no in the memory location 2051.
2000 21 50 20 LXI H,2050 ;Load 2050h In Hl Register Pair
; The Content of Memory Location Pointed By Hl

2003 7E MOV A,M
Register Pair Is Copied To ACC
2004 23 INX H ; Increment HL Register Pair By 1
2005 96 SUB M ;Subtract Content Of Memory Location From ACC
2006 23 INX H ;Increment Hl Register Pair By 1

;The Content of Acc IS Copied To Memory Location
2007 77 MOV M,A
Pointed By Hl Register Pair
2008 76 HLT ;Halt
Example:
2050 FF 2052 11
2051 EE
103
Connector Details
The pin details of the various connectors are given here for your reference.
Bus Connector-CN1 (for Model: Nvis 5585)
Pin 1 Signals Vcc Pin 2 Signals Vcc

3 GND 4 GND
5 AD3 6 AD7
7 AD2 8 AD6
9 AD1 10 AD5
11 AD0 12 AD4
13 A7 14 A15
15 A6 16 A14
17 A5 18 A13
19 A4 20 A12
21 A3 22 A11
23 A2 24 A10
25 A1 26 A9
27 A0 28 A8
29 WR 30 RD
31 IORQ 32 MEMRQ
33 RST 6.5 34 RST 6.5
35 ALE 36 ALE
37 S1 38 S0
39 BUSACK 40 BUSRQ
41 INTA 42 INTR
43 READY 44 NMI
45 RESET OUT 46 RESET IN
47 CLK OUT 48 CS-I/O
49 CS-MEM 50 CS-MEM
104
8253 Connector-CN2 (for Model: Nvis 5585)
Pin Signals Pin Signals
1 CLK2 2 OUT2
3 CLK1 4 GATE2
5 GATE1 6 CLK0
7 OUT1 8 OUT0
9 GND 10 GATE0

1 P1C4 14 P1B1
2 P1C5 15 P1A6
3 P1C2 16 P1A7
4 P1C3 17 P1A4
5 P1C0 18 P1A5
6 P1C1 19 P1A2
7 P1B6 20 P1A3
8 P1B7 21 P1A0
9 P1B4 22 P1A1
10 P1B5 23 P1C6
11 P1B2 24 P1C7
12 P1B3 25 GND
13 P1B0 26 VCC
105
Power Supply Connector for Interfacing Modules (Right Side Bottom near
Mains Socket):-
Gnd +5V +12V -12V
1 2 3 4 5

1 Gnd 2 +5V
3 Blank 4 +12V
5 -12V
Serial (RS-232C) Connector-CN5 (for Model: Nvis 5585)

1 RX 2 TX
3 GND
1 PC4 14 PB1
2 PC5 15 PA6
3 PC2 16 PA7
4 PC3 17 PA4
5 PC0 18 PA5
6 PC1 19 PA2
7 PB6 20 PA3
8 PB7 21 PA0
9 PB4 22 PA1
10 PB5 23 TIMER IN
11 PB2 24 TIMER OUT
12 PB3 25 GND
13 PB0 26 VCC
106
Jumper Details
For Nvis 5585:
JP 1
Short 1 & 2 for Vcc to RAM
Short 2 & 3 for Battery Supply to RAM
Factory Setting Short 1& 2
107
Frequently Asked Questions
Q1. What is Microprocessor?
Ans. It is a program controlled semiconductor device (IC}, which fetches, decodes
and executes instructions.
Q2. What are the basic units of a microprocessor?
Ans. The basic units of a microprocessor are ALU, an array of registers and control
unit.
Q3. What is Software and Hardware?
Ans. The Software is a set of instructions or commands needed for performing a
specific task by a programmable device or a computing machine. The Hardware
refers to the components or devices used to form computing machine in which the
software can be run and tested. Without software the Hardware is an idle machine.
Q4. What is assembly language?
Ans. The language in which the mnemonics (short -hand form of instructions) are
used to write a program is called assembly language. The manufacturers of
microprocessor give the mnemonics.
Q5. What are machine language and assembly language programs?
Ans. The software developed using 1's and 0's are called machine language programs.
The software developed using mnemonics are called assembly language programs.
Q6. What is the drawback in machine language and assembly language
programs? Ans. The machine language and assembly language programs are
machine dependent. The programs developed using these languages for a particular
machine cannot be directly run on another machine.
Q7. Define bit, byte and word.
Ans. A digit of the binary number or code is called bit. Also, the bit is the
fundamental storage unit of computer memory. The 8-bit (8-digit) binary number or
code is called byte and 16-bit binary number or code is called word.
Q8. What is a bus?
Ans. Bus is a group of conducting lines that carries data, address and control signals.
Q9. Why data bus is bi-directional?
Ans. The microprocessor has to fetch (read) the data from memory or input device for
processing and after processing, it has to store (write) the data to memory or output
device. Hence the data bus is bi-directional.
108
Q10. Why address bus is unidirectional?
Ans. The address is an identification number used by the microprocessor to identify
or access a memory location or I / O device. It is an output signal from the processor.
Hence the address bus is unidirectional.
Q11. What is the function of microprocessor in a system?
Ans. The microprocessor is the master in the system, which controls all the activity of
the system. It issues address and control signals and fetches the instruction and data
from memory. Then it executes the instruction to take appropriate action.
Q12. Define machine cycle.
Ans. Machine cycle is defined as the time required to complete one operation of
accessing memory, I/O, or acknowledging an external request. This cycle may consist
of three to six T-states.
Q13. Define T-State.
Ans. T-State is defined as one subdivision of the operation performed in one clock
period. These subdivisions are internal states synchronized with the system clock, and
each T-State is precisely equal to one clock period.
Q14. List the components of microprocessor (single board microcomputer)
based system. Ans. The microprocessor based system consists of microprocessor as
CPU, semiconductor memories like EPROM and RAM, input device, output device
and interfacing devices.
Q15. Why interfacing is needed for I/O devices?
Ans. Generally I/O devices are slow devices. Therefore the speed of I/O devices does
not match with the speed of microprocessor. And so an interface is provided between
system bus and I/O devices.
Q16. What does memory-mapping mean?
Ans. The memory mapping is the process of interfacing memories and peripheral to
microprocessor and allocating addresses to each device.
Q17. What is interrupt I/O?
Ans. If the I/O device initiates the data transfer through interrupt then the I/O is called
interrupt driven I/O.
Q18. What is the need for system clock and how it is generated in 8085?
Ans. The system clock is necessary for synchronizing various internal operations or
devices in the microprocessor and to synchronize the microprocessor with other
peripherals in the system.
Q19. What is the need for port?
Ans. The I/O devices are generally slow devices and their timing characteristics do
not match with processor timings. Hence the I/O devices are connected to system bus
through the ports.
109
Q20. What is a port?
Ans. The port is a buffered I/O, which is used to hold the data transmitted from the
microprocessor to I/O device or vice-versa.
Q21. Give some examples of port devices used in 8085 microprocessor based
system? Ans. The various INTEL I/O port devices used in 8085 microprocessor
based system are 8212, 8155, 8156, 8255, 8355 and 8755
Q22. Write a short note on INTEL 8255?
Ans. The INTEL 8255 is a I/O port device consisting of 3 numbers of 8 –bit parallel
I/O ports. The ports can be programmed to function either as a input port or as a
output port in different operating modes. It requires 4 internal addresses and has one
logic LOW chip select pin.
Q23. What is Instruction cycle?
Ans. The sequence of operations that a processor has to carry out while executing the
instruction is called Instruction cycle. Each instruction cycle of a processor indium
consists of a number of machine cycles.
Q24. What is fetch and execute cycle?
Ans. The instruction cycle of an instruction can be divided into fetch and execute
cycles. The fetch cycle is executed to fetch the opcode from memory. The execute
cycle is executed to decode the instruction and to perform the work instructed by the
instruction.
Q25. What is the need for timing diagram?
Ans. The timing diagram provides information regarding the status of various signals,
when a machine cycle is executed. The knowledge of timing diagram is essential for
system designer to select matched peripheral devices like memories, latches, ports,
etc., to form a microprocessor system.
Q26. What is an Interrupt?
Ans. Interrupt is a signal send by an external device to the processor so as to request
the processor to perform a particular task or work.
Q27. Define opcode and operand.
Ans. Opcode (Operation code) is the part of an instruction / directive that identifies a
specific operation. Operand is a part of an instruction / directive that represents a
value on which the instruction acts.
Q28. What is opcode fetch cycle?
Ans. The opcode fetch cycle is a machine cycle executed to fetch the opcode of an
instruction stored in memory. Every instruction starts with opcode fetch machine
cycle.
Q29. What operation is performed during first T-state of every machine cycle in
8085? Ans. In 8085, during the first T -state of every machine cycle the low byte
address is latched into an external latch using ALE signal.
110
Q30. Why status signals are provided in microprocessor?
Ans. The status signals can be used by the system designer to track the internal
operations of the processor. Also, it can be used for memory expansion (by providing
separate memory banks for program & data and selecting the bank using status
signals).
Q31. When the 8085 processor checks for an interrupt?
Ans. In the second T-state of the last machine cycle of every instruction, the 8085
processor checks whether an interrupt request is made or not
Q32. What is interrupt acknowledge cycle?
Ans. The interrupt acknowledge cycle is a machine cycle executed by 8085 processor
to get the address of the interrupt service routine in-order to service the interrupt
device.
Q33. How the interrupts are affected by system reset?
Ans. Whenever the processor or system is reset, all the interrupts except TRAP are
disabled. In order to enable the interrupts, EI instruction has to be executed after a
reset.
Q34. What is Software interrupts?
Ans. The Software interrupts are program instructions. These instructions are inserted
at desired locations in a program. While running a program, if software interrupt
instruction is encountered then the processor executes an interrupt service routine.
Q35. What is Hardware interrupt?
Ans. If an interrupt is initiated in a processor by an appropriate signal at the interrupt
pin, then the interrupt is called Hardware interrupt.
Q36. What is the difference between Hardware and Software interrupt?
Ans. The Software interrupt is initiated by the main program, but the Hardware
interrupt is initiated by an external device. In 8085, the Software interrupt cannot be
disabled or masked but the Hardware interrupt except TRAP can be disabled or
masked.
Q37. What is Vectored and Non- Vectored interrupt?
Ans. When an interrupt is accepted, if the processor control branches to a specific
address defined by the manufacturer then the interrupt is called vectored interrupt. In
Non-vectored interrupt there is no specific address for storing the interrupt service
routine. Hence the interrupted device should give the address of the interrupt service
routine.
Q38. List the Software and Hardware interrupts of 8085?
Ans. Software interrupts: RST 0, RST l, RST 2, RST 3, RST 4, RST 5, RST 6 and
RST 7. Hardware interrupts: TRAP, RST 7.5, RST 6.5, RST 5.5 and INTR.
111
Q39. What is TRAP?
Ans. The TRAP is non-maskable interrupt of 8085. It is not disabled by processor
reset or after recognition of interrupt.
Q40. Whether HOLD has higher priority than TRAP or not?
Ans. The interrupts including TRAP are recognized only if the HOLD is not valid;
hence TRAP has lower priority than HOLD.
Q41. What is masking and why it is required?
Ans. Masking is preventing the interrupt from disturbing the current program
execution. When the processor is performing an important job (process) and if the
process should not be interrupted then all the interrupts should be masked or disabled.
In processor with multiple 'interrupts, the lower priority interrupt can be masked so as
to prevent it from interrupting, the execution of interrupt service routine of higher
priority interrupt.
Q42. When the 8085 processor accept hardware interrupt?
Ans. The processor keeps on checking the interrupt pins at the second T-state of last
Machine cycle of every instruction. If the processor finds a valid interrupt signal and
if the interrupt is unmasked and enabled then the processor accepts the interrupt.
Q43. When the 8085 processor will disable the interrupt system?
Ans. The interrupts of 8085 except TRAP are disabled after anyone of the following
operations: 1. System or processor reset. 2. After recognition (acceptance) of an
interrupt.
Q44. What is the function performed by Dl instruction?
Ans. By this instruction Interrupt Enable flip-flop is reset and all the interrupts except
the TRAP are disabled.
Q45. What is the function performed by El instruction?
Ans. By this instruction the Interrupt Enable flip-flop is set and all interrupts are
enabled.
Q46. How the vector address is generated for the INTR interrupt of 8085?
Ans. For the interrupt INTR, the interrupting device has to place either RST opcode
or CALL opcode followed by l6-bit address. RST opcode is placed then the
corresponding vector address is generated by the processor. In case of CALL opcode
the given l6-bit address will be the vector address.
Q47. How clock signals are generated in 8085 and what is the frequency of the
internal clock?
Ans. The 8085 has the clock generation circuit on the chip but an external quartz
crystal or LC circuit or RC circuit should be connected at the pins XI and X2. The
maximum internal clock frequency of 8085A is 3.03 MHz.
112
Q48. What happens to the 8085 processor when it is reset?
Ans. When the 8085 processor is reset it executes the first instruction at the 0000H
location. The 8085 resets (clears) instruction register, interrupt mask bits and other
registers.
Q49. What are the operations performed by ALU of 8085?
Ans. The operations performed by ALU of 8085 are Addition, Subtraction, Logical
AND, OR, Exclusive OR, Compare Complement, Increment, Decrement Left shift
and Right shift.
Q50. What is a flag?
Ans. Flag is a flip flop used to store the information about the status of the processor
and the status of the instruction executed most recently.
Q51. List the flags of 8085.
Ans. There are five flags in 8085. They are sign flag, zero flag, auxiliary carry flag,
parity flag and carry flag.
Q52. What is the Hardware interrupts of 8085?
Ans. The hardware interrupts in 8085 are TRAP, RST 7.5, RST 6.5 and RST 5.5
Q53. Which interrupt has highest priority in 8085? What is the priority of other
interrupts?
Ans. The TRAP has the highest priority, followed by RST 7.5, RST 6.5, RST 5.5 and
INTR.
Q54. What is ALE?
Ans. The ALE (Address Latch Enable) is a signal used to demultiplex the address and
data lines, using an external latch. It is used to enable the external latch.
Q55. Explain the function of IO/M’ in 8085.
Ans. The IO/M‟ is used to differentiate memory access and I/O access. For IN and
OUT instruction it is high. For memory reference instructions it is low.
Q56. Where is the READY signal used?
Ans. READY is an input signal to the processor, used by the memory or I/O devices
to get extra time for data transfer or to introduce wait states in the bus cycles.
Q57. What are HOLD and HLDA and how it is used?
Ans. HOLD and hold acknowledge (HLDA) signals are used for the Direct Memory
Access (DMA) type of data transfer. The DMA controller places a high on HOLD pin
in order to take control of the system bus. The HOLD request is acknowledged by the
8085 by driving all its tristated pins to high impedance state and asserting HLDA
signal high.
Q58. What is polling?
Ans. Polling is a scheme or an algorithm to identify the devices interrupting the
processor. Polling is employed when multiple devices interrupt the processor through
one interrupt pin of the processor.
113
Q59. What are the different types of Polling?
Ans. The polling can be classified into software and hardware polling. In software
polling the entire polling process is governed by a program .In hardware polling, the
hardware takes care of checking the status of interrupting devices and allowing one
by one to the processor.
Q60.What is the need for interrupt controller?
Ans. The interrupt controller is employed to expand the interrupt inputs. It can handle
the interrupt request from various devices and allow one by one to the processor.
Q61. List some of the features of INTEL 8259 (Programmable Interrupt
Controller). Ans. 1. It manages eight interrupt requests. 2. The interrupt vector
addresses are programmable. 3. The priorities of interrupts are programmable. 4. The
interrupt can be masked or unmasked individually.
Q62. What is a programmable peripheral device?
Ans. If the functions performed by a peripheral device can be altered or changed by a
program instruction then the peripheral device is called programmable device.
Usually the programmable devices will have control registers. The device can be
programmed by sending control word in the prescribed format to the control register
Q63. What is synchronous data transfer scheme?
Ans. For synchronous data transfer scheme, the processor does not check the
readiness of the device after a command has been issued for read/write operation. In
this scheme the processor will request the device to get ready and then read/write to
the device immediately after the request. In some synchronous schemes a small delay
is allowed after the request.
Q64. What is asynchronous data transfer scheme?
Ans. In asynchronous data transfer scheme, first the processor sends a request to the
device for read/write operation. Then the processor keeps on polling the status of the
device. Once the device is ready, the processor executes a data transfer instruction to
complete the process.
Q65. What are the operating modes of 8212?
Ans. The 8212 can be hardwired to work either as a latch or tri-state buffer. If mode
(MD) pin is tied HIGH then it will work as a latch and so it can be used as output
port. If mode (MD) pin is tied LOW then it work as tri- state buffer and so it can be
used as input port.
Q66. Explain the working of a handshake output port.
Ans. In handshake output operation, the processor will load a data to port. When the
port receives the data, it will inform the output device to collect the data. Once the
output device accepts the data, the port will inform the processor that it is empty.
Now the processor can load another data to port and the above process is repeated.
114
Q67. What are the internal devices of 8255?
Ans. The internal devices of 8255 are port-A, port-B and port-C. The ports can be
programmed for either input or output function in different operating modes.
Q68. What is baud rate?
Ans. The baud rate is the rate at which the serial data are transmitted. Baud rate is
defined as l / (The time for a bit cell). In some systems one bit cell has one data bit,
then the baud rate and bits/sec are same.
Q69. What is USART?
Ans. The device which can be programmed to perform Synchronous or
Asynchronous serial communication is called USART (Universal Synchronous
Asynchronous Receiver Transmitter). The INTEL 8251A is an example of USART.
Q70. What are the functions performed by INTEL 8251A?
Ans. The INTEL 825lA is used for converting parallel data to serial or vice versa.
The data transmission or reception can be either asynchronously or synchronously.
The 8251A can be used to interface MODEM and establish serial communication
through MODEM over telephone lines.
Q71. How many machine cycles constitute one instruction cycle in 8085?
Ans. Each instruction of the 8085 processor consists of one to five machine cycles.
The number of machine cycles varies from instruction to instruction.
Q72. What are the control words of 8251A and what are its functions?
Ans. The control words of 8251A are mode word and command word. The mode
word informs 8251 about the baud rate, character length, parity and stop bits. The
command word can be send to enable the data transmission and reception.
Q73. What is the information that can be obtained from the status word of 8251?
Ans. The status word can be read by the CPU to check the readiness of the transmitter
or receiver and to check the character synchronization in synchronous reception. It
also provides information regarding various errors in the data received. The various
error conditions that can be checked from the status word are parity error, overrun
error and framing error.
Q74. Give some examples of input devices to microprocessor-based system.
Ans. The input devices used in the microprocessor-based system are Keyboards, DIP
switches, ADC, Floppy disc, etc.
Q75. What are the tasks involved in keyboard interface?
Ans. The tasks involved in keyboard interfacing are sensing a key actuation,
debouncing the key and generating key codes (Decoding the key). These tasks are
performed software if the keyboard is interfaced through ports and they are performed
by hardware if the keyboard is interfaced through 8279.
115
Q76. How a keyboard matrix is formed in keyboard interface using 8279?
Ans. The return lines, RL0 to RL7 of 8279 are used to form the columns of keyboard
matrix. In decoded scan the scan lines SL0 to SL3 of 8279 are used to form the rows
of keyboard matrix. In encoded scan mode, the output lines of external decoder are
used as rows of keyboard matrix.
Q77. What is scanning in keyboard and what is scan time?
Ans. The process of sending a zero to each row of a keyboard matrix and reading the
columns for key actuation is called scanning. The scan time is the time taken by the
processor to scan all the rows one by one starting from first row and coming back to
the first row again.
Q78. What is scanning in display and what is the scan time?
Ans. In display devices, the process of sending display codes to 7 –segment LEDs to
display the LEDs one by one is called scanning ( or multiplexed display). The scan
time is the time taken to display all the 7-segment LEDs one by one, starting from
first LED and coming back to the first LED again.
Q79. What are the internal devices of a typical DAC?
Ans. The internal devices of a DAC are R-2R resistive network, an internal latch and
current to voltage converting amplifier.
Q80. What is conversion time in DAC?
Ans. The time taken by the DAC to convert a given digital data to corresponding
analog signal is called conversion time.
Q81. What are the different types of ADC?
Ans. The different types of ADC are successive approximation ADC, counter type
ADC flash type ADC, integrator converters and voltage-to- frequency converters.
Q82. Define stack.
Ans. Stack is a sequence of RAM memory locations defined by the programmer.
Q83. What is program counter? How is it useful in program execution?
Ans. The program counter keeps track of program execution. To execute a program
the starting address of the program is loaded in program counter. The PC sends out an
address to fetch a byte of instruction from memory and increments its content
automatically.
Q84. How the microprocessor is synchronized with peripherals?
Ans. The timing and control unit synchronizes all the microprocessor operations with
clock and generates control signals necessary for communication between the
microprocessor and peripherals.
116
Warranty
1) We guarantee the product against all manufacturing defects for 12 months from the date
of sale by us or through our dealers.
2) The guarantee will become void, if
a) The product is not operated as per the instruction given in the learning material.
b) The agreed payment terms and other conditions of sale are not followed.
c) The customer resells the instrument to another party.
d) Any attempt is made to service and modify the instrument.
3) The non-working of the product is to be communicated to us immediately giving full
details of the complaints and defects noticed specifically mentioning the type, serial
number of the product and date of purchase etc.
4) The repair work will be carried out, provided the product is dispatched securely packed
and insured. The transportation charges shall be borne by the customer.
117
References
http://nptel.iitm.ac.in/courses/
http://www.cpu-world.com/CPUs/8085/index.html
118

Nvis-8085-V1mp Kit

Hochgeladen von

Dokumentinformationen

Originalbeschreibung:

Originaltitel

Copyright

Verfügbare Formate

Dieses Dokument teilen

Dokument teilen oder einbetten

Freigabeoptionen

Stufen Sie dieses Dokument als nützlich ein?

Sind diese Inhalte unangemessen?

Copyright:

Verfügbare Formate

Nvis-8085-V1mp Kit

Hochgeladen von

Copyright:

Verfügbare Formate

Nvis 5585 8085 Microprocessor Trainer

8085 Microprocessor Trainer

The main features of 8085 microprocessor are:

· Data bus is a group of 8 lines D0 – D7 . It supports external interrupt request. A

The following describes the function of each pin:

S1 can be used as an advanced R/W status.

Reset the system.

Hardware interrupts via keyboard, RST 7.5.

Provides a second level command to all keys. To execute the program.

To execute the program in single step mode

Examine Register; allows user to examine and modify the contents of

Allows user to move a block of memory to any RAM area.

Allows user to fill RAM area with a constant.

Relocates a program written for some memory area and to be transferred

Move the Contents of A Value into

2003 EF RST 5 Software Breakpoint

Terminate the command again.

To run the program further presses SHIFT and SI.

Since 9 bytes have to be entered,

The contents of 20 1E is displayed.

Verify that 22 is filled from 2000 to 2050.

Since the two blocks are identical a „-‘ will be displayed.

Enter a Memory Block

Address Opcode Mnemonic Comment

2000 0E 09 Start : MVI C,09 ;Counter Loaded

H,205 ;Memory Pointer(Load 2050h In Register

2005 7E MOV A,M ; Move Content of Memory To Acc

2006 23 INX H ; Increment Hl Register Pair By 1

2007 46 MOV B,M ; Move Content of Memory To B Register

2008 23 INX H ; Increment Hl Register Pair By 1

2009 80 ADD B ;ACC=ACC+B

200A 27 DAA ;Decimal Adjust ACC

200B 77 MOV M,A ; Move Content of ACC to memory

200C 2B DCX H ; Decrement Hl Register Pair By 1

200D 0D DCR C ;Content Of Register C Is Decremented By 1

200E C2 05 20 JNZ 2005 ;Jump To 2005 Memory Location If No Zero

2011 CF RST 1 ;Reset

· A window appears as shown below

· Run MASM file in below mention format

· Now it is waiting for input file

· Step4>Run NVISHEXKIT.exe as shown

· It will generate kit file format which is supported by our Trainer

Address Opcode Mnemonic Comment

2000 3E 0E MVI A,0E Initialize RST 5.5

2002 30 SIM Set Interrupt Mask

2003 FB EI Enable Interrupt

2004 CD 29 06 CALL RD KB Read Keyboard

2007 32 F6 27 STA 27F6 Store Current Data

Display The Scan Code On Data

200D C3 00 20 JMP 2000 Loop

Address Opcode Mnemonic Comment

2000 3E 0B MVI A,0B Initialize RST 7.5

2002 30 SIM Set Interrupt MASK

2003 FB EI Enable Interrupt

2004 C3 04 20 JMP 2004 Loop

Address Opcode Mnemonic Comment

2100 CD 55 04 Call ERR Initialize RST 7.5

This Displays Err On The

Now enter the jump address of interrupt service routine at 27BD.

Address Opcode Mnemonic Comment

Jump To Interrupt Service

27E6 Stack Pointer MSB