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Polysilicon Aluminum
Complementary CMOS
• Complementary CMOS logic gates
– nMOS pull-down network pMOS
pull-up
network
– pMOS pull-up network inputs
output
– a.k.a. static CMOS
nMOS
pull-down
network
Pull-down ON 0 X (crowbar)
Signal Strength
• nMOS pass strong 0
– But degraded or weak 1
• pMOS pass strong 1
– But degraded or weak 0
• Thus NMOS are best for pull-down network
• Thus PMOS are best for pull-up network
Conduction Complement
• Complementary CMOS gates always produce 0 or 1
• Ex: NAND gate
– Series nMOS: Y=0 when both inputs are 1
– Thus Y=1 when either input is 0
– Requires parallel pMOS
Y
A
• Rule of Conduction Complements
– Pull-up network is complement of pull-down B
– Parallel -> series, series -> parallel
CMOS Gate Design
• A 4-input CMOS NOR gate
A
B
C
D
Y
Example: O3AI
• Y = ( A + B + C) • D
Example: O3AI
Y = ( A + B + C) • D
A
B
C D
Y
D
A B C
Layout of Inverter : Detailed Steps
Vp
x x
Gnd
Inverter Cross-section
• Typically use p-type substrate for nMOS transistors
• Requires n-well for body of pMOS transistors
A
GND VDD
Y SiO2
n+ diffusion
p+ diffusion
n+ n+ p+ p+
polysilicon
n well
p substrate
metal1
VDD
Vin
Vout
GND
Stick Diagrams
Metal
poly
ndiff
pdiff
Can also draw
in shades of
gray/line style.
Stick Diagram - Example I
A
OUT
NOR Gate
Stick Diagrams
• Stick diagrams help plan layout quickly
– Need not be to scale
– Draw with color pencils or dry-erase markers
Sticks Diagram
V DD 3
In Out
• Dimensionless layout entities
• Only topology is important
• Final layout generated by
1 “compaction” program
GND
VDD
A B C D
GND
Design Rules
Design Rules
• Interface between designer and process engineer
• Guidelines for constructing process masks
• Unit dimension: Minimum line width
– scalable design rules: lambda parameter
– absolute dimensions (micron rules)
Wiring Tracks
• A wiring track is the space required for a wire
– 4 l width, 4 l spacing from neighbor = 8 l pitch
• Transistors also consume one wiring track
Well spacing
• Wells must surround transistors by 6 l
– Implies 12 l between opposite transistor flavors
– Leaves room for one wire track
Area Estimation
• Estimate area by counting wiring tracks
– Multiply by 8 to express in l
Example: O3AI
Y = ( A + B + C) • D
Y = ( A + B + C) • D
Example: O3AI
Sketch a stick diagram for O3AI and estimate area
Y = ( A + B + C) • D
Simplified Design Rules
• Conservative rules to get you started
S
Intra-Layer
a m e
Design Rules
P o Dt e in f t f i e a r l e n t P o t e n t i a l
9 2
0
W e l l o r P o l y s i l i c o n
6
1 0 2
3 3
A c t i v e M e t a l 1
C o n t a c t
o r V i a 2
3 H o l e 3
2 2 4
S e l e c t Metal2
3
Sequential Logic Cells
• Latch
• Flip-Flop
• Clocked Inverter
D Latch Design
• Multiplexer chooses D or old Q
CLK
CLK
D Q Q
1
Q D Q
0
CLK CLK
Old Q
CLK
D Latch
• When CLK = 1, latch is transparent
– Q follows D (a buffer with a Delay)
• When CLK = 0, the latch is opaque
– Q holds its last value independent of D
• a.k.a. transparent latch or level-sensitive latch
CLK CLK
D
Latch
D Q
Q
D Latch Operation
Q Q
D Q D Q
CLK = 1 CLK = 0
CLK
Q
D Flip-flop
• When CLK rises, D is copied to Q
• At all other times, Q holds its value
• a.k.a. positive edge-triggered flip-flop, master-slave flip-flop
CLK
CLK
D
Flop
D Q
Q
D Flip-flop Design
• Built from master and slave D latches
CLK CLK
CLK QM
D Q
CLK CLK CLK CLK
CLK
Latch
Latch
QM
D Q
CLK CLK
QM Q
D
CLK = 0
Q -> NOT(NOT(QM))
CLK = 1
CLK
Q
Race Condition
• Back-to-back flops can
malfunction from clock skew
– Second flip-flop fires Early
– Sees first flip-flop change
and captures its result
– Called hold-time failure or
race condition
Timing Constraints
R1 R2
In Combinational
D Q D Q
Logic
tc − q tlogic
tc − q, cd t
tsu, thold
tc − q tlogic
tc − q, cd t
tsu, thold
φ2 φ2 φ1 φ1
φ2 φ1
φ1
φ2
Clocked Inverter
• A series combination of an inverter and a transmission
gate
Datapath Logic Cells
• Adder
– Ripple, Carry Save, Carry Bypass, Carry Skip
– Carry Look ahead Adders ( Brent-Kung)
– Carry Select and Conditional Sum adder
Adders
• A. Conventional number system.
– Carry-propagate adders / Ripple carry Adders (CPA / RCA)
– Carry-skip adder
– Carry-lookahead adder
– Carry-select adder
– Conditional-sum adder
• B. Redundant number system : limited carry propagation
– Carry-save adder
Full-Adder
A B
Sum
Full Adder Implementations
The Binary Adder
A B
Sum
S = A⊕ B ⊕i
C
= A BCi + A BC i + AB Ci + A B Ci
C o = A B + B Ci + A Ci
Express Sum and Carry as a function of P, G, D
S0 S1 S2 S3
P0 G 1 P0 G1 P2 G2 P3 G3
BP=P oP1 P2 P3
Ci,0 Co ,0 Co,1 Co,2
FA FA FA FA
Multiplexer
C o,3
Ci,0 P0 Ci,1 P1
Ci, N-1 PN-1
S0 S1 ••• SN-1
C o, k = f ( A k, B k C,o, k – 1 = Gk + P k) Co, k –1
Look-Ahead: Topology
C o, k = Gk + Pk ( Gk – 1 + Pk – 1 Co, k –2 )
G2
G1
All the way:
G0
C o, k = Gk + Pk ( Gk – 1 + P k – 1 ( … + P1( G0 + P0 Ci, 0 ) ) )
Ci,0
Co,3
P0
P1
P2
P3
Carry Lookahead Trees
Co, 0 = G0 + P0Ci, 0
C o, 1 = G1 + P1 G0 + P1P0 Ci, 0
C o, 2 = G2 + P2G1 + P2 P1G0 + P2 P1P0C i, 0
= ( G2 + P2G1 + ( P2P)1 ( G0) + P0Ci, 0 = G 2:1 )+ P2:1 C o, 0
1 0 1 0 1 0 Multiplicand
x 1 0 1 1 Multiplier
1 0 1 0 1 0
1 0 1 0 1 0
0 0 0 0 0 0 Partial products
+ 1 0 1 0 1 0
1 1 1 0 0 1 1 1 0 Result
Canonical Signed Digit Vector
Note : B = Binary Number, D= CSD vector
Ci+1 is the Carry from the sum of Bi+1 + Bi + Ci ( start with C0=0)
Booth’s Algorithm
Booth’s Algorithm Rules
Booth’s Algorithm – An Example
Radix-4 Modified Booth’s Algorithm
Radix-4 Booth’s Algorithm Rules
Radix-4 Versus Radix-2 Booth’s Algorithm
Residue Number System: Continued
• Subtracter
• Barrel-Shifter
• Leading-one detector
• Priority Encoder
• Accumulator
• Decrementer
• All-zeros / ones detector
• Register File
• FIFO
Summary
• ASIC Cell Libraries
• CMOS Logic :Logic Levels, Design Rules
• Layout, Stick diagrams
• Sequential & Data Path Logic Cells
• Residue Number Systems
• I/O Cells
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