DLD CEL-120 Lab Manual

Digital Logic Design
CEL-120
Lab Manual
BSCS
Department of Computer Science

Bahria University, Islamabad
Contents
Introduction ................................................................................................................................................... 3
Lab 1: Introduction to trainer: Identifying discrete logic gates, IC’s, Pin configurations. ........................... 4
Lab 2: Implementing the basic integrated circuit ........................................................................................ 12
Lab 3: Designing from the Given Problem Statement and Implementation of the Given Functions. ........ 18
Lab 4: Circuit Complexity Reduction by Minimization of Boolean Expressions ...................................... 23
Lab 5: Designing from Logical Statement, Function Minimization and Implementation .......................... 27
Lab 6: Don’t Care Conditions ..................................................................................................................... 30
Lab 7: Half Adder, Full Adder and 7 Segment Display .............................................................................. 34
Lab 8: Decoder Implementation ................................................................................................................. 38
Lab 9: Multiplexer Implementation ............................................................................................................ 42
Lab 10: Latches........................................................................................................................................... 46
Lab 11: Flip Flops ....................................................................................................................................... 51
Lab 12: Counters ......................................................................................................................................... 55
Lab 13: Counters in Practical Scenarios ..................................................................................................... 59
Lab 14: Gate level Modeling using HDL,VHDL, Verilog ......................................................................... 62
2
PREPARED BY: ZAIN BIN KHALID
Introduction
Safety comes first in any laboratory.
If in doubt about any procedure, or if it seems unsafe to you, STOP. Ask

your lab instructor for help.
A. What to bring to each laboratory session:
FOR EXAMPLE:
1. Bring an 8" by 10" graph-ruled lab journal, to all lab sessions.

2. Bring a "scientific" calculator.
3. Bring this lab manual.
B. Prepare for each laboratory session:
Each laboratory consists of a series of related problems that can be solved using the same basic
concepts and principles. Sometimes all lab groups will work on the same problem, other times
groups will work on different problems and share results.
1. Before beginning a new lab, carefully read the Introduction, Objectives and Preparation
sections.
2. Each lab contains several different experimental problems. Before you come to a lab,
complete the assigned Prediction and Warm-up. The Warm-up helps you build a
prediction for the given problem, so it is usually helpful to complete the Warm-up before
making the prediction.
C. Attendance
Attendance is required at all labs without exception. If something disastrous keeps you from
your scheduled lab, contact your lab instructor immediately. The instructor will arrange for
you to attend another lab section that same week. There are no make-up labs in this course.
E. Grades
<Grading policy> (course content file)
3
Lab 1: Introduction to trainer: Identifying discrete logic gates, IC’s,
Pin configurations.
OBJECTIVE:
To demonstrate the operation and characteristics of typical discrete components like logic
switches, LED indicators, especially the various operations of the Digital Trainer Kit.
Detailed descriptions of integrated logic circuits (IC) , dual, quadruple-in-line IC’s and their Top
view with pin configurations etc.
Lab journal writing procedures, its format and the way to describe the logic circuits.
Grouping of students for lab works.
1. Introduction to gates and integrated circuits:

 Individual gates constructed from transistors and discrete passive components.
 Integrated gate circuits (also called chips) consisting of several transistors, passive
components fabricated in a single package.
 All chips must be connected to a power source (VCC) and ground (GND). All the gates in
the chip share these connections.
2. Packaging of integrated circuits (Top View)

Dual in line packages
4
5
3. Introduction to some standard gates and their symbols and truth tables:
6
Task # 1.1:
Use the ICs of individual gates to construct the circuit and verify the truth table of all gates.
(AND, OR, NAND, NOR, XOR)
Circuit:
Truth Table:
Conclusion:
7
Task # 1.2:
Use NAND to build NOT gate.
Circuit:
Truth Table:
Conclusion:
8
Task # 1.3:
 Implement the following circuit on bread board
 Construct the truth table
 Identify the type of gate constructed
Circuit:
Truth Table:
Conclusion:
9
Task # 1.4:
Use an inverter designed from a NOR gate to invert the output of the circuit
below
Circuit:
Truth Table:
Conclusion:
10
Answer the following questions
1. Which two connections are necessary for an IC to work?

2. What is the nominal value of voltage (Vcc) supplied to the IC for it to work?
3. To design a NOT gate from a NAND gate, both the inputs of a NAND gate are
fed with the same input signal. Does this concept hold for constructing a NOT
gate using a NOR gate as well?
4. Which two gates are known as universal gates and why?
11
Lab 2: Implementing the basic integrated circuit
OBJECTIVE:
To learn to build basic integrated circuits on bred board. Construct different logic gates using
universal gates. The use of simulation software (proteus) to conduct simulations.
12
Task # 2.1:
Implement the following circuit on bred board. Note the output and identify the new gate
constructed.
Circuit:
Truth Table:
Conclusion:
13
Task # 2.2:
 Invert the output of the circuit built in task-1?
 Show circuits for all possible ways
Circuit:
Truth Table:
Conclusion:
14
Task # 2.3:
Implement the following circuit on bred board. Note the output and identify the new gate
constructed.
Circuit:
Truth Table:
Conclusion:
15
Task # 2.4:
 Invert the output of the circuit built in task-3?
 Show circuits for all possible ways
Circuit:
Truth Table:
Conclusion:
16
1. If the constructed circuit is not giving the desired output, what steps would you
take to troubleshoot the problems? What can be the possible issues?
2. What basic information can be obtained from the datasheet?
17
Lab 3: Designing from the Given Problem Statement and
Implementation of the Given Functions.
OBJECTIVE:
To learn to design circuits from the given problem statements and implementation of the given
functions on bred board along with their simulations
Task # 3.1:
Obtain the truth table of the following function and its schematic. Simulate the circuit in
proteus and implement it on bred board.
F= X + Y’Z
Circuit:
Truth Table:
Conclusion
18
Task # 3.2:
Obtain the truth table of the following function and its schematic. Simulate the circuit in
proteus and implement it on bred board.
F= X’Y’Z + X’YZ + XY’
Circuit:
Truth Table:
Conclusion:
19
Task # 3.3:
Fire alarm system has been installed in a building. The system has two ways of detecting
the emergency situation (fire in the building).
 Smoke detection
 Sudden rise of temperature
The system sounds the alarm if it detects a sudden rise in temperature or smoke in the
building. Obtain the truth table and function of the above scenario. Simulate the circuit on
proteus. Implement it on bred board.
Circuit:
Truth Table:
Conclusion:
20
Task # 3.4:
A building security system works such that it uses the following ways of intrusion detection.
 Security cameras
 Motion sensors
 Security Guard
The system works such that when an intruder is detected by either security cameras or motion
sensors or the guard, the system not only sounds an alarm but also sends an sms alert to the
security supervisor of the building. Obtain the truth table and function of the above scenario.
Simulate the circuit on proteus. Implement it on bred board.
Circuit:
Truth Table:
Conclusion:
21
1. From the given function, how do you identify which gates are to be used and the
number of inputs each gate has?
2. Identify the following in the given function F= AB’D + ACD’ + ABC
i. Total number of gates
ii. Types of gates to be used
iii. Number of inputs to each gate
22
Lab 4: Circuit Complexity Reduction by Minimization of Boolean
Expressions
OBJECTIVE:
To learn the advantages of simplifying Boolean expressions and thus helping in reduction of
circuit complexity.
Task # 4.1:
 Simplify the following function
 F=A’D + BD + B’C + AB’D
 Obtain the truth table
 Simulate the circuit in Proteus and build it on bread board.
 Mention the total number of gates used to implement the original
function and the simplified one.
Circuit:
Truth Table:
Conclusion:
23
Task # 4.2:
 Simplify the function F1. F1= (A,B,C,D)= ∑ (0,1,2,5,8,9,10)
 Obtain the simplified SOP expression and the truth table.
 Simulate the circuit and build it on bread board.
Circuit:
Truth Table:
Conclusion:
24
Task # 4.3:
 Derive the function from the given circuit, simplify it and implement the simplified
circuit.
 Mention the total number of gates used to implement the original function and the
simplified one.
Simplified Circuit:
Truth Table:
Conclusion:
25
1. How does minimization help in reducing the circuit’s complexity?

2. For the function F= A’B’D+A’BD+AC’D+ACD+AB’D’
a) Simulate the circuit without simplification
b) Simulate the circuit with simplification
26
Lab 5: Designing from Logical Statement, Function Minimization
and Implementation
`
OBJECTIVE:
To learn the advantages of simplifying Boolean expressions and thus helping in reduction of
circuit complexity along with the aim to extract the function from the given problem statement.
Task # 5.1:
 A security system for a building has three ways of detecting an intruder.
 Security camera (SC) which sends a 1 when an intruder is detected
 Motion sensor (MS) which sends a 0 when an intruder is detected
 Noise level detector (NLD) which sends a 1 when the noise level rises
beyond a certain threshold
 The system works in such a way that the alarm sounds when
 SC doesn’t detect an intruder but the MS and the NLD do
 Neither SC nor the MS detects but the NLD does
 SC and the MS detect but NLD doesn’t
 SC detects only
 SC and NLD detect but MS doesn’t
Circuit:
Truth Table:
Conclusion:
27
Task # 5.2:
F= D’(B’C’+B’C) + B(A’D+AD)
 Simplify the function using k-map. Simulate and implement on bred board
 Combine the 0’s in the k-map to obtain the complement of the function.
 Simulate and implement F’
Circuit:
Truth Table:
Conclusion:
28
1. F= ∑(1,3,4,5,6,7,8,10,12,13,14,15)
 Simplify the function using k-map
 Combine the 1’s to obtain simplified F
 Combine the 0’s to obtain simplified F’
 Simulate the circuit for both F and F’
29
Lab 6: Don’t Care Conditions
OBJECTIVE:
To learn the importance and the use of don’t care conditions.
Task # 6.1:
Design a 4 bit parity checker which works such that when the parity is even the
output is 1 and when the parity is odd the output is 0.
Circuit:
Truth Table:
Conclusion:
30
Task # 6.2:
Company decides to monitor its employees packet data usage and decides to take
action against the employees who are using more than 2GB per week. The company
consists of 5 employees and employee’s data usage per week is given below
E1= 1GB
E2= 5GB
E3= 12GB
E4= 1.5GB
E5=0.5GB
Design a system which works such that the output is 1 if the data usage is more than
2GB and its 0 otherwise.
Circuit:
Truth Table:
Conclusion:
31
Task#6.3
Design a circuit which is capable of telling which month has 31 days. The system
works such that it gives the output as 1 if the month has 31 days. The output is 0
otherwise.
Circuit:
Truth Table:
Conclusion:
32
2. F= ∑(2,5,7,9,11,12), d(0,4,6,8,10)
 Simplify the function using k-map
 Simulate the circuit in proteus
33
Lab 7: Half Adder, Full Adder and 7 Segment Display
OBJECTIVE:
To implement Half and Full Adder circuits and the use of 7 segment display.
Task # 7.1:
Implement the half adder circuit
Circuit:
Truth Table:
Conclusion
34
Task # 7.2:
Implement the full adder circuit.
Circuit:
Truth Table:
Conclusion:
35
Task#7.3
Design the circuit for 7-segment display which displays numbers from 0 to 9.
Circuit:
Truth Table:
Conclusion:
36
Design the circuit for 7-segment display which displays numbers from 0 to 9 and
letters from A to F.
37
Lab 8: Decoder Implementation
OBJECTIVE:
To use the decoder for implementation of Boolean functions.

Task # 8.1:
Implement the function F1 using decoder F1= (A,B,C,)= ∑ (0, 1, 2, 4, 5, 7, )
Circuit:
Truth Table:
Conclusion:
38
Task # 8.2:
Design a circuit which takes 3 bits as input. The output is 1 if two or more inputs are
1.
Circuit:
Truth Table:
Conclusion:
39
Task # 8.3:
Design a circuit which takes 3 bits as input. The output is 1 if the binary sum is two.
Circuit:
Truth Table:
Conclusion:
40
 Implement A’C + ABC + BC’D + AB’C using decoder. Simulate the circuit in proteus
 Implement A’DC + A’D’ + B’CD + CD’ using decoder. Simulate the circuit in proteus.
41
Lab 9: Multiplexer Implementation
OBJECTIVE:
To use the multiplexer for implementation of Boolean functions.
Task # 9.1:
Implement F1 using multiplexer F1= (A,B,C,D)= ∑ (0, 1, 2, 4, 5, 7, 11, 15)
Circuit:
Truth Table:
Conclusion:
42
Task # 9.2:
Implement the F2 using MUX F2= (W, X, Y, Z)= X’Z + W’XY’ + W( X’Y + XY’)
Circuit:
Truth Table:
Conclusion:
43
Task # 9.3:
 A toy police motorbike for kids has four buttons A,B,C,D. The bike starts moving if
either of the two conditions is satisfied
 A single button is pressed
 two buttons are pressed simultaneously.
 If more than two buttons are pressed simultaneously, it begins to sound the police
siren as well.
 Identify the inputs and outputs
 Truth table
 Implement using MUX
Circuit:
Truth Table:
Conclusion:
44
 A toy police motorbike for kids has four buttons A,B,C,D. The bike starts moving if
either of the two conditions is satisfied
 A single button is pressed
 two buttons are pressed simultaneously.
 If three buttons are pressed simultaneously, it begins to sound the police siren as
well.
 If all four buttons are pressed, its light turns on along with the police siren
 Identify the inputs and outputs
 Truth table
 Implement using MUX
45
Lab 10: Latches
OBJECTIVE:
To understand the concept of memory storage using latches.
Task # 10.1:
SR Latch Using NOR Gates
Circuit:
Truth Table:
Conclusion:
46
Task # 10.2:
S’R’ Latch Using NAND Gates
Circuit:
Truth Table:
Conclusion:
47
Task # 10.3:
SR Latch With Control Input
Circuit:
Truth Table:
Conclusion:
48
Task # 10.4:
D Latch With Control Input
Circuit:
Truth Table:
Conclusion:
49
1. How does a latch store a binary value?
2. How many latches are required to store 4 bits?
3. What does illegal state mean? Why is it called illegal?
4. What is the advantage of having a control input in a latch?
50
Lab 11: Flip Flops
OBJECTIVE:
To understand the difference between latches and flip flops and learn to use flip flops in practical
scenarios.
Task # 11.1:
Connect and verify the output of D flip flop according to its function table
Circuit:
Function Table:
Conclusion:
51
Task # 11.2:
Connect and verify the output of J-K flip flop according to its function table
Circuit:
Function Table:
Conclusion:
52
Task # 11.3:
Build a T flip flop using the following and construct its function table
 D flip flop
 J-K flip flop
Circuit Using D Flip Flop:
Circuit Using J-K Flip Flop
Function Table:
Conclusion:
53
1. Explain the difference between a latch and a flip flop.
2. What is the difference between edge triggering and level triggering?
54
Lab 12: Counters
OBJECTIVE:
To understand the working of counters and design counters with external bits.
Task # 12.1:
Design and implement 2 bit forward counter using flip flop of your own choice
Circuit:
Function Table:
Conclusion:
55
Task # 12.2:
Design and implement 3 bit forward counter using flip flop of your own choice
Circuit:
Function Table:
Conclusion:
56
Task # 12.3:
Design and implement 3 bit even counter using flip flop of your own choice
Circuit Using D Flip Flop:
Function Table:
Conclusion:
57
1. Design a 3 bit counter which takes a fourth bit ‘x’ as external input. When
x=1 the counter works as forward even, and when x=0, the counter works as
reverse odd. All the invalid states should be returned to a higher valid state.
For instance for a forward even counter, if the present state is 3 which is
invalid, it should be returned to a higher valid state which in this case is 4,
similarly 5 would be returned to 6 and so on.
2. Design the counter used in your project.
58
Lab 13: Counters in Practical Scenarios
OBJECTIVE:
To understand the use of counter in practical scenarios.
Task # 13.1:
A revolving statue is to be designed for décor. It revolves and fires with a water gun
in six different directions (forward, backward, left, right, up and down). Implement
the above scenario using counter.
Circuit:
Function Table:
Conclusion:
59
Task # 13.2:
If in the previous task the robot is said to skip the downward direction, modify the
implementation accordingly.
Circuit:
Function Table:
Conclusion:
60
Task # 13.3:
If an input is given at user end and the robot skips the direction which is entered by
user, modify the implementation accordingly.
Circuit:
Function Table:
Conclusion:
61
Lab 14: Gate level Modeling using HDL,VHDL, Verilog
OBJECTIVE:
Gate level Modeling using HDL,VHDL, Verilog
Refer to “Digital Techniques Student Workbook” (page- )

Task # 14.1:
Half adder
module half_adder_v(x, y, s, c);
input x, y;
output s, c;
assign s = x ^ y;
assign c = x & y;
endmodule
62
Task # 14.2:
Full adder
module full_adder_v(x, y, z, s, c);
input x, y, z;
output s, c;
wire hs, hc, tc;
half_adder_v HA1(x, y, hs, hc),
HA2(hs, z, s, tc);
assign c = tc | hc;
endmodule
63
Task # 14.3:
4-bit full adder
module adder_4_v(B, A, C0, S, C4);
input[3:0] B, A;
input C0;
output[3:0] S;
output C4;
wire[3:1] C;
full_adder_v Bit0(B[0], A[0], C0, S[0], C[1]),
Bit1(B[1], A[1], C[1], S[1], C[2]),
Bit2(B[2], A[2], C[2], S[2], C[3]),
Bit3(B[3], A[3], C[3], S[3], C4);
Endmodule
64
Task # 14.4:
4 to 1 line multiplexer
// 4-to-1 Line Multiplexer: Dataflow Verilog Description
module multiplexer_4_to_1_df_v(S, D, Y);
input [1:0] S;
input [3:0] D;
output Y;
assign Y = (~ S[1] & ~ S[0] & D[0])| (~ S[1] & S[0] & D[1])
| (S[1] & ~ S[0] & D[2]) | (S[1] & S[0] & D[3]);
endmodule
65

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Digital Logic Design

Department of Computer Science

Safety comes first in any laboratory.

If in doubt about any procedure, or if it seems unsafe to you, STOP. Ask

1. Bring an 8" by 10" graph-ruled lab journal, to all lab sessions.

B. Prepare for each laboratory session:

Grouping of students for lab works.

1. Introduction to gates and integrated circuits:

2. Packaging of integrated circuits (Top View)

1. Which two connections are necessary for an IC to work?

1. How does minimization help in reducing the circuit’s complexity?

To use the decoder for implementation of Boolean functions.

Circuit Using D Flip Flop:

Circuit Using J-K Flip Flop

Circuit Using D Flip Flop:

Gate level Modeling using HDL,VHDL, Verilog

Refer to “Digital Techniques Student Workbook” (page- )

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