ISSCC 2013 / SESSION 2 / ULTRA-HIGH-SPEED TRANSCEIVERS AND EQUALIZERS / 2.
2.1 A 32Gb/s Wireline Receiver with a Low-Frequency
Equalizer, CTLE and 2-Tap DFE in 28nm CMOS
Samir Parikh1, Tony Kao1, Yasuo Hidaka1, Jian Jiang1, Asako Toda1,
Scott Mcleod1, William Walker1, Yochi Koyanagi2, Toshiyuki Shibuya2,
Jun Yamada3
1
Fujitsu Laboratories of America, Sunnyvale, CA,
2
Fujitsu Laboratories, Kawasaki, Japan, 3Fujitsu, Kawasaki, Japan
Standards such as OIF CEI-25G, CEI-28G and 32G-FC require transceivers oper-
ating at high data rates over imperfect channels. Equalizers are used to cancel
the inter-symbol interference (ISI) caused by frequency-dependent channel loss-
es such as skin effect and dielectric loss. The primary objective of an equalizer
is to compensate for high-frequency loss, which often exceeds 30dB at fs/2.
However, due to the skin effect in a PCB stripline, which starts at 10MHz or
lower, we also need to compensate for a small amount of loss at low frequency
(e.g., 500MHz). Figure 2.1.1 shows simulated responses of a backplane channel
(42.6dB loss at fs/2 for 32Gb/s) with conventional high-frequency equalizers
only (4-tap feed-forward equalizer (FFE), 1st-order continuous-time linear equal-
izer (CTLE) with a dominant pole at fs/4, and 1-tap DFE) and with additional low-
frequency equalization. Conventional equalizers cannot compensate for the small
amount of low-frequency loss because the slope of the low-frequency loss is too
gentle (<3dB/dec). The FFE and CTLE do not have a pole in the low frequency
region and hence have only a steep slope of 20dB/dec above their zero. The DFE
cancels only short-term ISI. Effects of such low-frequency loss have often been
overlooked or neglected, because 1) the loss is small (2 to 3dB), 2) when plot-
ted using the linear frequency axis which is commonly used to show frequency
dependence of skin effect and dielectric loss, the low-frequency loss is degener-
ated at DC and hardly visible (Fig. 2.1.1a), and 3) the long ISI tail of the channel
pulse response seems well cancelled at first glance by conventional equalizers
only (Fig. 2.1.1b). However, the uncompensated low-frequency loss causes non-
negligible long-term residual ISI, because the integral of the residual ISI magni-
tude keeps going up for several hundred UI. As shown by the eye diagrams in
the inset of Fig.  2.1.1(b), the residual long-term ISI results in 0.42UI data-
dependent Jitter (DDJ) that is difficult to reduce further by enhancing
FFE/CTLE/DFE, but can be reduced to 0.21UI by adding a low-frequency equaliz-
er (LFEQ). Savoj et al. also recently reported long-tail cancellation [2].
In this paper, we present a 32Gb/s receiver (RX) capable of loss compensation
from low frequency to high frequency. Due to the addition of a LFEQ, the RX
compensates for low frequency losses due to skin effect while intermediate and
high frequency losses are compensated by a CTLE up to fs/4 and by a 2-tap DFE
at fs/2. Recent work [1-2] has shown equalizers using peaking inductors/T-coils
for bandwidth enhancement. However, the equalizers in this RX are implement-
ed without passive or active inductors. The RX achieves BER<10-12 with a 32Gb/s
PRBS31 pattern over a channel with 40dB loss at 16GHz.
The RX, shown in Fig.  2.1.2, is implemented using a half-rate architecture. It
consists of a T-coil-based input-termination network, CTLE, LFEQ, 2-tap specu-
lative DFE, clock recovery, and equalizer adaptation circuits. T-coils are used at
the receiver input to compensate for the capacitance of the ESD network in order
to meet the return-loss specifications. Boundary samplers capture the phase
error at the CTLE output and since the CTLE only cancels residual ISI up to fs/4,
clock recovery is performed using pattern filtering [3] to use the phase error only
for frequencies below fs/4. The recovered clock is generated from a half-rate ref-
erence clock with a CML-to-CMOS level converter, a duty-cycle corrector (DCC),
a four-phase generator, and independent phase interpolators for the data path
and boundary path. The speculative error sampler provides error information to
the equalizer adaptation block, which also uses pattern filtering [4]. In the equal-
izer adaptation block, pattern filtering is used to implement sign-based zero-
forcing (S-ZF) for adaptation of the LFEQ and CTLE circuits, to implement sign-
sign least mean square (SS-LMS) for DFE adaptation, and to correctly select the
speculative error samples. Since detection of long-term ISI (e.g., 10 to 1000UI)
is necessary for LFEQ adaptation, S-ZF is extended by dealing with the long-term
ISI in an aggregate manner.
28 • 2013 IEEE International Solid-State Circuits Conference
Figure 2.1.3 shows the implementation of the data path with 2-tap speculative
DFE, boundary samplers and error samplers. Error samplers with a speculative
configuration are used to reduce power and area. They determine the error infor-
mation by applying the various DFE and reference levels combinatorially. A lin-
ear transconductor circuit (LTC), used in front of the error sampler, can be con-
figured to inject 3 different currents in the signal path, each with positive/nega-
tive polarity. Thus, the LTC can provide all 8 combinations needed for specula-
tive error sampling. The equalizer adaption block correlates the speculative error
samples with the data samples to select the correct error samples. One of the
current inputs in each LTC is used to add/subtract an offset compensation cur-
rent to calibrate for the offset of the sampler connected to it. In the data path, the
two other LTC inputs are used to perform DFE speculation by applying four dif-
ferent level shifts for each of the four speculative paths. A digital feedback cir-
cuit is implemented in the data path to correctly select the two data samples
from the eight speculative data samples.
The CTLE and LFEQ circuits are shown in Fig. 2.1.4. The CTLE implements a zero
in the signal path using source degeneration. The location of the zero is tuned by
digital control of the source-degeneration resistor (Rs1), while the location of the
poles is fixed by design with the dominant pole occurring at fs/4. In contrast, the
LFEQ implements a zero at low frequency (500MHz) through a feedback topolo-
gy. This topology implements variable gain in the feedback path to control the
first pole, fp1, from 500MHz to 1GHz. Since the CTLE provides large boost (0 to
15dB) at high frequencies to compensate for dielectric loss and skin effect, while
the LFEQ implements a small amount of equalization (0 to 4dB) to compensate
for the gentle slope of the low frequency loss due to skin effect, their design
requirements are quite different. The CTLE poles are restricted to fs/4 or higher
and require the ability to tune the zero in relatively high frequency (1 to 8GHz)
with a wide range. As a result, the span between the first pole and zero depends
only on the location of the zero. On the other hand, the only restriction in a LFEQ
is that its first pole and zero must be close to each other. In other words, the
placement of the pole-zero pair gives us two degrees of freedom; the first being
the center frequency, and the second being the span of the pair. In our imple-
mentation, we implement a fixed zero at 500MHz and tune the first pole (fp1) in
a small frequency range above the zero.
A die micrograph of the 28nm test chip is shown in Fig. 2.1.7. The total area of
the RX is 0.33mm2 and it consumes 240mW of power from a 0.9V supply when
operating at 32Gb/s with the CDR and related clock circuits powered down. The
differential input return loss is measured to be better than 10dB from 0 to
20GHz, and is shown in Fig. 2.1.5. The receiver achieves a BER <10-12 over a 31-
inch PCB trace with 37dB loss at 16GHz (40dB total loss with receiver package)
using a TX with 3-tap FFE and 1Vpp differential swing. Figure 2.1.6(a) shows the
trace characteristics and Fig. 2.1.6(b) shows the measured bathtub curve. The
BER floor is improved from 10-7 to <10-12 with the LFEQ.
References:
[1] J. Bulzacchelli et al., “A 28Gb/s 4-Tap FFE/15-Tap DFE Serial Link Transceiver
in 32nm SOI CMOS Technology,” in ISSCC Dig. Tech. Papers, pp. 324-325, Feb.
2012.
[2] J. Savoj, et al., “A Wide Common-Mode Fully-Adaptive Multi-Standard
12.5Gb/s Backplane Transceiver in 28nm CMOS,” in VLSI Circuits Dig. Tech.
Papers, pp.104-105, June 2012.
[3] Y. Hidaka, et al., “A 4-Channel 10.3Gb/s Transceiver with Adaptive Phase
Equalizer for 4-to-41dB Loss PCB Channel,” in ISSCC Dig. Tech. Papers, pp.
346-347, Feb 2011.
[4] Y. Hidaka, et al., “A 4-Channel 1.25-10.3Gb/s Backplane Transceiver Macro
With 35dB Equalizer and Sign-Based Zero-Forcing Adaptive Control,” IEEE J.
Solid-State Circuits, vol. 44, no. 12, pp.3547-3559, Dec. 2009.
978-1-4673-4516-3/13/$31.00 ©2013 IEEE
 ISSCC 2013 / February 18, 2013 / 1:30 PM

Figure 2.1.1: Frequency-domain and time-domain responses of a backplane

channel with and without low frequency equalization. Figure 2.1.2: Receiver block diagram.

Figure 2.1.3: Data path with two-tap speculative DFE, boundary and error
path. Figure 2.1.4: CTLE and low-frequency equalizer.

Figure 2.1.6: Measurement results: channel characteristic and bathtub

Figure 2.1.5: Receiver′s differential input return loss measurement. curves.

DIGEST OF TECHNICAL PAPERS • 29

 ISSCC 2013 PAPER CONTINUATIONS

Figure 2.1.7: Die micrograph.

• 2013 IEEE International Solid-State Circuits Conference 978-1-4673-4516-3/13/$31.00 ©2013 IEEE