Finite State Machine – Verilog HDL

by
C. Prayline Rajabai
Assistant Professor
SENSE, VIT University, Vellore
FSM Design Using Verilog
 Using Verilog HDL design a sequence detector with one input X
and one output Z. The detector should recognize the input
sequence “101”. The detector should keep checking for the
appropriate sequence and should not reset to the initial state after
it has recognized the sequence. The detector initializes to a reset
state when input, RESET is activated.
State Diagram and State Transition Table
Mealy Machine in Verilog HDL
module mealy_fsm(reset,clk,in_seq,out_seq);
input reset;
input clk;
input in_seq;
output out_seq;

//----------- Parameters defining State machine States-----

parameter SIZE = 2;
parameter S0 = 2'b00, S1 = 2'b01, S2 = 2'b10;

reg out_seq;
//------------ Internal Variables ----------------------------------
reg [SIZE-1:0] state; // Memory part of the FSM
reg [SIZE-1:0] next_state;
 Mealy Machine in Verilog HDL
always @ (state or in_seq) S2 : if (in_seq== 1'b0) begin
begin : FSM_COMBO next_state = S0; out_seq = 1'b0;
next_state = 2'b00; end else begin
case(state) next_state = S1; out_seq = 1'b1;
S0 : if (in_seq == 1'b0) begin end
next_state = S0; default : begin
out_seq = 1'b0; next_state = S0; out_seq = 1'b0;
end else begin end
next_state = S1; endcase
out_seq = 1'b0; end
end
S1 : if (in_seq == 1'b0) begin // Register combinational “next_state” variable
next_state = S2; always @ (posedge clk)
out_seq = 1'b0; begin : FSM_SEQ
end else begin if (reset == 1'b1) state <= S0;
next_state = S1; else state <= next_state;
out_seq = 1'b0; end
end endmodule
Moore Machine in Verilog HDL
Moore Machine in Verilog HDL