Lecture 5 - Sequential Circuits PDF

SEQUENTIAL CIRCUITS
Prepared by:
Engr. Reymond D. Serafica, ECE
ELE 411: Logic Circuits and Switching Theory
Introduction to Sequential
Circuits

Motivation
• Almost all gadgets that we use today have
memories.
• So far, what we have discussed are combinational
circuits, whose outputs depend only on the present
inputs, therefore, they have no memory.
Combinational circuits are static systems.
• This lecture will be about sequential circuits.
• Sequential circuits are circuits whose output depends
on the present inputs and the past outputs.
• They acts as storage elements and have memory, hence
they are dynamic systems.

Sequential Circuits
• A sequential circuit consists of a combinational
circuit to which storage elements are connected to
form a feedback path.

Sequential Circuits
• Consider the inverter with feedback below.

Sequential Circuits
• The memory elements are the devices capable of
storing binary information.
• The memory elements may be a latch or a flip-flop.
• The information stored in the memory elements at
any given time defines the state of the sequential
circuit at that time.
• The current output and the next state of the system
depend on the current inputs and the present state.

Sequential Circuits
• In a synchronous sequential circuit, a reference
signal causes the system to change state at a specific
instant of time. This reference signal is called the
clock.
• The flip-flop is a memory device that has a clock input.
• In an asynchronous sequential circuit, the change
of state is not dictated by the clock.
• The latch is a memory element that has no clock input.

Sequential Circuits
• Below is the block diagram for a synchronous
sequential circuit.

Latches
• Recall that latches are memory elements that are not
controlled by a clock. They operate using signal
levels.
• RS latch  may use NAND or NOR
• JK latch
• D latch
• T latch

SR Latch using NOR Gates
• Logic diagram and schematic symbol
• Draw the characteristic table, state diagram, and

characteristic equation.

Problem 1:
• Draw the timing diagram for the SR NOR latch
given the timing diagram for its inputs.

SR Latch using NAND Gates

Problem 2:
• Draw the timing diagram for the SR NAND latch
given the timing diagram for its inputs.

RS Latch/SR Latch with EN

JK Latch

JK Latch

Problem 3:
• Draw the output timing diagram.

D Latch

D Latch

D Latch

T Latch

T Latch

Summary of Latches
• SR NAND Latch
• 𝑆𝑅 = 00, unchanged state
• 𝑆𝑅 = 01, reset state
• 𝑆𝑅 = 10, set state
• 𝑆𝑅 = 11, indeterminate, forbidden state
• SR NOR Latch
• 𝑆𝑅 = 00, indeterminate, forbidden state
• 𝑆𝑅 = 01, set state
• 𝑆𝑅 = 10, reset state
• 𝑆𝑅 = 11, unchanged state

Summary of Latches
• JK Latch
• 𝐽𝐾 = 00, unchanged state
• 𝐽𝐾 = 01, reset state
• 𝐽𝐾 = 10, set state
• 𝐽𝐾 = 11, toggle state
• D Latch  The next state of 𝑄 will be whatever 𝐷 is.
• T latch
• 𝑇 = 0, unchanged state
• 𝑇 = 1, toggle state

Problem 4:
• Draw the circuit of a T latch implemented using a
JK latch.

Flip-flops
• If latches are memory elements that have no clock
input, flip-flops are memory devices whose states
can be controlled by clock input.
• RS flip-flop
• JK flip-flop
• D flip-flop
• T flip-flop
• They have the same operation as their latch
counterparts. The only difference is that the states
are updated with reference to the clock.

Two Types of Clocking
• Level clocking  output/state of the flip-flop
responds during the high or low level of the clock
signal
• Positive level clocking
• Negative level clocking

Two Types of Triggering
• Edge triggering  state of the flip-flop changes if
there is a transition in the clock
• Positive edge triggering
• Negative edge triggering

Schematic Symbols
• JK flip-flop, positive edge triggered

Schematic Symbols
• JK flip-flop, negative edge triggered

Schematic Symbols
• JK flip-flop, positive level clocking

Schematic Symbols
• JK flip-flop, negative level clocking

Problem 5: Positive Level Clock
• Given the timing diagram below. Find 𝑄.

Problem 5: Negative Level Clock

Problem 5: Positive Edge Trigger

Problem 5: Negative Edge Trigger

Problem 6:
• The waveform shown below drive a positive edge
triggered RS flip-flop. If 𝑄 is low before time 𝐴:
• At what point does 𝑄 becomes a ‘1?’
• When does 𝑄 reset to?

Problem 7:*
• Given the circuit in the next slide. Construct the
timing diagram and the state diagram. What circuit
is this?

Problem 7:*

Preset and Clear
• Preset and clear are two external inputs that
initiates the state of the flip-flop.
• The preset input sets the state of the flip-flop to ‘1.’
• The clear input resets the state of the flip-flop to ‘0.’

Preset and Clear
• Below is the circuit for a D flip-flop with preset and
clear.

Schematic of FF with PR and CLR
• Active high JK flip-flop with preset and clear

Schematic of FF with PR and CLR
• Active low JK flip-flop with preset and clear

Important Parameters in FFs
• Propagation delay time  the amount a flip-flop
takes for the output of the gate or flip-flop to change
states.
• Setup time  minimum length of time the data bit
must be present before the clock edge hits
• Hold time  minimum length of time the data bit
must be present after the clock edge has struck

Example:
• The clock of the figure below has a frequency of 1
MHz and the flip-flop has a propagation delay time
of 25 ns.
• What is the period of the clock?
• What is the frequency and period of the output 𝑄?
• How long after the negative clock edge does the output
𝑄 change?

Master-Slave Flip-flops
• A master-slave flip-flop is a flip-flop consisting of
master and slave elements clocked con
complementary transitions of the clock signal.
• Data is only transferred from the master, then the
master passes the data to the slave.

Master-Slave Flip-flops*
• Master-slave flip-flops are often used in order to
overcome race-around conditions.
• Race-around conditions occur in JK flip-flops when 𝐽 =
𝐾 = 1 and the clock pulse is greater than the
propagation delay.
• Master-slave flip-flops are also used in large
circuits.
• Master-slave flip-flops are also used in order to
overcome 𝑆 = 𝑅 = 1 state of SR flip-flops.

• JK flip-flop implemented using two SR latches.
• See how the master-slave configuration overcame
the forbidden state 𝑆 = 𝑅 = 1

• The circuit below is a master-slave flip-flop where
the JK flip-flop is the master and the SR flip-flop is
the slave.

• The figure shows the schematic symbol for the
circuit in the previous slide.

Problem 8:
• Complete the timing diagram of the master-slave
circuit shown in the previous slide.

Practice Problem 1:
• A latch with output 𝑄 and 𝑃 = 𝑄′ can be constructed
from an OR gate, an AND gate, and an inverter
connected as follows.
• Construct the transition table, characteristic

equation and state diagram for the latch. What
values of 𝑅 and 𝐻 make the forbidden state?

Practice Problem 1:
• A latch with output 𝑄 and 𝑃 = 𝑄′ can be constructed
from an OR gate, an AND gate, and an inverter
connected as follows.
• Complete the timing diagram in the next slide.

Practice Problem 1:

Practice Problem 2:
• A reset-dominant flip-flop behaves like an SR flip-
flop except that 𝑆 = 𝑅 = 1 is allowed, and the flip-
flop is reset when 𝑆 = 𝑅 = 1 . Derive the
characteristic equation for a reset dominant flip-
flop.

Practice Problem 3:
• Complete the following timing diagram for a JK
flip-flop with a falling edge trigger and clear and
preset inputs.

Practice Problem 4:
• Show that the circuit below is an SR flip-flop. What
is the dominant state of the flip-flop?

Analysis of Synchronous
Sequential Circuits

State Equation
• The behavior of a clocked sequential circuit can be
described algebraically by means of state equations.
• A state equation or transition equation specifies
the next state as a function of the present state and
inputs.

State Table
• The time sequence of inputs, outputs, and flip-flop
states can be enumerated in a state table.
• It is also called as the transition table.
• It consists of present state, input, next state, and
output (and sometimes flip-flop inputs).
• A sequential circuit with 𝑚 flip-flops and 𝑛 inputs
have 2𝑚+𝑛 rows in the state table.

State Diagram
• The information in the state table can be represented
graphically using the state diagram.
• In a state diagram, the state is represented by a
circle, and the transitions between states are
indicated by arrows connecting the circles.
• The binary numbers inside the circle are the states of
the flip-flop.
• The arrows are labeled with two binary numbers
separated by a slash.

Excitation and Output Equations
• The input to each flip-flop can be expressed as a
Boolean expression known as the flip-flop input
equations or the excitation equation.
• The output of a combinational logic circuit part of a
sequential circuit can also be summarized in a
Boolean expression known as the output equation.

Analysis of Sequential Circuits
• A series of slides showing circuit diagrams will be
shown after this.
• Find their state equations, state tables, state
diagrams, excitation equations, and output
equations if applicable.

Problem 1:

Problem 2:

Problem 3:

Practice Problem 1:

Practice Problem 1:
• The sequential circuit has one flip-flop 𝑄, two inputs
𝑥 and 𝑦, and one output 𝑆 as shown in the previous
slide. Derive the state table and state diagram of the
sequential circuit.

Mealy and Moore
Machines

Mealy and Moore Machines
• There are two models of sequential circuits—the
Mealy and Moore machines.
• In the Mealy model, the output is a function of both the
present state and the input.
• In the Moore model, the output is a function only of the
present state.
• Between the Mealy and Moore machine:
• Whose output will change instantaneously if there is a
change in input?
• Whose output is synchronized with the clock?

Mealy and Moore Machines
• The block diagram of a Mealy machine
• The block diagram of a Moore Machine

Problem 1:
• Given the Moore machine in the next slide with a D
flip-flop for 𝐴 and a T flip-flop for 𝐵, where the
binary number 𝐴𝐵 represent a state of the circuit.
• Find the state equations.
• Construct the transition table.
• Draw the state diagram.
• Determine the excitation equations for 𝐷𝐴 and 𝑇𝐵 and
output equation for 𝑦. Using the output equation for 𝑦,
prove that the circuit is a Moore machine.

Problem 1:

Problem 2:
• Given the Mealy machine in the next slide with a D
prove that the circuit is a Mealy machine.

Problem 2:

Mealy to Moore Machine
• STEP 1: Determine the states with more than 1
output.
• STEP 2: Create two states for these states.
• STEP 3: Create an empty Moore machine transition
table considering the new introduced states in step
2.
• STEP 4: Fill in the entries of the transition table.

Problem 2:
• Convert the Mealy machine whose transition table
is given below to Moore machine.
𝒙=𝟎 𝒙=𝟏
PS NS 𝒚 NS 𝒚
𝑄0 𝑄2 0 𝑄0 1
𝑄1 𝑄1 1 𝑄2 0
𝑄2 𝑄3 1 𝑄1 1
𝑄3 𝑄0 0 𝑄2 0

Problem 3:
• Convert the Mealy machine whose transition table
is given below to Moore machine.
𝒙=𝟎 𝒙=𝟏
PS NS 𝒚 NS 𝒚
𝑄0 𝑄1 0 𝑄2 1
𝑄1 𝑄1 1 𝑄2 0
𝑄2 𝑄1 1 𝑄0 1

Moore to Mealy Machine
• STEP 1: Construct an empty Mealy machine
transition table.
• STEP 2: Copy all the Moore machine states into the
empty Mealy machine transition table.
• STEP 3: Check the present states and their
corresponding outputs. If the output for state 𝑄𝑖 is
𝑦𝑖 , copy 𝑦𝑖 into the output columns of the Mealy
machine transition table wherever 𝑄𝑖 appears in the
next state.

Problem 4:
• Convert the Moore machine whose transition table
is given below to Mealy machine.
NS
PS 𝒙=𝟎 𝒙=𝟏 𝒚
𝑄0 𝑄3 𝑄1 1
𝑄1 𝑄0 𝑄3 0
𝑄2 𝑄2 𝑄2 0
𝑄3 𝑄1 𝑄0 1

Problem 5:
• Convert the Moore machine whose transition table
is given below to Mealy machine.
NS
PS 𝒙 = 𝟎 𝒙 = 𝟏 𝒚
𝑄0 𝑄1 𝑄3 0
𝑄1 𝑄1 𝑄4 0
𝑄2 𝑄1 𝑄4 1
𝑄3 𝑄2 𝑄3 0
𝑄4 𝑄2 𝑄0 1

Synchronous Sequential
Logic Circuit Design

Review
• So far, we are familiar with the following:
• The different flip-flops
• State diagram
• State table or transition table
• State equation
• Now we will discuss what we call the excitation
table.

Excitation Table
• The excitation table is different from the state table.
• A state table summarizes the present state, inputs,
next states, and outputs of a sequential circuit.
• The excitation table tells you what should the input
to the flip-flop be given the present and next states.
It is like the reverse of the characteristic table.

Excitation Table (SR Flip-Flop)
• The characteristic table of an SR flip-flop
𝑸 𝒕 𝑺 𝑹 𝑸 𝒕+𝟏
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 IND
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 IND
Excitation Table (SR Flip-Flop)
• The excitation table of an SR flip-flop
𝑸 𝒕 𝑸 𝒕+𝟏 𝑺 𝑹
0 0 0 X
0 1 1 0
1 0 0 1
1 1 X 0

Excitation Table (JK Flip-Flop)
• The characteristic table of an JK flip-flop
𝑸 𝒕 𝑱 𝑲 𝑸 𝒕+𝟏
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 0
Excitation Table (JK Flip-Flop)
• The excitation table of an JK flip-flop
𝑸 𝒕 𝑸(𝒕 + 𝟏) 𝑱 𝑲
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0

Excitation Table (D Flip-Flop)
• The characteristic table of an D flip-flop
𝑸 𝒕 𝑫 𝑸 𝒕+𝟏
0 0 0
0 1 1
1 0 0
1 1 1

Excitation Table (D Flip-Flop)
• The excitation table of an D flip-flop
𝑸 𝒕 𝑸 𝒕+𝟏 𝑫
0 0 0
0 1 1
1 0 0
1 1 1

Excitation Table (T Flip-Flop)
• The characteristic table of a T flip-flop
𝑸 𝒕 𝑻 𝑸 𝒕+𝟏
0 0 0
0 1 1
1 0 1
1 1 0

Excitation Table (T Flip-Flop)
• The excitation table of a T flip-flop
𝑸 𝒕 𝑸 𝒕+𝟏 𝑻
0 0 0
0 1 1
1 0 1
1 1 0

Problem Statement
• In the previous section, we were given the circuit,
we were asked to derive the state equation, state
table, and state diagram.
• This time, we are given the state diagram, state
equation, or the state table, and we are asked to
design the circuit.
• The excitation table is a very important tool in
designing synchronous sequential circuits.

State Assignment
• Before you start designing a circuit, you must
express the states of the sequential circuit in binary.
• The number of bits for the state assignment will be
the number of flip-flops you will use for your
design.
• EXAMPLE: How many flip-flops will you use for
your sequential circuit that has:
• 4 states?
• 6 states?

Problem 1:
• Given the state diagram (that I will draw on the
board), design the circuit using
0/1
• RS flip-flops
• JK flip-flops
a
• D flip-flops 1/0 0/0
• T flip-flops
1/1 1/0
b d
1/1
0/0 0/1
c

Problem 2*:
• Design a sequential circuit with two T flip-flops, 𝐴
and 𝐵, and two inputs 𝐸 and 𝑥.
• If 𝐸 = 0, the circuit remains in the same state regardless
of the value of 𝑥.
• When 𝐸 = 1 and 𝑥 = 1, the circuit goes through the
state transitions from 00 to 01 to 10 to 11 back to 00, and
repeats.
• When 𝐸 = 1 and 𝑥 = 0, the circuit goes through the
state transitions from 00 to 11 to 10 to 00, and repeats.

Problem 3: Flip-Flop Conversions
• Convert a JKFF into a DFF.
• Convert a JKFF into a TFF.
• Convert a DFF into a JKFF.
• Convert a DFF into a TFF.
• Convert a TFF into a JKFF.
• Convert a TFF into a DFF.

Practice Problem 1:
• Design the sequential circuit specified by the state
diagram. Use JKFF for the MSB of the states, DFF
for the second, and TFF for the LSB.

Practice Problem 2:
• Given the Moore machine in the next slide with a D
prove that the circuit is a Mealy machine.
• Convert the Moore machine into a Mealy machine, and
draw its circuit.

Practice Problem 2:

State Reduction
• Sometimes, in a sequential circuit, there are
redundant states.
• State reduction algorithms are concerned with
procedures for reducing the number of states in a
transition table while keeping input-output
requirements unchanged.
• What will be the effect if the states are reduced?
• Less components, less cost
• Computationally cheaper

Problem 4:
• Design the sequential circuit described by the state
diagram in the next slide. Use JK flip-flops. Reduce
the states if applicable.

Problem 4:

Design of Binary Counters
• Problem 5: Design a mod-6 synchronous counter
using T flip-flops.*
• Problem 6: Design a counter with the following
repeated sequence: 0  1  3  5  7. Use JK flip-
flops.*

Registers and Counters

Register
• A register is a group of memory elements working
together in order to perform a certain function.
• They can store binary data.
• They can manipulate binary data.
• A counter is actually a special type of register that
can count.

Buffer Register
• A buffer register stores a digital word through
parallel loading.
• Parallel loading is described by the expression
𝑄3 𝑄2 𝑄1 𝑄0 ← 𝑋3 𝑋2 𝑋1 𝑋0

Controlled Buffer Register
• A controlled buffer register is a buffer register with
additional control pins, LOAD and CLR

Shift Left Register

Shift Right Register

Controlled Shift Left Register

Controlled Shift Right Register

SH Register with Broadside Load
• It is a controlled shift right register with parallel
loading.

Ripple Counter

Controlled Ripple Counter

Synchronous Counter
• The synchronous counter minimizes the effects of
propagation delay.

Controlled Synchronous Counter
• It is a synchronous counter with COUNT control
pin.

Ring Counter

Mod-10 Counter

Presettable Counter

Introduction to ELE 421:
Microprocessor Systems

ELE 421: Microprocessor Systems
• What should you expect in ELE 421?
• Algorithmic state machines (ASM)
• Discussion of microprocessor systems
• Computer arithmetic
• Register transfer language
• Microprocessor design
• Simple-as-possible (SAP) microprocessors

Algorithmic State Machines
• What we discussed in ELE 411 are actually finite
state machines. Circles and arrows were only
involved in the diagrams.
• In algorithmic state machines, the diagram looks
more like a flowchart, with more details.

Microprocessor Systems
• Here, you will be discuss the history, evolution, or
developments of microprocessors.
• You will also be introduced to the parts of a
microprocessor and how each part operates.

Computer Arithmetic
• This is the integrated application of our lecture on
number systems and combinational logic circuits.
Only more intense.
• You will also be introduced to single- and double-
precision floating point numbers.

Register Transfer Language
• In this lecture, you will be know the configurations
of how different registers in a computer
communicate.
• You will also be taught to design the circuit that will
accommodate the given RTL.

Microprocessor Design
• Remember Quiz 4? There, we designed a simple
arithmetic and logic unit with only four
instructions.
• In this lecture, you will be taught how to design a
CPU, complete with the ALU and the different
registers.

SAP-1, -2, and -3
• In these lectures, you will be introduced to 3
microprocessors.
• Given a problem, you will write and hand-assemble
a code using hose three microprocessors.

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SEQUENTIAL CIRCUITS

ELE 411: Logic Circuits and Switching Theory

ELE 411: Logic Circuits and Switching Theory

ELE 411: Logic Circuits and Switching Theory

ELE 411: Logic Circuits and Switching Theory

ELE 411: Logic Circuits and Switching Theory

ELE 411: Logic Circuits and Switching Theory

ELE 411: Logic Circuits and Switching Theory

ELE 411: Logic Circuits and Switching Theory

• Draw the characteristic table, state diagram, and

ELE 411: Logic Circuits and Switching Theory

ELE 411: Logic Circuits and Switching Theory

ELE 411: Logic Circuits and Switching Theory

ELE 411: Logic Circuits and Switching Theory

ELE 411: Logic Circuits and Switching Theory

ELE 411: Logic Circuits and Switching Theory

ELE 411: Logic Circuits and Switching Theory

ELE 411: Logic Circuits and Switching Theory

ELE 411: Logic Circuits and Switching Theory

ELE 411: Logic Circuits and Switching Theory

ELE 411: Logic Circuits and Switching Theory

ELE 411: Logic Circuits and Switching Theory

ELE 411: Logic Circuits and Switching Theory

ELE 411: Logic Circuits and Switching Theory

ELE 411: Logic Circuits and Switching Theory

ELE 411: Logic Circuits and Switching Theory

ELE 411: Logic Circuits and Switching Theory

• Negative level clocking

ELE 411: Logic Circuits and Switching Theory

• Negative edge triggering

ELE 411: Logic Circuits and Switching Theory

ELE 411: Logic Circuits and Switching Theory

ELE 411: Logic Circuits and Switching Theory

ELE 411: Logic Circuits and Switching Theory

ELE 411: Logic Circuits and Switching Theory

ELE 411: Logic Circuits and Switching Theory

ELE 411: Logic Circuits and Switching Theory

ELE 411: Logic Circuits and Switching Theory

ELE 411: Logic Circuits and Switching Theory

ELE 411: Logic Circuits and Switching Theory

ELE 411: Logic Circuits and Switching Theory

ELE 411: Logic Circuits and Switching Theory

ELE 411: Logic Circuits and Switching Theory

ELE 411: Logic Circuits and Switching Theory

ELE 411: Logic Circuits and Switching Theory

ELE 411: Logic Circuits and Switching Theory

ELE 411: Logic Circuits and Switching Theory

ELE 411: Logic Circuits and Switching Theory

ELE 411: Logic Circuits and Switching Theory

ELE 411: Logic Circuits and Switching Theory

ELE 411: Logic Circuits and Switching Theory

ELE 411: Logic Circuits and Switching Theory

ELE 411: Logic Circuits and Switching Theory

ELE 411: Logic Circuits and Switching Theory

• Construct the transition table, characteristic

ELE 411: Logic Circuits and Switching Theory

• Complete the timing diagram in the next slide.

ELE 411: Logic Circuits and Switching Theory

ELE 411: Logic Circuits and Switching Theory

ELE 411: Logic Circuits and Switching Theory

ELE 411: Logic Circuits and Switching Theory

ELE 411: Logic Circuits and Switching Theory

ELE 411: Logic Circuits and Switching Theory