Beruflich Dokumente
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1
CURSO: Sistemas Operativos
CATEDRATICO: Ing. Mario David Soto E.
Primer Semestre 2020 Ciclo: 1 Jornada: Nocturna
1.13 Consider the following two options: Asymmetric cluster nd parallel grouping. With
asymmetric clustering, the host runs database program with other hosts just to monitor it. If so the
server is down,tthe host monitoring server is activated. It is however, it is not suitable for
redundancy potential processing power for two hosts. With parallel cluster, the program database is
managed by the two hosts. Running parallel clusters provides some type of distribution File locking
mechanism on the shared disk.
1.16TheCPUcan initiate a DMA operation by writing valuesinto special registers that can be indepe
ndently accessed by the device.The device initiates the corresponding operation once it receives a c
ommand from the CPU. When the device is finished with its operation, itinterrupts the CPU to indic
at the completion of the operation.Both the device and the CPU can be accessing memory simultane
ously.The memory controller provides access to the memory bus in a fairmanner to these two entitie
s. A CPU might therefore be unable to issuememory operations atpeak speeds since it has to compet
e with thedevice in order to obtain access to the memory bus.
1. 17 An operating system for a machine of this type would need to remain o in control (or monitor
mode) at all times. This could be accomplished by twmethods: a. Software interpretation of all user
programs (like some BASIC, Java, and LISP systems, for example). The software interpreter would
provide, in software, what the hardware does not provide. b. Require meant that all programs be
written in high‐level languages so that ll object code is compiler‐produced. The compiler would
generate (either in‐ine or by function calls) the protection checks that the hardware is missing.
1.18 Recall one purpose of cache is to store frequently accessed data for
efficient access. When the processor needs data that is not available in
its cache, it can then access the cache shared by all of the processors.
This is much more efficient each processor sharing the same cache.
1.19
1.f
2.c
3.a
4.e
5.g
6.b
7.d