Project of High-Speed Information Search on FPGA

- Research and Education Platform “e-Research FPGA” -

Yoshikazu Miyanaga and Shingo Yoshizawa (Global COE, Grad. Sch. of IST, Hokkaido University)

1. Interdisciplinary Field Research 3. e-Research FPGA

Collaborative work between experienced and inexperienced research fields Research and education platform that provides training courses by e-Learning,
on FPGA design. remote controlled development software tools and FPGA boards through
Current Major Topics on internet connection.
FPGA Design
FPGA FPGA Design e-Learning
Experienced Field - Image/Video Processing
Board Server Server
- Speech/Audio Processing
- Wireless/Wired Communication Circuit Training
FPGA Configuration
New Samples
Design
Paradigms Knowledge Emerging Topics
Data Development
- Computational Analysis Monitoring Acquisition
- Algorithm Analysis Software Web Lecture
Inexperienced Field - Bioinformatics
(Japanese/English)

- Data Mining and Pattern Matching Network

- Mechatronics Camera Remote Control User’s
PC
a
MUL q
2. What is FPGA ? Console on b
VNC Viewer
(1) What is FPGA? module multiplier_16x16(a, b, q);
input [15:0] a, b;
- A field-programmable gate array (FPGA) is a digital integrated circuit output [31:0] q;
device that can be programmed by users after manufacture. assign q = a * b;
endmodule
(2) What is purpose?
Example of 16-bit Multiplier in
- Users can develop a special-purpose computer that operates more than 100 Verilog HDL
times faster than a personal computer*.
(3) Is it difficult to try FPGA design? 5. FPGA Design in Wireless MIMO-OFDM Communication
- Not difficult. Users can design a circuit by using hardware description - MIMO-OFDM systems with an 80-MHz occupied bandwidth (proposed as
language (HDL) in the same way as software programming. “HU-VHT”) have been studied for next generation WLAN with over 1-Gbps
- Remote controlled development software tools and FPGA boards with are data transmission.
provided by the Global COE program. Users do not need to spend time to - The MIMO-OFDM transceiver with 1.5-Gbps data transmission has been
make development environments on FPGA design. evaluated in circuit performance and is to be implemented into a FPGA board
* Typical researches in FPGA design. for data transmission experiments over wireless channels.
Block Diagram of 4x4 MIMO-OFDM Transceiver
4. FPGA Design in Robust Speech Recognition
 Transmitter
- A hardware-based speech recognition system has been developed for
achieving real-time processing in robust speech recognition.
- The developed system (“HMM Recognition V3”) provides more than 98%
in recognition accuracy under 20-dB SNR environment and achieve 1/10 in Scrambler Encoder Interleave Mapper Pilot IFFT Re-order & Preamble
Insertion
energy dissipation compared with a DSP processor. & Puncture GI Insertion Insertion

 Receiver
Block Diagram of Word Speech Recognition Demapper Viterbi Decoding

Covert to Speech Feature Calculate Probability

(Cepstrum) (likelihood Scores)

Speech Speech Robust Speech Frame & Freq. FFT Re-order & MIMO Channel Est. De-interleaver
De-scrambler
Results
Analysis Processing Recognition Synchronization Pilot Remove & Decoding

Preprocessing
ρk
σ2 Inv
Speech Feature Vectors Reference Models Matrix Pk Matrix Rk Matrix Gk
Mul Inv Mul SINR
Reference Patterns by Speech Training Hk Qk Calculation
Signal
State Transition Probability Scope
Matrix Channel
Add Estimation Memory
Output Prob. Calc. Score Calc. MIMO Decoding
a11 a22 a33 a44 Set of States uk ^
Output Prob. Calc. Score Calc. yk sk
a12 a23 a34 a45 ot Select
Vector
q1 q2 q3 q4 uk, yk Mul
Max Pk
Output Prob. Calc. Score Calc.
FPGA Board
Path for upper
state G k  (H kH H k   2I) 1 H kH
b1 (k ) b 2 ( k ) b N (k ) (OFDM TX & RX)
Output Prob. Calc. Score Calc.
1
Output Probability Rk Qk
 j ,k 
sˆ k  G k y k (t ) 4 2 [R k ] j , j Web Camera
Hidden Markov Models (HMM) Parallel Computations in HMM
MPU Interface
Master Bus
Filter Coefficients for RSF
Data Flow in 4x4 MIMO Channel FPGA Board in OFDM Communication
Interrupt Signal
CLK Estimator and Decoder
16 RESET Recognition System
16 5 2 2 1 RSF/DRA SRAM HMM
SRAM
24 24 16 16 16 interface Sampling Clock
SW
Bus Control
16
System Control
16
20
Generator
6. Future Plans
5 16
24 24 16 16 24 24
3
Address External SRAM - Interdisciplinary research project
16 5 2 2 1
MFCC SRAM SRAM
Data Control RS232C I/F - FPGA design seminar (on Feb. 2009) *
- e-Learning and remote network services*
Slave Bus Data Control
Working for MFCC and RSF *GCOE RA/PDs and IST student s can join if they submit an
Chip Select Feature parameters before speech detection Microphone
A/D Converter application.
Circuit Structure of “HMM Recognition V3”
FPGA Board in Speech Recognition - International research and education project FPGA Design Seminar