IET Research Journals

Submission Template for IET Research Journal Papers

Switching Losses Prediction Methods ISSN 1751-8644

doi: 0000000000
www.ietdl.org
Oriented to Vertical-Diffused Power
MOSFETs – A Review
Wesley Josias de Paula 1 , Gabriel Henrique Monteiro Tavares1 , Guilherme Marcio Soares1 , Pedro Santos
Almeida1 , Henrique Antonio Carvalho Braga1
1
Electrical Engineering Post-Graduation Programme, Federal University of Juiz de Fora, Rua José Lourenço Kelmer, s/n - São Pedro, Juiz de Fora –
MG, Brazil
* E-mail: wjpeletrica@yahoo.com.br

Abstract:
The aim of this paper is to review the state-of-the-art of recent prediction methods for power MOSFETs switching losses using
datasheet parameters. A detailed technical literature investigation is carried out in order to collect the latest research contributions
on this subject, pointing out their main features and drawbacks. Then, a particular section is dedicated to compare three different
selected methods oriented to Si-based and SiC-based MOS power transistors. This analysis is performed on several voltage
and current level ratings using an experimental prototype of a double pulse circuit. According to the experimental results it can
be concluded that it is very difficult to obtain a high level of accuracy concerning MOSFET switching losses, mainly due to the
uncertainty when selecting datasheet information. Among the parameters that most influence the measurements, one could list the
MOSFET transconductance, the channel threshold voltage and the parasitic inductances.

1 Introduction 2 Switching losses estimation in power MOSFET

Currently, the silicon-based metal-oxide-semiconductor field-
effect transistor (MOSFET) is the preferred semiconductor device in
low to medium-powered high-frequency power processing applica-
tions [1–5]. This kind of transitor represents one of the major sources
of power losses and heating in such applications often requiring
a proper cooling system to be integrated into the static converter.
According to the tendency of higher switching frequencies of such
converters, device switching losses need to be very well modeled in
order to achieve a good quality design.
The estimation or calculation of the switching losses in power
MOSFETs has been extensively investigated in the technical literature
but it is not yet consolidated because of the inaccuracy or the com-
plexity of some prediction methods. This topic is important because
a more accurate assessment regarding such losses may reduce the
design and optimization time of a static converter without the need to
build various prototypes for experimental comparison purposes [6].
Considering that the calculation methods of switching losses usu-
ally present low accuracy, several works have been proposed in
technical literature to improve the key issues on the matter, namely
simulation time, computational effort and accuracy. Therefore, the
main objective of this paper is to present a review of the most recent
datasheet-dependent switching losses prediction methods oriented to
power MOSFETs. Moreover, the text also provides a performance
comparison study concerning three selected methods by employing
an experimental double-pulse test circuit approach.
This document is structured as follows. Section II discusses some
conventional estimation methods of power MOSFETs switching
losses and addresses their main limitations. Section III presents an
extensive comparison involving three different analytical techniques
devised to estimate the switching losses. In order to effectively evalu-
ate the main features and the performance of those selected techniques
a practical experiment is proposed. Therefore, Section IV is dedicated
to describe the acquisition methodology, which is applied to three
different transistor unities, including a SiC device. A thorough dis-
cussion regarding the results is also given at the end of this section.
Finally, the main conclusions are carried out in section V.
Power losses analysis approaches are presented as an interesting
alternative for the performance investigation of power MOSFETs
devices. This research field evaluates both the conduction losses and
the switching losses. The first one is related to the power losses in
the device on-resistance whereas the former results of a simultaneous
exposure of a MOSFET to voltage and current during a transition
between conducting and blocking states.
This paper is focused on switching losses estimation methods and,
according to the technical literature, such approaches are devised in
order to obtain shorter simulation times and higher accuracies. These
prediction models can be particularly divided into three categories:
1) Physical-model based device, such as the thickness of oxide layer,
substrate doping concentrations, device geometry, etc.
2) Behavioral device model, in which SPICE-based algorithms are nor-
mally used, having good trade-off between precision and simulation
time.
3) Mathematical model (analytical model), which adopts expressions
by means of the equivalent circuits analysis. The main advantage of
this approach over the aforementioned models is the lower simula-
tion time. However, the biggest challenge of this alternative is the
parameter dependency and accuracy.
Physical models are normally based on finite-element simulations
and provides the best results, regarding accuracy, however, it could
take few days to simulate a complete static converter [7]. The SPICE
Models are faster than physical models, but also demands long sim-
ulation times when small time-steps are used, being a significant
drawback in the evaluation of high-frequency converters. Despite
that the SPICE models presents a good trade-off between accuracy
and simulation time, the fact that some parasitic elements are not
properly modeled can lead to poor results in terms of switching losses
prediction [8].On the other hand, the analytical calculation of switch-
ing losses are a straightforward mechanism to obtain a first insight
regarding the switching losses, thus allowing a quick comparison
between different devices and operating conditions.

IET Research Journals, pp. 1–9

c The Institution of Engineering and Technology 2015 1
 The following points outline how parameters and conventional
assumptions affect the accuracy of analytical-based predictions: Lb
iLb Ds

A1) MOSFET parasitic components (such as source inductance, drain iD Vdd

inductance and MOSFET output capacitances): these parasitic param- iD
eters should be included as they are an important source of switching iG Rg CGD
losses, and because they contribute to an overlap between the device CDS vDS
vdr vDS
voltage and current [7–18].
A2) Loss distributions: since the charging and discharging losses cannot CGS M
vGS
be separated, the effect of MOSFET output capacitance, Coss , is ton toff t(s)

indirect and it affects both the rise and fall time intervals. The separa-
tion between the overlap loss and the losses owing to the MOSFET
output capacitance results in inaccurate predictions. Moreover, using
a constant fixed time for rise and fall intervals leads to an improper
approximation [19].
A3) Current divergence: the input characteristic obtained by means of
MOSFET datasheets (QG curve) cannot be easily used because it
neglects the Coss currents. In addition, this approach adopts an erro-
neous assumption that the load current is equal to the channel current.
Therefore, such simplifications introduce current deviations when
compared to the device actual behavior [19]. It must be also high-
lighted that all the transition periods are determined from the parasitic
capacitance values.
A4) Circuit analysis (double-pulse circuit, as detailed in Section 2.1):
in the analytical approach it is considered the complete solution
of the electrical circuit where the device is employed by including
parasitic inductances and capacitances in all operating stages. The
solution is carried out based on the effects of the parameters, such as
gate driver voltage, switching frequency, transconductance, threshold
voltage, gate source inductance, etc. The highlighted point is that
circuit parameters drive the rise time and fall time [19]. On the other
hand, most literature uses the circuit parameters only in the circuit
switching loss calculation of the rise and fall time intervals. Then, the
circuit parameters effect variation is divided into two alternatives:
A4.1) Add the MOSFET characteristics and circuit parameters for
calculating the switching times (ton and tof f );
A4.2) Add the circuit parameters only to derive power losses under overlap
calculation
(a) (b)
Fig. 2: (a) Typical experimental circuit, called double-pulse test cir-
cuit (DPT), used to evaluate the switching losses of a given MOSFET,
or DUT, an acronym for device under test (highlighted in dashed
lines); (b) Simplified theoretical switching waveforms of a power
MOSFET, adapted from [20].
In Fig. 2a, vGS , is the gate-source voltage, Vdd is the input voltage,
iD is the drain current, and Rg is the total gate resistance, given by
Rg = Rg(int) + Rg(ext) , (1)
where Rg(int) is the internal gate resistance and Rg(ext) is the
external gate resistance.
Fig. 3 shows the idealized waveforms of the DPT circuit. The first
pulse duration is such that the current through device reaches the
desired test value, Idd . So, the falling edge of the first pulse provides
information related to the turn-off power loss of the device. As a
consequence, the pulse width, ∆t1 is defined by the combination of
the load parameters and MOSFET characteristics as shown in Fig. 3
and equation (2). Moreover, the vdr signal magnitude must be the
same as the gate-source voltage recommended by the manufacturers
in datasheets. For SiC devices, as an example, a value of 18 V is
commonly adopted.

Based on the aspects cited here, the classification for prediction of vdr Turn-on Turn-off
switching losses in power MOSFETs can be organized according Vgg(on) Turn-off
to Fig. 1. As already mentioned, this paper proposes a discussion
concerning the issues associated with switching losses prediction by
analytical methods based on datasheet parameters only.

0
Prediction of switching
losses in MOSFETs
Vgg(off)
t
Physical
Spice-based Mathematical iD Idd
model (1) models (3)
model (2)

MOSFET Loss Current

Circuit parameters
parasitic distributions (A2) divergence (A3)
(A4)
components (A1)

Rise time and fall time Power loss derived t

under overlap
used for calculation (A4.1) vDS
calculation (A4.2) Vdd
Fig. 1: Classification of switching losses estimation methods oriented
to power MOSFETs.

t
t1 t 2 t3 t 4
Δt1 Δt2(max) Δt3(max)
2.1 The Double Pulse Test Circuit

The Double-pulse test circuit (DPT) is commonly used in the anal-
ysis of the switching transients in hard-switching applications. Fig. 2
depicts the test circuit (a) and the simplified theoretical electrical
waveforms of the device under test (b), namely the drain-to-source
voltage and drain current.
Fig. 3: Idealized waveforms of the DPT circuit.
In Fig. 3, Vgg(on) is the high-level for turn-on the MOSFET and
Vgg(of f ) is the low-level for turn-off the MOSFET.

IET Research Journals, pp. 1–9

2
c The Institution of Engineering and Technology 2015
 parameters, with respect to datasheet information, providing more
Rds(on)
  
Lb accurate MOSFET capacitances models for the analysis of switch-
∆t1 = ln 1 − Idd (2) ing transitions. Such parameters describe the area modulation effect
Rds(on) Vdd
of gate-source and drain-to-source voltages on the interelectrode
where Rds(on) is the on-resistance of the MOSFET under test. Usu- capacitances during commutations. They are identified by means
ally, the second pulse is recommended to be as short as possible, so of empirical evaluations starting from experimental measurements
that the iLb current decreases according to a T OL1 dimensionless during switching transitions.
value, which depends on Idd . Thus, ∆t2(max) is defined by Recent researches have investigated and proposed more accurate
switching losses estimation. These works can be classified depending
! on the previously listed points, as organized in Table 1, which shows
Lb vf d + T OL1 · (Rds(on) ) · Idd the switching prediction losses models highlighting the aspects that
∆t2(max) = ln (3) are considered and disregarded while quantifying such losses. As
Rds(on) Vf d + Rds(on) · Idd
can be seen in Table 1, [9, 10, 13, 25] have proposed approaches
where vf d represents the forward voltage of, Ds . for switching loss prediction that consider the changes in MOS-
FET behaviour during the transitions intervals, mainly the changes
∆t3(max) represents the maximum value that iD can achieve at
in parasitic capacitances. The aforementioned models allow for a
this stage, as shown in (4). In addition, T OL2 is a dimensionless straightforward and fast estimation of the switching losses by simpli-
value greater than zero and indicates how much the Idd load current fying the calculation of time intervals ton and tof f . However, their
can increase regarding its original value. After this stage, the MOS- main drawback is that they neglect switching losses effects due to
FET is turned off. Usually, a time of 500 ns are adopted for ∆t2(max) parasitic inductances. Typically, these models predict that turn-on and
and ∆t3(max) . turn-off losses are nearly similar in magnitude. In a real converter,
operating at a high switching frequencies, those models reveal to be
! highly inaccurate since turn-off loss is much larger due to parasitic
Lb Vdd − (Rds(on) ) · (1 + T OL2 )Idd
∆t3(max) = ln inductances [12]. In addition, current and voltage ringing are always
Rds(on) Vdd − Rds(on) · Idd observed in a switching-mode power supplies and it is ignored in the
(4) traditional model. It is interesting to note that [11], for example, takes
According to this explanation, the experimental evaluation is taken into account the nonlinear nature of device capacitances and the para-
at once and no repetition is conducted in order to avoid an increment sitic inductances of the circuit (such as the source inductance shared
of device junction temperature. by the power stage and driver loop as well as the drain inductance).
A commonly used formula for estimating the power MOSFET
switching losses (Psw ) is given by (5) [16].
Table 1 Comparison of the mathematical switching power loss models
1
Prediction loss model
Psw = iD · vDS · fs · (ton + tof f ) + (Coss · vDS ) (5) Characteristic [9] [7] [10] [13] [14] [15] [16] [17] [8] [18] [5] [11] [12]
2
(A1) YES1 YES YES1 YES1 YES1 YES1 YES YES YES YES1 YES YES YES
(A2) NO NO NO NO NO NO NO NO NO NO NO NO NO
where frequency, fs , is the inverse of the switching period, Ts ; vDS (A3) NO NO NO NO NO NO NO YES NO YES2 YES YES YES
(A4.1) NO NO NO YES NO NO YES NO NO NO NO NO NO
is the drain-to-source dut voltage iD is the drain current of the MOS- (A4.2) YES YES NO NO YES YES NO YES YES YES YES YES YES
FET, while ton and tof f are the power MOSFET turn-on and turn-off
times, respectively. From equation (5), the first term simply calculates 1
: The method considers exclusively the stray capacitances.
the switching power loss during the transition periods in Fig. 2 (b). 2
: The method considers variable resistance of the MOSFET gate
The second term represents the losses owing to the output capacitance driver.
(Coss ), i.e. CGD + CGS , whose energy is dissipated in the device It is also worth mentioning that the model proposed by [12]
channel by means of a joule losses mechanism, during the entry into includes the impact of power supply inductance and the transistor
conduction stage. According to semiconductor manufacturers appli- parasitic inductances on switching losses. The model uses simple
cation notes, the switching times ton and tof f are often estimated equations to calculate the rise and fall times and piecewise linear
by approximations of voltage and current waveforms to allow switch-
ing losses calculation. According to this reference, the rise time is
Qsw
ton = tof f = , (6) strongly related to the MOSFET parasitic capacitances and the cur-
iG rent capability of the gating circuitry; the fall time is, on the other
where iG is the average gate drive current and Qsw is the gate charge hand, dictated not only by the same parameters, but also by the cir-
parameter, as provided in most power MOSFET datasheets. cuit parasitic inductances. In [5], a circuit-level analytical model
The classic estimation method is based on computing the switching also takes MOSFET parasitic capacitances and inductances, along
losses by using the expression (5), which adopts the switching times with circuit stray inductances and reverse current of the freewheeling
derived by (6). However, this can be very inaccurate, mainly due to the diode into consideration in order to evaluate the MOSFET switching
controversial inclusion of the second term in (5), which is related to characteristics.
the output capacitance, and because of the nonlinear nature of drain-to- Graovac et al. [14] add the nonlinear effect of the reverse transfer
source voltage. In addition, the extraction procedure of the gate charge capacitance Crss , i.e, CGD for the calculation of voltage rise time
parameter is usually not a trivial procedure considering the variety and voltage fall time and adopts the two capacitance average value
of commercially available products. Furthermore, the documentation in calculation. This method considers the worst case for the switch-
adopted by the manufacturers does not follow the same guidelines. ing losses prediction. As reported by [14], regarding turn-on energy
Basically, a thorough evaluation may consider some particularities losses in power MOSFETs occurs when the influence of the reverse-
and parameters, such as the influence of parasitic inductances, as recovery of the freewheeling diode is accounted. In Guo et al. [15], an
well as the drain-to-source voltage dependence with the junction improved calculation methodology of [14] is developed by using the
capacitances. datasheet reverse transfer capacitance (Crss ) against drain-to-source
Over the last few decades, many studies have been presented in voltage (vDS ) curve provided in datasheet. The method improves the
the most prestigious scientific conferences and journals, highlighting evaluation of the drain-to-source voltage during the rise-time voltage,
the key importance of a proper modeling of the MOSFET nonlinear tru and the fall-time voltage (tf u ). However, it still disregards the
capacitance aiming a more accurate prediction of device switching effects of parasitic inductance in the analysis.
losses, especially in hard switching converters. Various approaches To overcome the limitations of most estimation methods men-
to MOSFET modeling and parameters extraction have also been tioned before, some authors have addressed the dynamic behavior of
proposed [21–24]. Particularly, in [23] and [24], the authors dis- a power MOSFET in segmented divisions describing various com-
cuss an experimental test allowing the identification of additional mutation stages [7],[16, 17]. All these models have in common the

IET Research Journals, pp. 1–9

c The Institution of Engineering and Technology 2015 3
segmentation in various time intervals of an operation cycle. In this convergence time of the method while the implementation complexity
context, the turn-on and turn-off periods are constituted by multiple is regarded to the number of equations and iterations that must be
intervals, each one associated with an equivalent circuit by switching evaluated.
an inductive load.
It is claimed by some authors, e.g. [16], that including so many
3 Comparison among selected estimation
parasitic effects and physical parameters in analytical switching
losses prediction methods is still advantageous, since the simula- methods of MOSFET switching loss
tion time remains much shorter than those associated to the so
called physical-parameter-based methods or even compared with This section is dedicated to the in-depth analysis of three predic-
SPICE-based simulations methods. Also, according to the authors, tion methods for MOSFET switching losses using only datasheet
the resonances between parasitic inductances and capacitances can parameters, namely the Brown [9], Guo [15] and Ahmed [8] methods.
result in significant switching losses. It is important to compare them adequately so that it is possible to
In order to improve the accuracy of the analytical method, the identify eventual advantages and drawbacks in potential applications.
inclusion of drain and gate inductances in the circuit is proposed in The methods were selected owing to their different characteristics,
[7]. Those elements represent parasitic effects mainly due to manufac- allowing for a comparison regarding their complexity, assumptions
turing process and packaging [7]. Indeed, the equations of the circuit and results.
are derived for each operating stage. Authors of [7] also analyze the The Brown method [9], is described using straightforward model-
influence of the capacitance along with the drain and source induc- ing of the MOSFET behaviour, as well as equations to determine the
tances in the switching process. In addition, it shows that the turn-on MOSFET switching intervals.
and the turn-off transients are quite different differing from what The Guo method [15] is an improvement of the method proposed
is usually adopted in technical literature. According to the authors, in [9] considering the effects of nonlinearity of the reverse transfer
it is still difficult to predict the converter efficiency by using the capacitance.
model proposed by them due to the uncertainties associated with Finally, the Ahmed method [8], develops a methodology using
the parasitic inductance, the threshold voltage and transconductance the complete modeling of MOSFETs, i.e. the method considers the
variation. Furthermore, it may be inferred that the major cause for maximum influence of the circuit parasitic elements, besides the
errors can be attributed to some parameters being used - which are nonlinear behaviour of the device parasitic capacitances. So, the
operating-point dependent and cannot be applied when all operating methods, proposed by Brown, Guo and Ahmed are revisited and
regions are under consideration. In the study carried out in [17], an compared in next subsections.
estimation method based on a second order model for the transient
analysis of SiC MOSFET with the inclusion of parasitic elements has 3.1 Brown Method
been proposed. The aforementioned method analyzes the source and
gate inductances impact on switching process. The effect of output According to the Brown method [9], the switching transient analy-
capacitance (Coss ) on losses is also taken into account in this model. sis of the power MOSFET can be divided into six intervals, as shown
Higher source inductance values will reduce the switching speed, in Fig. 4. All equations that describe the switching turn-on times are
increasing the rise-time current. On the other hand, it was shown that stated by (7), (8) and (9), concerning t1 , t2 and t3 , respectively:
gate inductance affects the switching process, which is also dependent
to the gate-source voltage. The methodology has been validated using
a software based on the finite element method. iD,
vGS, iD
Ahmed, Todd and Forsyth describe an analytical model with the
inclusion of the input capacitance (CGD + CGS ), reverse capac- vDS
itance, CGD , as well as the drain-to-source inductance in the
double-pulse circuit [8]. This techinique uses an equation to describe Vdr(on) vGS
the nonlinear behavior of the junction capacitances. The analysis is
performed for a SiC device operating at high-voltage levels. Accord-
ing to the authors, the average estimation error was lower than 50%
Vpl
in the analyzed range. The main drawback of this the model is the
Vth
need to measure the source and drain inductance of the power circuit vDS
experimentally. Vds(on) Vdr(off)
In view of the aforementioned aspects, it can be recognized the t1 t3 time
development of a great number of works aimed on improving the t2 t4 t5 t6
accuracy of hard-switching MOSFET behavior. In spite of such huge tir tfu tru tif
number of methods, there is no consensus regarding which one is
the most accurate for estimating losses. In addition, it is worth men- Fig. 4: Switching waveforms turn-on and turn-off, adapted from [9].
tioning that the datasheet aspects are given to specific voltage and
current conditions, being necessary to evaluate them under different
conditions. !
Table 2 shows an overall comparison involving accuracy, computa- Vdr(on)
tional effort, and implementation complexity of the aforementioned t1 = Rg · (CGS + CGD ) ln (7)
Vdr(on) − Vth
methods of estimating switching losses in power MOSFETs. In this
table, the following convention has been adopted: where Vdr(on) represents the high-level output voltage applied to the
Table 2 Comparison among several estimation methods MOSFET switching loss external gate resistance; Vth is defined as the gate voltage at which
Prediction loss model the device starts to turn-on; while CGS and CGD are the gate-source
Characteristic [9] [7] [10] [13] [14] [15] [16] [17] [8] [18] [5] [11] [12] capacitances and gate-drain capacitances, respectively.
Accuracy L A L L L A A A H L A A A
Computational Effort L H L L L A H H H L H L L  
Implementational complexity L H L L L A H H H L H L L

1
 
t2 = Rg · (CGS + CGD ) · ln  (8)
 
Vpl 

The accuracy of a given method in Table 2 is classified according 
1−
to the following performance criteria: High (H) means an error less Vdr(on)
than 20%, Average (A) is related to an error between 20% and 50%
and Low (L), which is concerned to an error greater than 50%. On Vdd − Vds(on)
t3 = tf u = Rg · CGD · , (9)
the other hand, the computation effort is classified according to the Vdr(on) − Vpl

IET Research Journals, pp. 1–9

4
c The Institution of Engineering and Technology 2015
where Vpl represents the Miller’s plateau voltage, Vds(of f ) is the In order to better explain the method, it is adopted a group of
low level drain-to-source voltage of the MOSFET, and Vds(on) is the n subintervals during the voltage fall time, requiring n + 1 voltage
drain-to-source voltage observed during the MOSFET conduction. levels vDS , what leads to the final tf u value according to (16).
By analyzing Fig. 4, it can be concluded that t3 is the equivalent n
vDS(i+1) − vDS(i)
time taken for the voltage to fall to its on-state value during the turn-
X
tf u(guo) = Rg · Crss(i+1) , (16)
on transient (tf u ) and that the difference between the intervals t2 and Vdr(on) − Vpl
i=1
t1 is the time taken for the current to rise to its on-state value (tir ).
Turn-off times are defined as t4 , t5 and t6 , being given by (10), Similarly, the rise-time of the voltage is defined by (17):
(11) and (12), respectively.

Vdr(on)
 
n
t4 = Rg · (CGS + CGD ) · ln , (10)
X vDS(i+1) − vDS(i)
Vpl tru(guo) = Rg · Crss(i+1) , (17)
Vpl − Vdr(of f )
i=1
Vds(of f ) − Vf
 
t5 = tru = Rg · CGD , (11) where i = 1, 2, 3, ..., n
Vpl Analogously, the energy losses are calculated by using (13), (14)
where Vf represents the voltage across MOSFET conducts the full and (15).
load current and tru represents the time required for drain-to-source
voltage to achieve its nominal value, when rising from Vds(on) during 3.3 Ahmed method
the turn-off period.
! This method is presented in [8] and adopts a similar approach
Vpl as described in [16], but it includes additional parasitic elements
t6 = tif = Rg · (CGS + CGD ) ln , (12)
Vdr(on) during the transient stages. Moreover, a more accurate method that
accounts for the influence of junction capacitances, which uses the
curves provided in the device datasheet is proposed. According to the
where tif represents the time for the drain current to reach its off-
Ahmed Method, it is necessary to solve four correspondent circuits
state value. Finally, the energy related to the switching losses can be
regarding the specific stages, which are shown in Fig. 6. It is worth
calculated by using (13), (14) and (15):
mentioning that this circuit is the same DPT circuit of Fig. 2, although
1
it includes some parasitic elements, namely the drain stray inductance,
Eon = Etir + Etf u = v · i tir + tf u , (13) Ld , a drain resistance, Rs , a source stray inductance, Ls , a diode and
2 DS D load inductor lumped parasitic capacitance, Cak , and the Schottky
1
diode voltage, vak . In addition, the inductor is large enough to be
Eof f = Etru + Etf i = v · i tru + tif , (14) considered a constant current source.
2 DS D ˙ (which is the first-
Four state variables, vGS , vDS , iD and iD
1
time derivative of the drain current) are adopted and solved, in a
Etotal = v · i tir + tf u + tru + tif . (15) computer, by applying a state-space representation. In this analysis,
2 DS D the gate inductance Lg was neglected because of its small value when
compared with the power loop inductances Ls and Ld . The transient
3.2 Guo method subperiods are listed at following.
This method considers the reverse transfer capacitance (Crss ) of 1) Subperiod 1 (turn-on delay): when a signal from Vdr(of f ) until
power MOSFET as a function of vDS voltage, as presented in Fig. 5. Vdr(on) is applied, iG charges the gate-source capacitance and
The current subintervals, tif and tir are not affected because the gate-drain capacitance, CGS and CGD , respectively. The MOSFET
drain-to-source voltage is nearly constant during those periods. remains off until vGS reaches Vth and Idd flows through the free-
wheeling diode. The expressions that describe this subperiod are
stated in (18) to (22).
vDS (V) vDS (V)
50 vDS(1) = Vdd
Crss
Ciss

vDS(2) diD di
40
Rg · iG + vGS + Ls · + Ls · G = Vdr(on) (18)
30 vDS(3) dt dt
20 vDS(4)
dvGS i iG
= G = (19)
dt Ciss CGS + CGD
10 vDS(n)
Coss

C (pF) 0 vGS = vGD + vDS (20)

1M 100k 10k 1k
v
100 DS(n+1)
= Δtfu1 Δtfu2 Δtfu3 Δtfun time
Crss(n)
Crss(n+1) Crss(4) Crss(1) vDS(on)
Crss(2) t3=tfu= Δtfui(i=1,2,3,..., n)
Crss(3) Ciss = CGS + CDS (21)
(a) (b)

Fig. 5: (a) MOSFET parasitic capacitance waveforms 

(APTC60BBM24T3G) and (b) variation of vDS during turn-on,
adapted from [26].
The implementation methodology is based on determining the spe-
cific capacitances according to the drain-to-source voltage associated
to the several subintervals. Afterwards, a group of voltages are added
between Vdd and Vds(on) with respect to a specific capacitance, Crss .
In Fig. 5 (b), each time segment is associated with the voltage fall
time, tf u (i). It is assumed that these subintervals are relatively small,
and Crss remains constant during these periods. Finally, tf u can be
obtained by summing all subintervals of tf u (i).
−vGS − Rg iG + Vdr(on)

d iG
= (22)
Ls dt
2) Subperiod 2 (current rise time): the drain current rises until it
reaches the load current. In this stage, the channel properties are
modeled as a voltage-controlled current source, which is proportional
to the difference between the gate-source voltage and the threshold
voltage (vGS − Vth ). The current rise time represents the interval
necessary for vGS to achieve the Miller’s plateau voltage, Vpl , where
Vpl = Idd /gm + Vth and gm is the transconductance of the MOS-
FET. The expressions that describe this subperiod are presented in
(23) to (26).

IET Research Journals, pp. 1–9

c The Institution of Engineering and Technology 2015 5
 diD
vDS = Vdd − (Ls + Ld ) · − Rs · iD (23)
dt vak vak
Cak D Cak D

dvDS iD Rs iD Rs
iD = gm · (vGS − Vth ) + Coss · (24)
dt Ld
vDS
Vdd Ld
vDS
Vdd
iG iG
where, Rg Rg CGD
CGD CDS CDS
Coss = CDS + CGD (25) vdr vdr
vGS CGS vGS CGS
di
Rg · iG = Vdr(on) − vGS − Ls D (26) Ls Ls
dt
(a) (b)
3) Subperiod 3 (Miller time): It is the time required for the drain-
to-source voltage, vDS , to drop from the off-state, Vdd , to the low
vak vak
conduction voltage, Vds(on) , which equals iD times Rds(on) . The Cak D Cak D

expressions that describe this subperiod are presented in (27) and

iD Rs
(28). iD Rs

Ld Vdd Ld Vdd
dvak 1 vDS vDS
= · (iD + Idd ) (27) iG iG
dt Cak Rg CGD CDS
Rg CGD CDS
Rds(on)
di vdr vdr
Vdd − Ls D − vak − Rs · iD = vDS (28) vGS CGS vGS CGS
dt
Ls Ls
4) Subperiod 4 (ringing period): It is considered the time to overcharge
the input capacitance, Ciss , and to completely turn-on the gate chan- (c) (d)
nel. The expressions that describe this subperiod are presented in (19)
and (22), as well as (26) to (29). Fig. 6: General switching circuit of a SiC power MOSFET with
parasitic components (a) subperiod 1 (turn-on delay); (b) subperiod 2
vDS dv (Current Rise Time); (c) subperiod 3 (Miller time), and (d) subperiod
+ Coss DS = iD (29) 4 (Ringing Period), adapted from [8].
Rds(on) dt
Regarding the switching turn-off stages, the events occurs similarly
to the switching turn-on stages, although the circuit should be ana-
lyzed in the opposite way. The detailed modeling will be suppressed 4 Acquisition method and calculation
here, as it can be found in [8].
The Ahmed method can be summarized as follows. At first, the In order to perform an experimental comparison among the dif-
previous declared set of equations (15)-(26) are organized in the ferent estimation methods, the DPT circuit was assembled as seen
form of a state-space system. This system is, then, solved by means in Fig 7. Its main parameters are detailed in Table 4. The printed
of a MATLAB function named “ode45”. This function returns a circuit board (PCB) of this circuit has a hole to house the current
time-dependent solution vector concerning the desired set of system probe, so that it was not necessary to add external wiring to the
variables. Those vectors are associated to a correspondent transition experimental setup for measuring the DUT current. Furthermore, a
stage, which depends on specific process conditions. After the conclu- SiC freewheeling diode, Ds , with small reverse recovery charge is
sion of a given stage solution, its vector of values is used to feed up used to avoid affecting the overall MOSFET switching losses. Hence,
the subsequent stage calculation. Table 3 shows up the stage names, multiple ceramic capacitors (480 nF, 600 V), Cbp , are parallel to
main events and stop conditions regarding each subintervals. further reduce the equivalent stray inductance (these are placed on
It is important to mention that during the subintervals where the the bottom layer of the board). High-bandwidth passive probes (500
drain-source voltage changes abruptly (i.e. high dv/dt occurrences), MHz) have been used to sense vDS and vGS , respectively. The gating
namely the stages 3 and 5, it is required to discretize the parasitic scheme was implemented digitally by means of an FPGA module.
capacitances Ciss , Coss and Crss . Those voltage quick transitions In the experiments, the tested devices were of the brands IRF840,
take place because of the nonlinear nature of the capacitances. Hence, FQH8N100C and SCT3120AL, whose main parameters are presented
the capacitance discretized values are used to lead the process solution in Table 5. In addition, it is worth mentioning that a deskew procedure
to its stop condition. test was previously performed in the oscilloscope in order to mitigate
the distinct delays concerning iD and vDS waveforms obtained by
different probes.
Table 3 Ahmed method stages Fig. 8 presents some experimental waveforms gathered from the
# Stage Subinterval Stop condition Transition DPT circuit prototype when the DUT was the SiC MOSFET, Vdd =
1. Turn-on delay vGS ≥ Vth 150 V and Idd = 2 A. As will be explained in the following, several
2. Rising of drain current vGS ≥ Vpl Turn-on
3. Falling of drain-source voltage vDS ≤ Vds(on)
voltage and current levels have been used during the tests in order to
4. Turn-off delay vGS ≤ Vpl verify the performance of the switching losses estimation methods
5. Rising of drain-source voltage vDS ≥ Vdd Turn-off over the device operating range. In order to ensure a constant ambient
6. Falling of drain current vGS ≤ Vth temperature, Ta at 25◦ C, which is the temperature that the parameters
7. Ringing (resonance) vGS ≥ Vdr(on) Turn-on and turn-off provided in the datasheet are obtained, the tests were conducted with
the use of a climatic chamber [27], as shown in the experimental setup
depicted in Fig. 9. For the analysis and losses calculation, the data
Upon the complete calculation of all the transition stages, the gathered by the oscilloscope, concerning vDS , vGS and iD signals,
whole turn-on or turn-off solution, i.e., the time behaviours of drain are inserted and processed by a personal computer using MATLAB
current (iD (t)) and drain-to-source voltage (vDS (t)), are obtained routines. A function was created in this software tool aiming the
by merging the correspondent subinterval solutions. Finally, the ener- analysis of the collected data for a specific sample set and to return
gies related to the switching losses, Eon and Eof f , are calculated the desired information regarding the DUT energy losses.
by integrating the result of the multiplication of iD (t) and vDS (t) The instantaneous energy Einst (i) calculation is done by inte-
using the trapezoidal numeric method. grating the instantaneous power p(t). In this work, Einst (i) was

IET Research Journals, pp. 1–9

6
c The Institution of Engineering and Technology 2015
 Cbp MOSFET
Vdd
driver

p(i)

p(i-1)
DUT Einst(i) =
[p(i) - p(i-1)]× t/2
Ds + p(i-1)× t
+ Einst(i-1)
Einst(i-1)
Lb t

Fig. 7: Double-pulse circuit prototype.

Fig. 10: Iterative calculation of accumulated instantaneous energy.

(p(i) + p(i + 1))∆t

Einst (i) = + Einst (i − 1) (30)
2
iD
4.1 Experimental results and discussion
vDS
As already mentioned, in order to compare the three meth-
ods, different manufacturing technologies of power MOSFETs
were chosen for theoretical and experimental evaluation purposes,
vGS which are - a conventional VDMOS Si-MOSFET (IRF840), a SiC-
MOSFET (SCT3120AL) and a planar stripe structure Si-MOSFET
(FQH8N100C).

Table 5 Key parameters of studied Power MOSFETs.

Parameter IRF840 [28] FQH8N100C [29] SCT3120AL [30]
drain-to-source voltage (vDS ) 500 V 1000 V 650 V
Fig. 8: Typical experimental waveforms of a given DUT, showing Drain current (iD ) 8A 8A 21 A
ID , vDS , and vGS signals. Conduction resistance (Rds(on) ) 850 mΩ 1200 mΩ 120 mΩ
Gate-source voltage (vGS ) 20 V 20 V 18 V
Threshold voltage (Vth ) 2−4V 3−5V 2.7 − 5.6 V
Transconductance (gm ) 4.9 S 8S 2.7 S
Rise Time (tr ) 32 ns 200 ns 21 ns
Table 4 Double-pulse circuit prototype parameters. Fall Time (tf ) 22 ns 170 ns 14 ns
Total gate charge (Qsw ) 30 nC 70 nC 38 nC
Parameter Description Value
Lb Inductor DPT 4.67 mH MAGMATEC (MMT052T2711); N=130; AWG21)
Cbp Bypass capacitor 4 x 480 nF/600 V Fig. 11 presents a comparison between experimental and theoret-
DUT Power MOSFETs IRF840, FQH8N100C, SCT3120AL
Ds Schottky Diode C3D16065A ical results for the three devices under different operating voltage
Vdr(on) Driver voltage 18 V conditions and fixed current, i.e., 1 A.. The theoretical results have
Rg Total gate resistance (10 + Rg(int) )Ω been obtained by using the mathematical analysis presented in Section
Vdd Voltage supply 50 – 300 V
3. As can be seen in Fig. 11, the Guo and Brown methods overes-
timate the switching energy loss in all the analyzed cases. These
methods present major errors, mainly in high current and voltage
levels. In some cases, they overestimate losses more than six times
(WKL100) when compared with the experimental results. The results showed
WEISS Climatic Chamber that as the voltage level increased, the theoretical estimation also
Digital oscilloscope 3001 iX AC Power Supply became higher for all the analyzed devices.
(DPO3014 Tektronix) (California Instruments) The Ahmed method is the one that more closely matches the
experimental results. Furthermore, the best results were found with
Double-pulse circuit the SiC MOSFET, which has the most detailed and well-defined
Current probe (iD) datasheet information among the tested devices. The minimum error
Lb Ds
was of 2.38% (100 V – 1 A) and a maximum error of 28.38% (in the
Passive voltage probe (vGS)
FPGA
Rg condition of 300 V – 1 A), respectively, for the total switching losses
Passive voltage probes (vDS) M
concerning the SiC device. In general, the results suggest that the
consideration of more parasitic elements circuit are very important
and can provide an increased accuracy in switching losses calculation.
Fig. 9: Setup employed in switching losses measurement experi- Fig. 12 compares experimental and theoretical results for the three
ments. devices under different operating current conditions and fixed voltage,
i.e. 250 V. The errors associated with the three methods behave
similarly to those found in Fig. 11. It is important to emphasize
that different values of the gate resistance were tested in the DPT
circuit and the results following the behavior presented in Figs. 11
calculated by using the trapezoidal approximation of a p sample, as and 12. Furthermore, it is worth mentioning that the experimental
shown in (30) and represented in Fig. 10. switching losses during turn-off transient include the losses caused by

IET Research Journals, pp. 1–9

c The Institution of Engineering and Technology 2015 7
 the output capacitance and other parasitic elements. Due to practical 6
limitations, it is unfeasible to deploy measurements of the MOSFET SCT3120AL

Esw/Eexp (%)
Expe rimental
channel current. Hence, this work has being adopted the drain current 4 Brown [9]
Guo [15]
in calculations. The difference between these two currents tends to Ahmed [8]
greatly impact the switching losses calculation. 2
Finally, the three studied methods presented a fast convergence,
which was lower than 1 minute for all cases. Although the method 0
0 1 2 3 4 5 6
proposed by Ahmed [8] present a more complex implementation Current [A]
procedure, it has shown an acceptable convergence time (less than 1 (a)
min ∗ ) and smaller errors compared to the other evaluated techniques. 8

Esw/Eexp (%)
FQH8N100C
6 Expe rimental
Brown [9]
6 Guo [15]
4
Esw /E exp (%)

SCT3120AL Ahmed [8]

Experimental
4 Brown method [9] 2
Guo method [15]
Ahmed method [8]
2 0
0 1 2 3 4 5 6
0 Current [A]
50 100 150 200 250 300 (b)
Voltage [V] 6

Esw/Eexp (%)
(a) IRF840
6 Expe rimental
4
Esw /E exp (%)

FQH8N100C Brown [9]

Experimental Guo [15]
4 Brown method [9]
Ahmed [8]
Guo method [15] 2
Ahmed method [8]
2
0
0 0 1 2 3 4 5 6
50 100 150 200 250 300 Current [A]
Voltage [V] (c)
(b)
6 Fig. 12: Comparison among Brown, Guo and Ahmed methods for
Esw /E exp (%)

IRF840
Experimental
switching losses carried out under different current conditions and
4
Brown method [9] fixed voltage (250 V). (a) SiC (SCTAL650), (b) FQH8N100C, and
Guo method [15]
2 Ahmed method [8] (c) IRF840.

0
50 100 150 200 250 300
MOSFETs, mainly because of the uncertainty related to the datasheet
Voltage [V]
(c) parameters, which are normally obtained for a single operating point
and do not properly describe the entire operating range of the device.
Fig. 11: Comparison among Brown, Guo and Ahmed methods for Among the parameters that most influence the measurements, one
switching losses carried out under different voltage conditions and could list the device threshold voltage and transconductance, as well
fixed current (1 A). (a) SiC (SCTAL650), (b) FQH8N100C, and (c) as the values of parasitic inductances.
IRF840.

5 Conclusion
Technical literature presents numerous methods aimed to predict
switching losses in power MOSFETs. Although Physical modelling-
based and SPICE-based simulations can lead to good results in terms
of accuracy, the simulation time and complexity difficult the consider-
ation of such strategies when designing static converters. On the other
hand, analytical methods are a quicker way to obtain a first insight
regarding the switching losses on MOSFET devices. Within this con-
text, this paper has presented an extensive review of datasheet-based
switching losses prediction methods.
The work showed that inherent errors occur especially when
neglecting parasitic elements, such as drain inductance and source
inductance. As possible solutions, some methods were devised so
that the influence of parasitic inductances are accounted. On the other
hand, some works considered the the non-linear variation of the junc-
tion capacitances according to the drain-to-source voltage. Therefore,
the analysis presented in this paper showed that as the completeness
of the model increases, the switching losses estimation accuracy also
increase at the cost of a higher complexity.
The experimental assessment was carried out in order to evaluate
the and compare these three methods for estimating the switching
losses of three different MOSFET devices under several operating
conditions. The conclusion of the experimental analysis was that
is very difficult do correctly predict the switching losses in power
∗ Intel Core i5 2.3 GHz computer
Acknowledgements
This study was supported in part by the Brazilian funding agencies
CAPES, CNPq and FAPEMIG. Authors would also like to express
gratitude for the financial and technical support of UFJF, INERGE
and the Department of Electrical Engineering.
6 References
1 Mazumder, SK and Jedraszczak, P.: ’Evaluation of a SiC dc/dc converter for plug-in
hybrid-electric-vehicle at high inlet-coolant temperature’, IET power electronics,
2011, 4, pp. 708–714
2 Lidow, A., Strydom, J., De Rooij, M., Reusch, D.: ’GaN transistors for efficient
power conversion’ (John Wiley & Sons, 2014)
3 Wang, Z., Zhang J., Wu, X., Sheng, K.: ’Evaluation of reverse recovery characteristic
of silicon carbide metal–oxide–semiconductor field-effect transistor intrinsic diode’,
IET Power Electronics, 2016, 9, pp. 969–976
4 Paula, W. J, Tavares, P. L, Pereira, D. C, Tavaras, G. M, Almeida, P. S., Braga, H. A.
C.: ’A review on gallium nitride switching power devices and applications’. Proc.
Brazilian Power Electronics Conference (COBEP), Juiz de Fora, Brazil, November
2017, pp. 1–7
5 Wang, J., Chung, H. S., Li, R. T.: ’Characterization and experimental assessment
of the effects of parasitic elements on the MOSFET switching performance’ IEEE
Transactions on Power Electronics, 2013, 28, pp. 573–590
6 Costinett, D.: ’Analysis and Design of High Efficiency, High Conversion Ratio,
DC-DC Power Converters’. PhD thesis, University of Colorado, 2013.
7 Rodríguez, M., Rodríguez, A., Miaja, P. F., Lamar, D. G., Zúniga, J. S.: ’An insight
into the switching process of power MOSFETs: An improved analytical losses
model’, IEEE Transactions on Power Electronics, 2010, 25, pp. 1626–1640
8 Ahmed, M. R., Todd, R. Forsyth, A. J.: ’Predicting SiC MOSFET Behavior Under
Hard-Switching, Soft-Switching, and False Turn-On Condition’, IEEE Transactions
on Industrial Electronics, 2017, 64, pp. 9001–9011
9 Brown, J.: ’Modeling the switching performance of a mosfet in the high side of
non-isolated buck converter’, IEEE Transactions on Power Electronics, 2006, 21,
pp. 3–10

IET Research Journals, pp. 1–9

8
c The Institution of Engineering and Technology 2015
10 Klein, J.: ’Synchronous buck MOSFET loss calculations with Excel model’,
Fairchild Semiconductor Application Notes AN-6005, 2006.
11 Meade, T., O’Sullivan, D., Foley, R., Achimescu, C., Egan, M., McCloskey, P.: ’Par-
asitic inductance effect on switching losses for a high frequency Dc-Dc converter’.
Proc. 2008, Austin, Tx, pp. 3–9
12 Eberle, W, Zhang, Z., Liu, Y., Sen, P. C.: ’A practical switching loss model for buck
voltage regulators’.IEEE Transactions on Power Electronics, 2009, 24, pp. 700–713
13 Baliga, B. J.: ’Fundamentals of power semiconductor devices’(Springer Science &
Business Media, 2006)
14 Graovac, D., Purschel, M., Kiep, A.: ’MOSFET power losses calculation using the
datasheet parameters’ Infineon application note, 2006
15 Guo J. Ge, H., Jin ye, Emadi, A.: ’Improved method for MOSFET voltage rise-
time and fall-time estimation in inverter switching loss calculation’. Proc. IEEE
Transportation Electrification Conference and Expo (ITEC)’, June 2015.
16 Ren, Y., Xu, M., Zhow, J., Lee, F. C.: ’Analytical loss model of power MOSFET’,
IEEE transactions on power electronics, 2006, 21, pp. 310–319
17 Li, X., Jiang, J., Huang, A. Q., Suxuan, D., Deng, X., Zhang, B., She, x.: ’A
SiC power MOSFET loss model suitable for high-frequency applications’ IEEE
Transactions on Industrial Electronics, 2017, 64, pp. 8268-8276
18 Pam, S. Sheeham, R., Mukhopadhyay, S.:’Accurate loss model for DC-DC buck
converter including non-linear driver output characteristics’. Proc. Twenty-Seventh
Annual IEEE Applied Power Electronics Conference and Exposition (APEC),
Orlando, Eua, March 2012, pp. 721–726
19 orabi, M. Shawky, A.: ’Proposed switching losses model for integrated point-of-load
synchronous buck converters’, IEEE Transactions on Power Electronics, 2014, 30,
pp. 5136–5150
20 Pathak, A. D.: ’MOSFET/IGBT drivers theory and applications’, AN002, 2001.
21 Shah, K., Shenai, K.: ’Simple and accurate circuit simulation model for gal-
lium nitride power transistors’, IEEE Transactions on Electron Devices, 2012,
59, pp. 2735–2741
22 Consentino, G., Ardita, G.: ’A simplified and approximate power MOSFET intrinsic
capacitance simulation: theoretical studies, measures and comparisons’. Proc. IEEE
International Symposium on Industrial Electronics, Cambridge, UK, November
2008, pp. 38-47
23 Aubard, L., Verneau, G., Crebier, J., Schaeffer, C., Avenas, Y.:’Power MOSFET
switching waveforms: an empirical model based on a physical analysis of charge
locations’. Proc. IEEE 33rd Annual Power Electronics Specialists Conference,
Cairns, Australia, November 2002, pp. 1305–1310
24 Karnoven, A. Thiriger, T.: ’MOSFET modeling adapted for switched applications
using a state-space approach and internal capacitance characterization’. Proc. Inter-
national Conference on Power Electronics and Drive Systems, Taipei, Taiwan,
January 2010, pp.1107–1112
25 Sodhi, R., Brown, S., Kinzer, D.: ’Integrated design environment for DC/DC
converter FET optimization’. Proc. he 11th International Symposium on Power
Semiconductor Devices and ICs, Toronto, Canada, May 1999, pp. 241–244
26 MICROSEMI, C. ’MOSFET datasheet: APTC60BBM24T3G’,
http://bit.do/fmMYh, acessed August 2019
27 WEISS, U., ’WKL-100 datasheet’, http://bit.do/fmMY3, acessed August 2019
28 VISHAY, ’Power MOSFET datasheet: IRF840’, http://bit.do/fmMWwf, acessed
August 2019
29 FAIRCHILD, S. ’Power MOSFET datasheet: FQH8N100C’, http://bit.do/fmMWU,
acessed August 2019
30 ROHM, S. ’Power MOSFET datasheet’, http://bit.do/fmMXr, acessed August 2019

IET Research Journals, pp. 1–9

c The Institution of Engineering and Technology 2015 9