5895

26182.14B*
8-BIT SERIAL-INPUT,
5895

Data Sheet
LATCHED DRIVERS

BiMOS II 8-BIT SERIAL INPUT,

LATCHED SOURCE DRIVERS
The UCN5895A, UCN5895EP, and A5895SLW BiMOS II serial-
UCN5895A input, latched source drivers are designed for applications emphasiz-
ing low output saturation voltages and currents to -250 mA per output.
SERIAL These smart high-side octal, driver ICs merge an 8-bit CMOS shift
GROUND 1 16 DATA OUT register, associated CMOS latches, and CMOS control logic (strobe
CLOCK CLK VDD 15 LOGIC and output enable) with medium current emitter-follower (sourcing)
2 SHIFT SUPPLY
REGISTER
outputs. Typical applications include incandescent or LED displays
OUTPUT
SERIAL 3 OE 14 ENABLE
(both directly driven and multiplexed), non-impact (i.e., thermal)
DATA IN
printers, relays, and solenoids.
LOAD
STROBE 4 ST LATCHES VBB 13
SUPPLY
Each device is suitable for high-side applications to -250 mA per
OUT 1 5 12 OUT 8 channel. The maximum supply voltage is 50 V and a minimum output
sustaining voltage rating of 35 V for inductive load applications. Under
OUT 2 6 11 OUT 7
normal operating conditions, the UCN5895A and UCN5895EP are
OUT 3 10 OUT 6
capable of providing -120 mA (8 outputs continuous and simultaneous)
7
at +65°C with a logic supply of 5 V. Similar devices, with higher output
OUT 4 8 9 OUT 5 current ratings, are the UCN5890A and UCN5891A.
BiMOS II devices can operate at greatly improved data-input rates.
Dwg. PP-026-2A With a 5 V supply, they will typically operate at better than 5 MHz.
Note the UCN5895A (DIP) and the A5895SLW At 12 V, significantly higher speeds are obtained.
(SOIC) are electrically identical and share a common
terminal number assignment. The CMOS inputs provide for minimum loading and are compatible
with standard CMOS, PMOS, and NMOS circuits. TTL or DTL circuits
may require the use of appropriate pull-up resistors to ensure a proper
ABSOLUTE MAXIMUM RATINGS input-logic high. A CMOS serial data output allows cascading these
at TA = +25°C devices in multiple drive-line applications required by many dot matrix,
Output Voltage, VOUT . . . . . . . . . . . . . . 50 V alphanumeric, and bar graph displays.
Logic Supply Voltage Range, These devices are rated for continuous operation over the tem-
VDD . . . . . . . . . . . . . . . . . . 4.5 V to 12 V perature range of -20°C to +85°C. Because of limitations on package
Driver Supply Voltage Range, power dissipation, the simultaneous operation of all output drivers may
VBB . . . . . . . . . . . . . . . . . . 5.0 V to 50 V require a reduction in duty cycle. The UCN5895A is supplied in a
Input Voltage Range, standard 16-pin dual in-line plastic package with a copper lead frame
VIN . . . . . . . . . . . -0.3 V to VDD + 0.3 V for increased allowable package power dissipation. The UCN5895EP
Continuous Output Current, is supplied in a 20-lead plastic leaded chip carrier for minimum area,
IOUT . . . . . . . . . . . . . . . . . . . . . -250 mA surface-mount applications. The A5895SLW is supplied in a 16-lead
Allowable Package Power Dissipation, wide-body plastic SOIC.
PD . . . . . . . . . . . . . . . . . . . . See Graph
Operating Temperature Range, FEATURES
TA . . . . . . . . . . . . . . . . . -20 °C to +85°C
■ Low Output-Saturation Voltage
Storage Temperature Range,
■ Source Outputs to 50 V
TS . . . . . . . . . . . . . . . . -55°C to +150°C
■ Output Current to -250 mA
Caution: CMOS devices have input-static ■ To 3.3 MHz Data-lnput Rate
protection, but are susceptible to damage when ■ Low-Power CMOS Logic & Latches
exposed to extremely high static electrical
charges.
Always order by complete part number, e.g., UCN5895A .
 5895
8-BIT SERIAL-INPUT,
LATCHED DRIVERS

FUNCTIONAL BLOCK DIAGRAM

ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS

2.5

SUFFIX 'EP', R θJA = 59°C/W

CLOCK
2.0
SUFFIX 'A', R θJA = 60°C/W SERIAL SERIAL
8-BIT SERIAL-PARALLEL SHIFT REGISTER DATA OUT
DATA IN

1.5
STROBE LATCHES VDD

GROUND OUTPUT
1.0
ENABLE
MOS
BIPOLAR
0.5 VBB

SUFFIX 'LW', R θJA = 80°C/W

0
25 50 75 100 125 150
AMBIENT TEMPERATURE IN °C OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 OUT8
Dwg. GP-024-4 Dwg. No. A-12,654

TYPICAL INPUT CIRCUIT

VDD

IN UCN5895EP

Dwg. EP-010-4A

TYPICAL OUTPUT DRIVER

Dwg. No. A-14,368

Dwg. No. A-12,655

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000
Copyright © 1985, 1999, Allegro MicroSystems, Inc.
 5895
8-BIT SERIAL-INPUT,
LATCHED DRIVERS

ELECTRICAL CHARACTERISTICS at TA = +25°C, VBB = 50 V, VDD = 5 V and 12 V

(unless otherwise noted).
Limits
Characteristic Symbol Test Conditions Min. Max. Units
Output Leakage Current IOUT TA = +25°C — -50 µA
TA = +70°C — -100 µA
Output Saturation Voltage VCE(SAT) IOUT = -60 mA — 1.1 V
IOUT = -120 mA — 1.2 V
Output Sustaining Voltage VCE(sus) IOUT = -120 mA, L = 2 mH 35 — V
Input Voltage VIN(1) VDD = 5.0 V 3.5 5.3 V
VDD = 12 V 10.5 12.3 V
VIN(0) VDD = 5 V to 12 V -0.3 +0.8 V
Input Current IIN(1) VDD = VIN = 5.0 V — 50 µA
VDD = VIN = 12 V — 240 µA
Input lmpedance zIN VDD = 5.0 V 100 — kΩ
VDD = 12 V 50 — kΩ
Max. Clock Frequency fCLK 3.3 — MHz
Serial Data-Output rOUT VDD = 5.0 V — 20 kΩ
Resistance
VDD = 12 V — 6.0 kΩ
Turn-ON Delay tPLH Output Enable to Output, IOUT = -120 mA — 2.0 µs
Turn-OFF Delay tPHL Output Enable to Output, IOUT = -120 mA — 10 µs
Supply Current IBB All outputs ON, All outputs open — 10 mA
All outputs OFF — 200 µA
IDD VDD = 5 V, All outputs OFF, Inputs = 0 V — 100 µA
VDD = 12 V, All outputs OFF, Inputs = 0 V — 200 µA
VDD = 5 V, One output ON, All inputs = 0 V — 1.0 mA
VDD = 12 V, One output ON, All inputs = 0 V — 3.0 mA
Diode Leakage Current IR VR = 25 V, TA = +25°C — 50 µA
VR = 25 V, TA = +70°C — 100 µA
Diode Forward Voltage VF IF = 120 mA — 2.0 V
5895
8-BIT SERIAL-INPUT,
LATCHED DRIVERS

CLOCK
A D
B
DATA IN
E F
C
STROBE

BLANKING
G

OUTN

Dwg. No. A-12,649A

TIMING CONDITIONS
(VDD = 5.0 V, Logic Levels are VDD and Ground)

A. Minimum Data Active Time Before Clock Pulse

(Data Set-Up Time) ................................................................. 75 ns
B. Minimum Data Active Time After Clock Pulse
(Data Hold Time) ..................................................................... 75 ns
C. Minimum Data Pulse Width ........................................................ 150 ns
D. Minimum Clock Pulse Width ...................................................... 150 ns
E. Minimum Time Between Clock Activation and Strobe ............... 300 ns
F. Minimum Strobe Pulse Width ..................................................... 100 ns
G. Typical Time Between Strobe Activation and
Output Transition .................................................................... 1.0 µs
Serial Data present at the input is transferred to the shift register
on the logic “0” to logic “1” transition of the CLOCK input pulse. On
succeeding CLOCK pulses, the registers shift data information towards
the SERIAL DATA OUTPUT. The SERIAL DATA must appear at the
input prior to the rising edge of the CLOCK input waveform.

Information present at any register is transferred to its respective

latch when the STROBE is high (serial-to-parallel conversion). The
latches will continue to accept new data as long as the STROBE is
held high. Applications where the latches are bypassed (STROBE tied
high) will require that the OUTPUT ENABLE input be high during serial
data entry.

When the OUTPUT ENABLE input is high, all of the output buffers
are disabled (OFF) without affecting the information stored in the
latches or shift register. With the OUTPUT ENABLE input low, the
outputs are controlled by the state of their respective latches.

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000
5895
8-BIT SERIAL-INPUT,
LATCHED DRIVERS

TYPICAL APPLICATION
+ 12 V
UCN5895A
DATA OUT
1 16 FOR > 8 SEGMENTS
PER DIGIT

CLOCK 2 SHIFT VDD 15

REGISTER
DATA IN 3 OE 14 OUTPUT ENABLE
(ACTIVE LOW)

STROBE 4 LATCHES VBB 13

5 12

6 11

7 10
8 9

TO OTHER SEGMENTS
UCN5821A
CLOCK 1 C 16
DATA IN 2 15

3 14
SHIFT REGISTER

TO
+ 12 V 4 13 OTHER
LATCHES

DIGITS
DATA OUT 5 12

STROBE 6 11
OUTPUT 7 10
ENABLE
8 99

Dwg. No. B-1541

TRUTH TABLE
Serial Shift Register Contents Serial Latch Contents Output Contents
Data Clock Data Strobe Output
Input Input I1 I2 I3 ... IN-1 IN Output Input I1 I2 I3 ... IN-1 IN Enable I1 I2 I3 ... IN-1 I N

H H R1 R2 ... RN-2 RN-1 RN-1

L L R1 R2 ... RN-2 RN-1 RN-1
X R1 R2 R3 ... RN-1 RN RN
X X X ... X X X L R1 R2 R3 ... RN-1 RN
P1 P2 P3 ... PN-1 PN PN H P1 P2 P3 ... PN-1 PN L P1 P2 P3 ... PN-1 PN
X X X ... X X H L L L ... L L

L = Low Logic Level H = High Logic Level X = Irrelevant P = Present State R = Previous State
 5895
8-BIT SERIAL-INPUT,
LATCHED DRIVERS

UCN5895A
Dimensions in Inches
(controlling dimensions)
0.014
0.008
16 9

0.430
MAX
0.280
0.240 0.300
BSC

1 8
0.070 0.100 0.005
0.045 BSC MIN
0.775
0.735

0.210
MAX

0.015 0.150
MIN 0.115

0.022
0.014 Dwg. MA-001-16A in

Dimensions in Millimeters
(for reference only)
0.355
0.204
16 9

10.92
MAX
7.11
6.10 7.62
BSC

1 8
1.77 2.54 0.13
1.15 BSC MIN
19.68
18.67

5.33
MAX

0.39 3.81
MIN 2.93

0.558
0.356 Dwg. MA-001-16A mm

NOTES: 1. Lead thickness is measured at seating plane or below.

2. Lead spacing tolerance is non-cumulative.
3. Exact body and lead configuration at vendor’s option within limits shown.

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000
 5895
8-BIT SERIAL-INPUT,
LATCHED DRIVERS

UCN5895EP
Dimensions in Inches
(controlling dimensions)
13 9

0.021
0.013
14 8
0.169
0.141 0.395 0.032
0.385 0.026
INDEX AREA

0.356
0.350
0.050
BSC
0.169 18 4
0.141

19 20 1 2 3

0.020 0.356
MIN 0.350
0.180 0.395
0.165 0.385
Dwg. MA-005-20A in

Dimensions in Millimeters
(for reference only)
13 9

0.533
0.331
14 8
4.29
3.58 10.03 0.812
9.78 0.661
INDEX AREA

9.042
8.890
1.27
BSC
4.29 18 4
3.58

19 20 1 2 3

0.51 9.042
MIN 8.890
4.57 10.03
4.20 9.78
Dwg. MA-005-20A mm

NOTES: 1. Lead spacing tolerance is non-cumulative.

2. Exact body and lead configuration at vendor’s option within limits shown.
 5895
8-BIT SERIAL-INPUT,
LATCHED DRIVERS

A5895SLW
Dimensions in Inches
(for reference only)
16 9
0.0125
0.0091

0.2992 0.419
0.2914 0.394

0.050
0.016

0.020 1 2 3 0.050
0.013 0.4133 BSC 0° TO 8°
0.3977

0.0926
0.1043

0.0040 MIN. Dwg. MA-008-16A in

Dimensions in Millimeters
(controlling dimensions)
16 9
0.32
0.23

7.60 10.65
7.40 10.00

1.27
0.40

0.51 1 2 3 1.27
0.33 10.50 BSC 0° TO 8°
10.10

2.65
2.35 Allegro MicroSystems, Inc. reserves the right to make, from time to time,
such departures from the detail specifications as may be required to permit
0.10 MIN. improvements in the design of its products.
Dwg. MA-008-16A mm
The information included herein is believed to be accurate and reliable.
NOTES: 1. Lead spacing tolerance is non-cumulative. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor
2. Exact body and lead configuration at vendor’s option for any infringements of patents or other rights of third parties which may result
from its use.
within limits shown.

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000