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A Three-Phase Line-Interactive UPS System Implementation with Series-Parallel

Active Power-Line Conditioning Capabilities


S. A. Oliveira da Silva P. Donoso-Garcia, P. C. Cortizo, P. F. Seixas
Centro Federal de Educação Tecnológica – CEFET-PR Universidade Federal de Minas Gerais - UFMG
Department of Electrical Engineering Department of Electronic Engineering
Av. Alberto Carazzai, 1640 EE.UFMG-DELT – Av. Antônio Carlos, 6627
Cornélio Procópio – PR – CEP. 86.300-000 – BRASIL Belo Horizonte – MG – CEP. 31.270-901 – BRASIL
Fax: +55.43.524.4040 – e-mail: augus@cpdee.ufmg.br Fax: +55.31.3499.5480 – e-mail: pedro@cpdee.ufmg.br

Abstract-This paper presents a three-phase line-interactive Operation of a three-phase phase-locked loop (PLL)
uninterruptible power supply (UPS) system with series-parallel structure, used in the line-interactive UPS implementation, is
active power-line conditioning capabilities, using synchronous presented and experimentally tested under distorted utility
reference frame (SRF) based controller, which allows an conditions. The control algorithm using SRF method and the
effective power factor correction, load harmonic current
active power flow through the UPS system are described and
suppression and output voltage regulation. The three-phase UPS
system is composed by two active power filter topologies. The analytically studied. Design procedures, digital simulations
first one is a series active power filter, which works as a and experimental results for a prototype are presented to
sinusoidal current source in phase with the input voltage. The verify the good performance of the proposed three-phase
other is a parallel active power filter, which works as a line-interactive UPS system.
sinusoidal voltage source in phase with the input voltage,
providing to the load a regulated and sinusoidal voltage with II. OPERATION OF THE LINE-INTERACTIVE UPS TOPOLOGY
low total harmonic distortion (THD). Operation of a three-phase
phase-locked loop (PLL) structure, used in the proposed line- The topology of the line-interactive UPS system is shown
interactive UPS implementation, is presented and
in Fig. 1. Two PWM converters, coupled to a common dc
experimentally verified under distorted utility conditions. The
control algorithm using SRF method and the active power flow bus, are used to perform the series active filter and the
through the UPS system are described and analytically studied. parallel active filter functions. A battery bank is placed in the
Design procedures, digital simulations and experimental results dc bus and a static switch ‘sw’ is used to provide a fast
for a prototype are presented to verify the good performance of disconnection between the UPS system and the power supply
the proposed three-phase line-interactive UPS system. when an occasional interruption of the incoming power
occurs.
I. INTRODUCTION
A control algorithm using synchronous reference frame
To improve the power source quality, UPS systems have based controllers is used to control the series PWM converter
been employed, providing clean and uninterruptible power to making the three-phase line currents ( i sa , i sb , i sc ) sinusoidal
critical loads such as, computers, medical equipment, etc, and balanced.
against power supply disturbances [1-7]. In [6, 7] three-phase The parallel PWM converter is controlled to acts as a
parallel processing UPS have been presented with harmonic
sinusoidal voltage source. The output UPS voltages v fa ,
and reactive compensation, but the output voltages and the
input currents can not be controlled simultaneously. Three- v fb and v fc are controlled to be in phase with respect to the
phase UPS systems with series-parallel active power-line input voltages v sa , v sb and v sc , respectively.
conditioning have been proposed using different control
strategies [1-3]. In [1, 2], two different approaches to control
three-phase UPS systems using synchronous reference frame
(SRF) based controllers were proposed, but only simulations
results were presented.
This paper presents experimental results for a three-phase
line-interactive UPS system with series-parallel active power-
line conditioning using SRF based controller. The series
active power filter acts as a sinusoidal current source and the
parallel active power filter acts as a sinusoidal voltage source
[2]. In this line-interactive UPS system, an effective power
factor correction is carried out. The output voltages are
controlled to have constant rms values and low total
harmonic distortion (THD) and the source currents are
controlled to be sinusoidal quantities with low THD, too. Fig. 1. Line-interactive UPS System Topology.

0-7803-7116-X/01/$10.00 (C) 2001 IEEE


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III. SYNCHRONOUS REFERENCE FRAME AND STATE the dc bus voltage is controlled, the UPS dc bus controller
FEEDBACK CONTROLLERS must be able to control the dc bus current too. The dc bus
controller is responsible by the control of the power flow
A. Current SRF Controller (Standby Mode)
through the UPS system. Its output is added to the active
The block diagram of the control scheme for current e
current in the d axis id dc , and thus the amplitude of the input
compensation is shown in Fig. 2. The control algorithm
should be developed to provide, by software, the currents is controlled as shown in Fig. 2.

compensating reference currents ( i ∗ , i∗ , i∗ ) for the series


ca cb cc
id s   1 −1 2 − 1 2  i La 
 s 2
active filter. The three-phase uncompensated currents iq  =  0 3 2 − 3 2 i Lb  (4)
( iLa , i Lb , i Lc ) are measured and transformed into two-phase i  3
1 2 1 2 1 2  i Lc 
 o 
stationary reference frame (dq)s quantities ( id s , iq s ). Then,
i ∗   s 
these quantities are transformed from the two-phase  ca 
 1 0 1 2  id f 
stationary reference frame (dq)s into a two-phase ∗ = 2 
i cb − 1 2 3 2 1 2  iq sf  (5)
synchronous rotating reference frame (dq)e, based on the ∗ 3  
i cc  −1 2 − 3 2 1 2   io 
transformation (1), where θ = ω.t, is the angular position of     
the reference frame. The inverse transformation matrix from
two-phase synchronous reference frame to two-phase B. State Feedback Current Controller (Standby Mode)
stationary reference frame is given by (2). The components of The single-phase block diagram of the current controller is
the unit vector sinθ and cosθ are obtained from a PLL system shown in Fig. 3. The load currents ( i L a,b,c ) are measured
that will be discussed in the next section.
The current at the fundamental frequency ω is now a dc and from the current SRF controller the sinusoidal current
value and all the harmonics are transformed into non-dc references ( i c∗a ,b,c ) are obtained. From Fig. 3, the closed loop
quantities and can be filtered using a low pass filter (LPF) as
e e transfer function i c ( s ) / i c∗ ( s ) is found as (6) and the output
shown in Fig. 2. Now, id dc and iq dc represent the
dynamic stiffness is given by (7), which shows the effect of
fundamental active and reactive component of the load
the difference between the output voltage v f and input
currents, respectively, both in dq axis. In this line-interactive
UPS system implementation the reactive power will be voltage v s on the compensated input current ic . The
compensated and then, k q is made equal to zero in Fig. 2. difference between the input and output voltages is treated as
The series filter reference currents in the stationary reference a disturbance.
frame is then given by (3). ic (s) K Ps s + K Is
= (6)
id e   cos θ sinθ  id s  i c∗ ( s ) 2
L fs s + ( K Ps + R L fs ) s + K Is
 e=   (1)
iq  − sinθ cos θ   iq s 
v f ( s) − v s (s) L fs s 2 + ( K Ps + R L fs ) s + K Is
=− (7)
id s  cos θ − sinθ  id e  ic (s) s
 s=  
iq   sinθ cos θ   iq e  (2)
The frequency response of equation (6) is shown in Fig. 4
(a) and (b). At the power system frequency (w = 377 rad/s),
id s  cos θ − sinθ  id ce  the gain of the system transfer function is about 0 dB and the
 f =   (3)
iq s   sinθ cos θ   0  phase shift is nearly zero degree. The bandwidth of the
 f  system is about 1600 Hz. Fig. 5 shows the dynamic stiffness
of the system. It is noted that the series active filter has high
Thereby, the dc components of the synchronous reference
impedance in a large range of the frequency spectrum.
e e
frame id dc and iq dc are transformed into the stationary
s
reference frame (dq) and yields all fundamental components
of the input uncompensated ac currents. The matrices that
provide the linear transformation from three-phase system to
two-phase stationary reference frame system and from two-
phase system to three-phase stationary reference frame
system are given by equations (4) and (5), respectively. An
additional dc bus controller is responsible for regulating the
current I dc and the voltage V dc . Different from the
conventional active power filter applications, in which only Fig. 2. Block diagram of the current SRF based Controller.

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From Fig. 6, the closed loop transfer function
v f ( s) / v ∗f ( s) is found as (8) and the output dynamic
stiffness is given by (9), which shows the effect of the
difference between the load current i L and the compensated
input current i s on the regulated output voltage v f . The
difference between the load current and the compensated
input current is treated as a disturbance.
Fig. 3. Single-Phase Current Controller of the Series Active Filter.
v f ( s) X 1s 2 + X 2 s + X 3
= (8)
v *f ( s ) Y1 s 3 + Y2 s 2 + Y3 s + Y4

i L (s) − i s (s) Y s 3 + Y2 s 2 + Y3 s + Y4
=− 1 (9)
v f (s) Z1s 2 + Z 2 s

X1 = Cˆ fp .K Pi Y1 = L fp .C fp Z1 = L fp 

X 2 = K pv .K Pi Y2 = C fp .( K Pi + RLfp ) Z 2 = RLfp  (10)
X 3 = Y4 = K Iv .K Pi Y3 = K pv .K Pi + 1 


The frequency response of equation (8) is shown in Fig. 7


(a) and (b). At the power system frequency (w = 377 rad/s),
the gain of the system transfer function is about 0 dB and the
Fig. 4. Frequency Response of the Series Active Filter ic ( s) / ic∗ ( s ) :
phase shift is nearly zero degree. The bandwidth of the
(a) Amplitude Response, (b) Phase Response.
system is about 6000 Hz. Fig. 8 shows the dynamic stiffness
of the system. It is noted that the parallel active filter has low
impedance in a large range of the frequency spectrum.

Fig. 6. Single-Phase Voltage Controller of the Parallel Active Filter.

Fig. 5. Dynamic Stiffness of the Current Controller (v f ( s) − vs ( s )) / ic ( s) :


Amplitude response.

C. State Feedback Voltage Controller (Standby and Backup Mode)


The parallel active filter is responsible by the control of the
output voltages. Thus, the output voltages must have constant
rms values with low THD and will be controlled to be in
phase with the input voltages. As the control algorithm for
input current compensation, the reference voltages ( v ∗ ) fa,b,c
are generated by software using a PLL system. The single-
phase block diagram of the voltage controller is shown in
Fig. 6, in which a classical PI controller with inner current Fig. 7. Frequency Response of the Parallel Active Filter v f ( s) / v ∗f ( s ) :
loop and outer voltage loop is used. (a) Amplitude Response, (b) Phase Response.

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Fig. 9. Three-Phase PLL Control Diagram.

p ' = V ab
' ' ' '
i sa + Vcb i sc . (14)
Fig. 8. Dynamic Stiffness of the Current Controller (iL ( s) − is ( s)) / v f ( s) :
Amplitude Response. '
V ab = k1 sin(θ + 30 o ) 

IV. THE THREE-PHASE PLL SYSTEM Vcb'
= k1 sin(θ + 90 o ) 
 (15)
The three-phase PLL structure implemented in this work is
'
i sa = k 2 sin(θ ∗ ) 
shown in Fig. 9. It is completely implemented in software. '
i sc = k 2 sin(θ ∗ + 120 o )
The input signals of the PLL system are the sampled
voltages v sa , v sb and v sc . The principle of operation of the To annul the dc component of p ' , PLL system will set the
' output of the integrating element as
presented PLL structure is to annul the dc component p dc of
the instantaneous power p ' (Fig. 9). The dynamic of the PLL θ ∗ = θ ' + 90 o . (16)
system will set the output of the PI controller to the angular
The error between the utility angle θ and the PLL angle
frequency reference w ∗ = 2.π . f , where f is the utility '
θ is given by (17). Then, substituting the equations (15),
frequency. The angle θ ∗ = w ∗ .t is obtained by integration of (16) and (17) in (14), the power p ' can be found as (18). As

the frequency reference w that will be identical to the utility constant k varies when either input voltages or input currents
frequency w. Thus, the angle θ ∗ is used to calculate the change, it is assumed in the PLL model to be equal to one.
' '
feedback signals i sa and i sc that will be orthogonal to the ∆θ = θ − θ ' (17)
sampled voltages v sa and v sc , respectively, such that the dc
p ' = k .sin(∆θ ) (18)
component of p ' is annulled.
Thus, the simplified PLL model shown in Fig. 10 can
A. Control Model of the Three-Phase PLL System replace the PLL control diagram shown in Fig. 9. For small
The instantaneous input power of the power system is values of ∆θ , the term sin(∆θ ) behaves linearly [8], that is,
found as sin(∆θ ) ≈ ∆θ .
p = v sa i sa + v sb i sb + v sc i sc = p dc + p ac . (11) The open loop transfer function G oL is found as (19),
which accounts for the sampling time Ts that introduces a
Assuming that the sum of the input currents i sa , i sb and
lag in the forward path of the PLL model. As it contains a
i sc is equal to zero, equation (11) can be found as double integration, a standard design procedure called
“symmetrical optimum” method is used to determine the PI
p = (v sa − v sb )i sa + (v sc − v sb )i sc = V ab i sa + Vcb i sc (12)
controller gains [9]. This method consists in choosing the
where crossover frequency wc at the geometric mean of the two
Vab = 3Vm sin(θ + 30o ) corner frequencies of G oL . The magnitude and the phase plot
. (13)
Vcb = 3Vm sin(θ + 90o )  of G oL should be symmetrical with respect to the crossover
frequency.
Thus, from Fig. 9, the PLL instantaneous power p ' is
sK Ppll + K Ipll
'
given by (14), where the quantities Vab '
, Vcb '
, i sa '
and i sc GoL = (19)
s 3τ s + s 2
are given by (15).

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Fig. 10. Control Model of the Three-Phase PLL.

Therefore, using the “symmetrical optimum” method


discussed above and from (19), equations (20) and (21) are
found, where δ is a normalizing factor. Thus, from (19),
(20) and (21) the proportional gain can be selected by (22).
Fig. 11. PLL Instantaneous Power p ' .
1 K Ipll 1 
wc = , δ wc =  (20)
δ K Ppll τ s 

G oL ( jwc ) = 1 
(21)
G oL ( jwc ) dB = 20 log G oL ( jwc ) s = jw = 0
c 
wc
K Ppll =
k (22)
The closed loop transfer function G cL is given by (23) and
its poles are found by (24).

wc2 δ ( s + wc / δ )
G cL = (23)
( s + wc )( s 2 + wc (δ − 1) s + wc2 ) Fig. 12. PLL Frequency w* .

 2 
 δ −1  δ − 1  
s1 = − wc , s 2 ,3 = wc  −   ± j 1−    (24)
  2   2  
 
Hence, the relationship between damping ratio ς and the
factor δ is
δ = 2ς + 1 . (25)
Thereby, with an adequate choice of the damping ratio ς
and from equations (20), (22) and (25), it is possible to select
the appropriate PI controller gains.
In Table I are shown the parameters and the controller
gains used in the PLL simulation and experimentation. In Fig. 13. Input Sampled voltage vsa and PLL Voltage v pll .
Figs. 11 and 12 the experimental results and the model
simulation results of the three-phase PLL system are shown.
V. ACTIVE POWER FLOW OF THE THREE-PHASE UPS SYSTEM
Fig. 11 and 12 show the PLL instantaneous power p’ and
PLL frequency w*, respectively. In Fig. 13 the distorted input Active power flow of the UPS system is shown in Fig. 14.
voltage v sa and the clean PLL voltage v pll are shown. The direction of the power flow can ever change because the
amplitude of the input voltages is variable.
TABLE I
PARAMETERS AND CONTROLLER GAINS Both the apparent powers S s and S p handled respectively
Factor δ 35 by the series and by the parallel converters, depend of the
Sampling Time ( Ts ) 200µs ratio between the output and input rms voltages ( V f V s ),
Crossover Frequency ( wc ) 898 rad/s
the displacement factor ( cosφ1 ) and the THD of the load
Proportional gain ( K Ppll ) 898
current i L ( THDiL ). In steady state, assuming a balanced
Integral gain ( K Ipll ) 23021 s −1 sinusoidal system, the normalized powers handled by the

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parallel converter | S p S L | and by the series converter
| S s S L | are given by equations (26) and (27), respectively.
The quantities S L , PL , Q L and H L are the apparent,
active, reactive and harmonic powers of the load,
respectively.
In Fig. 15 (a) and (b) the normalized powers handled by
the parallel converter | S p S L | and by the series converter
| S s S L | are plotted for two different displacement factors.
These curves can be used to design the converters.
2 2
 Vf   Vf 
PL2 1 − 
 cos φ 1 1 − 

Ss  Vs   Vs  (26)
= =
SL PL2 + QL2 + H L2 1 + TDH i2L

Vf Vf 
cos2 φ1 
 − 2  (27)
Sp Vs  Vs  +1
=
SL 1 + TDH i2L
If the charging of the batteries is taking into account,
additional active power Pb , given by (28), must be included
in the analysis. Thus, equations (29) and (30) replace (26)
and (27), respectively, where the charging factor k b ≥ 0 . Fig. 15. Normalized Powers: (a) Parallel Converter | S p S L |, (b) Series
Converter | S s S L |.
P = PL + Pb = PL + k b PL (28)

2 2
Vf 
2 
  Vf 
P 1 −  cos φ 1 (1 + kb ) 1 − 


Ss  Vs    Vs  (29)
= =
SL PL2 + QL2 + H L2 1 + TDH i2L

Vf Vf 
cos2 φ1 (1 + kb )  (1 + kb ) − 2 
Sp Vs  Vs  +1 (30)
=
SL 1 + TDHi2L
The plots of the normalized powers for two different
values of k b are shown in Fig. 16 (a) and (b). Depending of
the k b value and the input voltage deviation from the desired
output voltage, the batteries charging can be realized either
from the series or parallel PWM converters or from both.

Fig. 16. Normalized Powers for kb = 0 and kb = 0.1 ( cos φ1 = 1 ):


Fig. 14. Power Flow of the UPS System: (a) Vs > V f , (b) V f > Vs . (a) Parallel Converter | S p S L |, (b) Series Converter | S s S L |.

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VI. EXPERIMENTAL RESULTS output voltages ( v fa,b,c ) are almost sinusoidal with constant
The complete scheme of the three-phase line-interactive rms values and low THD v voltage.
UPS system is shown in Fig. 17. To verify the performance Fig. 18 (c) shows the phase ‘a’ input current isa and the
of the UPS system, a prototype was developed and tested. A input voltage vsa . It is noted that a high power factor is
2.5 kVA non linear load ( THDiL ≅ 30%) used to test the UPS obtained. Figs. 18 (d) shows the phase ‘a’ compensated
system is a there-phase diode rectifier. The parameters used current isa and the output voltage v fa , respectively. The
in the prototype are: L fp =300µH, L fs =1.4mH, C fp =130µF;
quantities v sa,b,c and i sa,b,c are controlled to be in phase
Rdc =30 Ω; Cdc =2200µF, nominal rms line-to-neutral output
with respect to v fa,b,c . The UPS stabilization capability of
voltages - V fa,b,c =115V and dc bus voltage - Vdc =570V.
the output voltage is shown in Figs. 18 (e) and (f).
The part of the scheme shown in the shaded area uses a In Fig. 18 (g) shows phase ‘c’ uncompensated current i Lc ,
400MHz PC computer, a 12 bits resolution data acquisition
system and a 12 bits resolution D/A converter board. Both parallel compensation current i cc p and compensated source
current SRF controller (Fig. 6) and PLL scheme (Fig. 2) are current i sc . It is noted the presence of a fundamental
implemented in software and are responsible to generate the component in ica p that is responsible by charging of the
current and voltage references for the current and voltage
analog controls. Both data acquisition systems and digital battery bank. Figs. 18 (h) and (i) show the output voltage v fa
controllers run at 5kHz frequency. and the uncompensated current iLa (load current), for the
The output voltages ( v fa,b,c ) and source currents ( i sa,b,c )
transition from standby to backup mode (0.1 s) and from
are shown in Figs.18 (a) and (b), respectively. The source backup to standby mode (0.586 s), obtained from data
currents i sa,b,c are almost sinusoidal and balanced. The acquisition software.

Fig. 17. Complete scheme of the Line-Interactive Series-Parallel UPS System.

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(a) (b) (c)

(d) (e) (f)

(g) (h) (i)


Fig. 18. (a) Output Voltages, (b) Input Currents, (c) Input Voltage and Current, (d) Output Voltage Current, (e) Boost Action - Input and Output Voltages,
(f) Buck Action - Input and Output Voltages (g) Currents i sc , i cc and i Lc , (h) Standby-Backup Transition Mode, (i) Backup-Standby Transition Mode.
p

VII. CONCLUSIONS REFERENCES


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