A B C D E

LCFC confidential File Name : ACLUA

NV (N15V-GM/N15S-GT)
GB2B-64 Package PCI-Express
Page 18~28 PCIe Port5
4x Gen2 Memory BUS (DDR3L)
Dual Channel DDR3L-SO-DIMM X2
Page 14,15
VRAM 256/128*16
1
1.35V DDR3L 1600 MT/s 1

DDR3L*8 4GB/2GB/1GB UP TO 8G x 2
Page 24~27

HDMI USB Left

HDMI Conn.
Page 34 USB 3.0 1x
USB 3.0 Port1
USB 2.0 Port1
DP to VGA DPx2 Lane USB 2.0 2x
VGA Conn.
Page 36 Page 35 Parade PS8613 Intel MCP USB 2.0 Port2
Page 41

l
eDP x2 Lane
eDP Conn

tia
USB 2.0 1x Touch Screen
USB2.0 1x
Int. Camera Page 33 USB2.0 Port4
USB2.0 Port5

2
Haswell U 15W / 2

Int. MIC Conn. Broadwell U 15W

en
Page 33
USB2.0 1x USB Right
USB2.0 Port0
SATA HDD SATA Gen3
Page 42 SATA Port0 USB2.0 1x
BGA-1168 Cardreader Realtek SD/MMC Conn.
40mm*24mm RTS5170 USB2.0 Port3

fid
SATA ODD SATA Gen1 USB Board
Page 42 SATA Port1

USB 2.0 1x
LAN Realtek NGFF Card
RJ45 Conn. PCIe 1x PCIe 1x WLAN&BT
Page 38
RTL8111GUL (1G) PCIe Port4

3
RTL8106EUL (10M/100M)
Page 37 PCIe Port3
on Page 40 USB2.0 Port6

Sub-board ( for 14")

3

HD Audio SPI BUS SPI ROM

Page 3~13
8MB Page 07 POWER BOARD

Codec SPI ROM 4MB USB Board

SPK Conn. for reserve
C
Conexant CX20752 Page 07
Page 43
Page 43

EC
ITE IT8586E-LQFP Sub-board ( for 15")
Page 44

HP&Mic Combo Conn. POWER BOARD

USB Board USB Board

Touch Pad Int.KBD Thermal Sensor
4 Page 45 Page 45 NCT7718W 4
Page 39
ODD Board

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 Block Diagram
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. ACLUA
Date: Thursday, December 26, 2013 Sheet 2 of 59
A B C D E

PDF created with pdfFactory Pro trial version www.pdffactory.com

 5 4 3 2 1

B2 A2
D
+3VLP PCH_PWR_EN# 2 D

Q25,+3V_PCH

V
V
AC A1
MODE VIN

V V
A2 A4 B5
3

V
PU301 PU904 +3V_PCH

V
B+
+3VALW
BATT BATT V 1
DPWROK_EC
V
MODE

V V V
B1
4
PCH_RSMRST#
EC 14
PM_DRAM_PWRGD
5 PBTN_OUT#

V
l
EC_ON PM_SLP_S3# PCH 15
PM_SLP_S4# H_CPUPWRGD CPU

tia
V V
A3 B4 PM_SLP_S5#
PM_SLP_SUS# 6

V
CPU_PLTRST# 16
12
PCH_PWROK

V V
C C

B3 13
SYS_PWROK

V
ON/OFF

en
V
NOVO

NVDD_PWR_EN
(DIS)
Vb
+VGA_CORE

V
11 VR_REDY SYSON 7 +1.35V
PU801

V
PU501

fid
DGPU_PWROK
DGPU_PWR_EN
10 Va (DIS)

V
PU901 VR_ON +1.5VS_VGA

V
Q31
V

PU601

V
+CPU_CORE
+5VS

B
on B

V
Q32 +1.05VSP_VGA

V
SUSP#,SUSP 9 +3VS PU702

V
VGA

V
PU602
+1.5VS +3VS_VGA

V
Q27
C

V
PU502
+0.675V
8
SUS_VCCP PU701
V
+1.05VS

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 Power sequence Block

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. ACLUA
Date: Thursday, December 26, 2013 Sheet 47 of 59
5 4 3 2 1

PDF created with pdfFactory Pro trial version www.pdffactory.com

 5 4 3 2 1

B+
+5VLP/ 100mA
Silergy
D
Silergy D

SY8208CQNC +5VALW/5A SY8868QMC

Adaptor Converter QFN10_2X2 +1.05VS/5A
FOR SYSTEM Switch Mode
EC_ON EN PGOOD ALW_PWRGD FOR VDDR
PAGE 39
SUSP# EN PGOOD

+3VLP/ 100mA
Silergy
SY8206BQNC ANPEC
Converter +3VALW/4A

FOR SYSTEM APL5930KAI-TRG_SO8 +1.5VSP/1A

EC_ON EN PGOOD ALW_PWRGD
PAGE 39 LDO
FOR VDDR

l
SUSP# EN PGOOD

tia
TI +1.35V/12A
TPS51716RUKR
SYSON S5 WQFN20_3X3 Silergy
C SUSP# S3 +0.675VS/2A C
TI Switch Mode SY8032ABC
FOR DDR PGOOD SOT23-6 +1.05VSP_VGA/2A
BQ24737RGRR Switch Mode

en
Battery Charger FOR VDDR
EN PGOOD
Switch Mode
PAGE 46 Onsemi
CPU Core/14A/32A
NCP81101MNTXG
QFN28_4X4
Switch Mode
VR_ON
SMBus EN FOR CPU Core PGOOD VGATE

fid
PGOOD_NB

Battery Onsemi
Li-ion NCP81172MNTWG
B

4S1P/41WH
VIDs
QFN24_4X4
on +VGA_CORE/31A
B

Switch Mode
NVDD_PWR_EN EN FOR GPU VDDC PGOOD VGA_PWRGD
C

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 Power Diagram
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OFSize
R&D Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. ACLUA
Date: Thursday, December 26, 2013 Sheet 50 of 59
5 4 3 2 1

PDF created with pdfFactory Pro trial version www.pdffactory.com

 A B C D E

LCFC confidential File Name : ACLU9

NV (N15V-GM/N15S-GT)
GB2B-64 Package PCI-Express Memory BUS (DDR3L)
Page 18~28 PCIe Port5 Dual Channel DDR3L-SO-DIMM
2x Gen2 Page 14

VRAM 256/128*16 1.35V DDR3L 1333 MT/s

UP TO 8G
DDR3L*8 4GB/2GB/1GB
1
Page 19~28 1

USB 3.0 1x USB Left 3.0 Conn

HDMI
HDMI Conn. USB 2.0 1x USB 3.0 Port0
Page 34
USB 2.0 Port0 Page 41

CRT
VGA Conn. Baytrail M (4.5W) USB 2.0 1x USB Left 2.0 Conn
Page 36
USB 2.0 Port3 Page 41
eDP Conn
USB 2.0 1x to Camera
to USB Port Int. Camera
USB2.0 Port2
eDP x2 Lane
Int. MIC Conn. USB Right
USB2.0 1x
USB2.0 Hub Port1
2
Page 33 2

USB2.0 1x Cardreader Realtek

USB 2.0 1x USB Hub SD/MMC Conn.
SATA HDD SATA Gen2 RTS5170USB2.0 Hub Port3
Page 42 SATA Port0 USB Board
BGA-1170
USB2.0 1x Touch Screen
SATA ODD SATA Gen1 25mm*27mm
Page 42 SATA Port1
reserved
USB 2.0 Port2 Page 33
Page 16
USB2.0 1x
USB 2.0 Port1
NGFF Card
LAN Realtek PCIe 1x WLAN&BT
PCIe Port0
RJ45 Conn. PCIe 1x Page 40
RTL8111GUL (1G) USB2.0 Hub Port4
Page 38
RTL8106EUL (10M/100M)
Page 37 PCIe Port1
HD Audio SPI BUS SPI ROM
Page 4~12
8MB Page 07 Sub-board ( for 14")
POWER BOARD
3 3

Codec SPK Conn.

Conexant CX20752 Page 43
Page 43 USB Board
EC
ITE IT8586E-LQFP
Page 44
Sub-board ( for 15")
HP&Mic Combo Conn.
POWER BOARD
USB Board
Touch Pad Int.KBD Thermal Sensor
Page 45 Page 45 NCT7718W USB Board
Page 39

ODD Board
4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 Block Diagram
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
ACLU9
Date: Monday, December 23, 2013 Sheet 2 of 59
A B C D E
 5 4 3 2 1

B2 A2
D
+3VLP PCH_PWR_EN# 1 D

Q26,+3VALW_SOC

V
V
AC A1
MODE VIN 3
VR_+1.0VALW_PWRGD

V V
A2 A4 B5

V
PU401 2

V
PU301 +3VALW_SOC

V
B+
+3VALW
BATT BATT V V

V V V
MODE B1
4
PCH_RSMRST#
EC
5 PBTN_OUT#

EC_ON SOC
A3 B4 other Device
PM_SLP_S3#
PM_SLP_S4# 6

V
PLTRST# 15

V
14
DDR_CORE_PWROK

V V
C C

B3 13
SYS_PWROK

V
ON/OFF V
NOVO

PXS_PWREN
(DIS)
Vb
+VGA_CORE

V
11 VR_REDY SYSON 7 +1.35V
PU909

V
PU501
DGPU_PWROK
PXS_PWREN
10 Va (DIS)

V
PU901 VR_ON Q4601 +1.35VGS

V
V

V
+CPU_CORE +5VS QV14
Q28

V
B Q4606 B

V
+1.35VS +1.05VGS

V
+1.0VS
SUSP# 9 PU702

V
VGA
PU602

V
V
PU603 +1.5VS
+1.05VS VR_+1.05VS_PWRGD +3VG_AON

V
QV11
V PU501
+0.675V VR_+1.5VS_PWRGD

12
V
EC_3VSPWREN Q30
V
Q4602
+1.8VS
+3VS

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 Power sequence Block

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
ACLU9
Date: Monday, December 23, 2013 Sheet 47 of 59
5 4 3 2 1
 5 4 3 2 1

B+
+5VLP/ 100mA
Silergy
D
Silergy D
SY8208CQNC +5VALW/6A SY8032LDBC
Adaptor Converter DFN10_3X3 +1.0VALW/2.5A
FOR SYSTEM Switch Mode
EC_ON EN PGOOD ALW_PWRGD FOR VDDR
PAGE 39
SUSP# EN PGOOD

+3VLP/ 100mA
Silergy
SY8206BQNC ANPEC
Converter +3VALW/ 5A APL5930AQBI-TRG
EC_ON EN FOR SYSTEM PGOOD ALW_PWRGD
TDFN10_3X3 +1.5VSP/1A
PAGE 39 Switch Mode
FOR VDDR
SUSP# EN PGOOD

TI +1.35V/10A
TPS51716RUKR
SYSON S5 WQFN20_3X3 Silergy
C SUSP# S3 +0.675VS/2A C
TI Switch Mode SY8032ABC
FOR DDR PGOOD SOT23-6 +1.05VSP_VGA/2A
BQ24737RGRR Switch Mode
Battery Charger FOR VDDR
EN PGOOD
Switch Mode
PAGE 46 Onsemi
CPU Core/12A
NCP6132AMNR2G
Silergy
QFN60_7X7 SY8089AAC
Switch Mode GFX Core/14A
SMBus
VR_ON
EN FOR CPU Core PGOOD VGATE
SOT23-5 +1.8VALW/1A
PGOOD_NB Switch Mode
FOR VDDR
EN PGOOD

Battery Onsemi Silergy

B
Li-ion NCP81172MNTWG SY8032ABC B

4S1P/41WH QFN24_4X4 +VGA_CORE/31A SOT23-6 +1.05VS/2A

VIDs
Switch Mode Switch Mode
NVDD_PWR_EN EN FOR VDDR
FOR GPU VDDC PGOOD VGA_PWRGD EN PGOOD

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 Power Diagram
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
ACLU9
Date: Monday, December 23, 2013 Sheet 50 of 59
5 4 3 2 1
 1 2 3 4 5

A A

Power-Up/Down Sequence
1. All the ASIC supplies must reach their respective nominal voltages within 20 ms
of the start of the ramp-up sequence, though a shorter ramp-up duration is
preferred. The maximum slew rate on all rails is 50 mV/µs.

2. The external pull ups on the DDC/AUX signals (if applicable) should ramp up
before or after both VDDC and VDD_CT have ramped up.
3. VDDC and VDD_CT should not ramp up simultaneously. For example, VDDC
should reach 90% before VDD_CT starts to ramp up (or vice versa).
4. For power down, reversing the ramp-up sequence is recommended.

PLT_RST#

VDDR3(3.3VGS) AND
PCH GATE
PLT_RST_VGA# PERSTB GPU
PCIE_VDDC(0.95V)
B B
GPIO50 DGPU_HOLD_RST

VDDR1(1.5VGS) GPIO54 DGPU_PWR_EN

TACH0/GPIO17 DGPU_PWROK

VDDC/VDDCI(1.12V)

VDD_CT(1.8V)
NOT DGPU_PWR_EN#

PERSTb
+3VS +3VS_VGA
REFCLK
MOS 1

Straps Reset +3VS +0.95VS_VGA +1.8VS +1.8VS_VGA

Regulator 2 MOS 5
Straps Valid
C B+ +VGA_CORE +1.5VS +1.5VS_VGA C

PWM 4 MOS 3
Global ASIC Reset

T4+16clock

CPU part

D D

Security Classification Compal Secret Data

Title
Compal Electronics, Inc.
Issued Date 2011/07/12 Deciphered Date 2012/07/01
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL MARS_Note
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
LA-9761PR01
Friday, November 02, 2012 Sheet 16 of 47
1 2 3 4 5
 5 4 3 2 1

[AC Mode] [DC Mode]

AC_IN BATT+

AC_PRESENT Ta <5ms AC_PRESENT

B+ Tb <5ms B+ Ta <5ms

+3VLP/+VL Tc <30ms +3VLP/+VL Tb <30ms

Td <5ms
D EN_5V/EN_3V Te moniter AC_IN (51_ON) ON/OFFBTN# D

+5VALW/+3VALW Tf <5ms EN_5V/EN_3V Td 10ms,Moniter ON/OFFBTN#

ON/OFFBTN# +5VALW/+3VALW Te <5ms

Tg 20ms,Moniter ON/OFFBTN# rising edge
EC_RSMRST# EC_RSMRST# Tc 20ms,Moniter ON/OFFBTN# and EN_3/5V rising edge
Th min 5ms,Moniter EC_RSMRST# rising edge
SUSCLK Tf 100ms,Moniter EC_RSMRST# rising edge
SUSCLK
PBTN_OUT# 20ms Ti=110ms Moniter ON/OFFBTN# rising edge
PBTN_OUT# 20ms Tg=110ms Moniter ON/OFFBTN# rising edge

PM_SLP_S5# T1 <20ms,Montier PBTN_OUT# falling edge.

PM_SLP_S4# T2 <30us
C C
PM_SLP_S3# T3 <30us

SYSON T4 10ms,moniter PBTN_OUT# rising edge.

+1.35V T5

SUSP# T6 < 40ms,moniter SYSON rising edge.

+5VS T7

+3VS T8

+1.8VS T9

+1.5VS T10

+1.05VS T11

+0.675VS T12

B VCCST_PG_EC (ALL_SYS_PWRGD,non CPU code VR) T14 <5ms B

VR_ON T17 immediately,After ALL_SYS_PWRGD assertion

+CPU_CORE Vboot, T18 <2.5ms

VGATE T19 <1us

PCH_PWROK T15 min 5ms,After VGATE assertion

H_CPUPWRGD T15 min 2ms ,After PCH_PWROK assertion

SYS_PWROK T20 min 5ms~99ms,After VCCST_PG_EC assertion

PCH_PLTRST# T22 TBD,After CPUPWRGD/PCH_PWRGD/SYS_PWROK assertion

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/08/25 Deciphered Date 2012/07/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power Sequence
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, November 02, 2012 Sheet 47 of 47
5 4 3 2 1
 A B C D E

LCFC confidential
File Name : ACLU5&6
AMD Jet LE/ Topaz XT
S3 Package: 23mmX23mm PCI-Express
Page 18~24
4x Gen2 Memory BUS (DDR3L)
Single Channel DDR3L-SO-DIMM X2
PEG 0~3 Page 14,15
VRAM 256/128*16
1
1.35V DDR3L 1600 MT/s 1

DDR3L*4 2GB/1GB UP TO 8G x 2
Page 25~26

HDMI
HDMI Conn. USB Left
Page 34 USB 3.0 1x
AMD FT3b APU USB 2.0 Port8
USB 3.0 Port0
VGA USB 2.0 2x JUSB2
CRT Conn. USB 2.0 Port3
Page 36 JUSB1 Page 41
eDP x2 Lane
eDP Conn
USB2.0 1x
Beema 15W /2.4G USB 2.0 1x Touch Screen
Int. Camera Page 33 USB2.0 Port4
USB2.0 Port5
(Integrated FCH)
2 2

Int. MIC Conn.

Page 33 USB2.0 1x USB Right

USB2.0 Port0
(Debug Port) JUSB3

SATA HDD SATA Gen3 USB2.0 1x

Page 42 SATA Port0 Cardreader Realtek SD/MMC Conn.
BGA-769 RTS5170 USB2.0 Port2
24.5mm*24.5mm USB Board
SATA ODD SATA Gen1
Page 42 SATA Port1

USB 2.0 1x
NGFF Card
LAN Realtek PCIe 1x WLAN&BT
RJ45 Conn. PCIe 1x PCIe Port1
Page 38
RTL8111GUL (1G) Page 40 USB2.0 Port6 Sub-board ( for 14")
RTL8106EUL (10M/100M)
3 3
Page 37 PCIe Port2
SPI BUS SPI ROM 0 POWER BOARD NS-A272
HD Audio
Page 4~9 8MB Page 07
USB Board  NS-A271

Codec SPK Conn.

Conexant CX20752 Page 43
Page 43
Sub-board ( for 15")
EC
ITE IT8586E-LQFP POWER BOARD  NS-A273
Page 44

HP&Mic Combo Conn. USB Board  NS-A275

USB Board
Touch Pad Int.KBD Thermal Sensor ODD Board NS-A274
4 Page 45 Page 45 NCT7718W
Page 39
4

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/15 Deciphered Date 2013/08/15 Block Diagram
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
NM-A281 0.4

Date: Thursday, February 20, 2014 Sheet 2 of 60

A B C D E
 5 4 3 2 1

Power Sequence Block need to be update! 2 SPOK

V
PU5
D D

VGA_PWRGD
AC A1
MODE VIN 3 +1.1VVALW

V V
A2 A3 B5

VV
A5 2

V
PU401

V
PU301
BATT B2
B+
+3VALW B7 2 V
BATT 4
MODE PU401 EC_RSMRST# VGA_PWRGD
B1

V
V
EC 5 PBTN_OUT#
VS B4

V
V
B3
PM_SLP_S3# FCH
V PM_SLP_S5# 6

V
51_ON#
A5 B7
11 FCH_PWRGD 12 APU_PWRGD

V V
V
EC_ON
PLT_RST# 13 14 APU_RST#
CPU

V
C C

15
A4 B6 KBRST#

V
V
ON/OFF V V
V

PXS_PWREN
PQ1
SYSON 7 PU7
8a

V
+VSYSMEM
+3VGS

V
QV2

V
SUSP#,SUSP 8
U12

V
+1.5VGS

V
+5VS
U14

V
U13 +1.8VGS
10
+3VS PU6
VGATE
B B

V
PU10 +0.95VGS VGA
+1.5VS PU12

V
PU7 VDDCI
+0.75VS PU11 8b

V
U15 +VGA_CORE VGA_PWRGD

V
+1.1VS PU13

PU8
+1.2VS
VR_ON 9 PU14 V
V

+CPU_CORE

A A

PU14
V

+APU_CORE_NB

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/15 Deciphered Date 2013/08/15 Power sequence Block
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
NM-A281 0.4

Date: Thursday, February 20, 2014 Sheet 47 of 60

5 4 3 2 1
 5 4 3 2 1

+5VLP/ 100mA
B+
Silergy
D SY8208CQNC +5VALW/5A
D

Adaptor Converter
EC_ON EN FOR SYSTEM PGOOD ALW_PWRGD

+3VLP/ 100mA
Silergy
SY8206BQNC
Converter +3VALW/4A Silergy
SY8868ABC
EC_ON EN FOR SYSTEM PGOOD ALW_PWRGD
Converter +1.8VALW/2.3A
FOR APU VDDIO
EC_APU_ALWEN EN PGOOD

Richtek +1.35V/11A
RT8231AGQW
C TI SYSON S5 Switch Mode C
+0.675VS/1.3A
BQ24737RGRR SUSP# S3
FOR DDR
Battery Charger PGOOD ANPEC
APL5930KAI-TRG
Switch Mode LDO +1.5VSP/150mA

FOR APU VDDIO

Intersil SUSP# EN PGOOD

ISL62771HRTZ APU Core/20A/25A

Switch Mode
SMBus
FOR APU/NB Core APU Core NB/13A/17A
EC_VR_ON EN PGOOD VR_APU_PWRGD
PGOOD_NB

Battery Silergy
Li-ion SYX198DQNC
B
Converter +0.95VS/7.68A
B
4S1P/41WH FOR APU VDD
EC_APU_ALWEN EN PGOOD APUALW_PWRGD

Interisl
ISL62771HRTZ
Switch Mode +VGA_CORE/20A
VIDs
PXS_PWREN EN FOR GPU VDDC PGOOD VR_VGA_PWRGD

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/15 Deciphered Date 2013/08/15 Power Diagram

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
NM-A281 0.4

Date: Thursday, February 20, 2014 Sheet 50 of 60

5 4 3 2 1
 Apple A1466 Power Up Timetable Full Version

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HP G4 Quanta Power Up Timing Diagram

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Samsung 300E4A timing chart Samsung OEM

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Lenovo Y470 power sequence diagram full version of Compal timing

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Sony timing diagram MBX-224 full version of the letter production

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