SMS 4 Synthesis and DFT

STAR Memory System Synthesis and DFT
Release 4.0
Synopsys, Inc. Page 1 of 40

SMS Release 4.0 Synthesis and DFT Revision A15
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REVISION DESCRIPTION REVISION ORIGINATOR DATE
HISTORY Vahagn Hovakimyan
Levon Hayrapetyan
Tigran Astvatsatryan

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INTRODUCTION
This Application Note describes the synthesis, scan insertion, fault coverage estimation, ATPG test patterns
generation and netlist simulation concepts, aspects, and techniques used in the SMS Network Release 4.0.
It includes general information, as well as tool-specific information.
The key steps of the SMS Network EDA Interoperability verification are as follows:
1. Generate memories, Wrappers, Processors, and Server.
2. Bottom-up synthesis of the SMS Network components.
3. Bottom-up scan insertion in the SMS Network components.
4. SMS level STA
5. ATPG
6. Formal equivalence checking of SMS RTL vs. netlist designs.
7. Formal equivalence checking of SMS RTL vs. DFT ready netlist designs.
8. Gate level simulation with SDF annotation.
SMS NETWORK GENERATION

At first the memory instances should be generated via Integrator.
It is necessary to ensure that each of the memories has a MASIS view, which describes the memory information
model and specifies the parameters necessary for SMS Network generation. Before wrapper generation you
should define/customize the SMS Wrapper timing, speed and DFT related options in order the timing constraints to
comply with the requirements of your design. Customization can be made through the custom.glb files (See
Appendix A.) of the SMS Network components as well as via the Integrator GUI illustrated below.
The SMS Network timing options are as follows:

 clocks frequency
 reset type
 clock multiplexing enable
The frequency of all clocks inside SMS can be manually set during wrapper configuration via following fields:
 Memory clock frequency defines the memory clock frequency in MHz
 SMS clock (clk_sms) frequency defines the SMS clock (clk_sms) frequency in MHz
 IEEE 1500 clock frequency defines the IEEE 1500 clock (WRCK) frequency in MHz
 Wrapper clock frequency defines the wrapper clock (clk_wr) frequency in MHz (for serial
architecture only)
The reset type of wrapper registers and the active level of rst_sms signal can be manually set during wrapper
configuration via “Reset type” field. Available values are as follows:
0 Wrapper registers have synchronous reset, synchronizers for both WRCK and clk_sms clock domains are
set on reset (rst_sms) signal inside wrapper. The active level of rst_sms signal is Logic High.
1 Wrapper registers have asynchronous reset, synchronizers for both WRCK and clk_sms clock
domains are set on reset (rst_sms) signal inside wrapper. The active level of rst_sms signal is Logic Low.

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2 Wrapper registers have asynchronous reset; no synchronizer is set on reset (rst_sms) signal inside
wrapper. The active level of rst_sms signal is Logic Low.
In case if the memory doesn’t have dedicated test clock and frequencies in test and functional mode are different,
a clock muxing should be added in SMS wrapper by setting the Clock multiplexing enable option value to true.
Based on these values the timing constraints and the corresponding input file for STAR Builder are generated.
Figure 1 Wrapper Configurations to Define Clocking and Reset Options

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The SMS Network speed enhancement options are as follows:
 Wrapper input pipeline registers
 Pipeline output in BIST mode
These options apply to the RTL views only. Constraints and scripts are not affected.
The Wrapper input pipeline registers option define the number of pipe-line registers added on Wrapper test
address, data and other high-speed control inputs (if 0, pipe-line registers will not be added).This option allows to
extend the processor-to-wrapper path for up to 3 fast-clock cycle passing distance improving data exchange speed
between processor and wrapper.
The Pipeline output in BIST mode option enabled the sets pipe-line register on the memory data output for high-
speed BIST. Memory data output functional path is not affected.

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Figure 2 Wrapper Configurations to Define Speed Enhancement Options
The SMS Network DFT options are as follows:

 DFT operations file path
 Reuse dm0 pin as ATPG scan enable
 External WT mode
 Additional DFT coverage (Func. Inputs)
The DFT operations file path option defines the path to the file in which DFT operation modes are defined.
The Reuse dm0 pin as ATPG scan enable option defines the wrapper dm0 pin as test scan enable pin.
This option allows to separate shift and capture stages by having separate modes for each stage.

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The External WT mode option enables or disables generation of external AWT or SWT logic in soft wrapper in
case if the memory does not have internal AWT or SWT function. Available values are as follows:
 No external WT Write trough logic will not be generated.
 External AWT AWT logic will be generated in wrapper.
 External SWT SWT logic will be generated in wrapper
NOTE: This option cannot be enabled in case when the memory has inputs with tag “DftMode” in MASIS or an
integrated comparator inside.
The Additional DFT coverage (Func. Inputs) option enables the generation of observable logic on the memory
functional inputs in wrapper in case if the memory does not have dedicated test inputs (soft wrapper).
Figure 3 Wrapper Configuration to Define DFT options
The Processor, Wrapper and Server compilers generate synthesis and DFT scripts as well as environment
constraints according to the default value of some Synthesis scripts parameters. Customization can be made
through the custom.glb files of the SMS Network components as well as via the Integrator GUI illustrated below.

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Figure 4 Wrapper Configurations to Define Synthesis scripts parameters
RESET SYNCHRONIZATION

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For both synchronous and asynchronous resets all synchronization requirements for the reset signal entering to
SMS Network are handled inside the SMS Network components. Data flow diagrams for reset synchronizers with
both synchronous and asynchronous resets are illustrated below.
vl_ra_rst_sms_syncf_r[1:0]
1'b1 SET SET

D Q D Q 0 rst_syncf_int
1 to Wrapper FFs
RST
CLR
Q RST
CLR
Q
rst_sms
clk_sms
dft_mode*
vl_ra_rst_sms_syncs_r[1:0]
1'b1 SET SET

D Q D Q 0 rst_syncs_int
1 to Wrapper FFs
RST
CLR
Q RST
CLR
Q
rst_sms
WRCK
dft_mode*
* When DFT operations are declared during wrapper generation, dft_mode = dm2|dm1|dm0, otherwise dft_mode = dm2.
Figure 5 Reset synchronizers for SRAM Wrapper with asynchronous reset
vl_ra_rst_sms_syncf_r[1:0]
rst_sms SET SET

rst_syncf_int
D Q D Q
to Wrapper FFs
RST
CLR
Q RST
CLR
Q
clk_sms
vl_ra_rst_sms_syncs_r[1:0]
rst_sms SET SET rst_syncs_int

D Q D Q
to Wrapper FFs
RST
CLR
Q RST
CLR
Q
WRCK
Figure 6 Reset synchronizers for SRAM Wrapper with synchronous reset

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CLOCK DOMAIN CROSSING
In the SMS Network components to avoid from metastability issues the following solution is used:
 two-flip-flop synchronizers are implemented on control signals crossing the slow to fast domain border
 data signals crossing the slow to fast domain border are synchronized using enable techniques
 functionality of SMS Network does not require synchronizers on signals crossing the fast to slow domain
border
 signals are registered in the source clock domain before passing to the destination clock domain to avoid a
combinational settling
Data flow diagrams for SMS Processor and Wrapper synchronizers are illustrated below.
0
m_scan_step
shift_dr
1
*_vlsmsmeta pos_wrck
half_wrck SET SET SET SET
D Q D Q D Q
D Q scan_step_r
CLR Q CLR Q CLR Q CLR Q
m_update_wir
update_wir *_vlsmsmeta
SET SET SET
D Q D Q D Q
CLR Q CLR Q CLR Q
*_vlsmsmeta m_updatedr
update_dr
SET SET SET
D Q D Q D Q
CLR Q CLR Q CLR Q
*_vlsmsmeta m_capturedr
capture_dr
SET SET SET
D Q D Q D Q
clk_sms CLR Q CLR Q CLR Q
Figure 7 CDC synchronizers for SMS Processor

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0
scan_step
int_wr_se
1
*_vlsmsmeta pos_wrck
half_wrck SET SET SET SET
D Q D Q D Q
D Q scan_step_r
CLR Q CLR Q CLR Q CLR Q
m_bira_mode
bira_mode *_vlsmsmeta
SET SET SET
D Q D Q D Q
CLR Q CLR Q CLR Q
*_vlsmsmeta m_biste
biste
SET SET SET
D Q D Q D Q
clk_sms CLR Q CLR Q CLR Q
Figure 8 CDC synchronizers for SMS Wrapper

The simple two-flip-flop synchronizer is implemented in special module which has prefix “*_vlsmsmeta” so the end
user can replace the synchronizer module with synchronizer cells from the library. In the SMS Network
components for CDC paths the “set_max_delay” is used as a constraint to override the default single-cycle timing.
The delay value for CDC paths which are sourced in slow clock domain and are captured by “pos_wrck”,
“m_update_wir”,”m_updatedr” or,”m_capturedr” should be less than “2 * $T_bist” units. The delay value for CDC
paths which are sourced in slow clock domain and are captured by “scan_step_r” should be less than “3 * $T_bist”
units. The example below shows how to specify the timing constraints for CDC paths:
set_max_delay [expr 2 * $T_bist] -from [get_cells -hierarchical *wr_se_r*] -to [get_clocks {clkgrp_bist}]
set_max_delay [expr 3 * $T_bist] -from [get_clocks {clkgrpslow}] -to [get_clocks {clkgrp_bist}]
Where:
T_bist is period of fast clock
clkgrp_bist is name of fast clock (clk_sms)
clkgrpslow is name of fast clock (WRCK)
For high speed design end user can replace two-flip-flop synchronizer with N-flip-flop synchronizer. In this case the
timing constraints should be changed accordingly.
set_max_delay [expr N * $T_bist] -from [get_cells -hierarchical *wr_se_r*] -to [get_clocks {clkgrp_bist}]
set_max_delay [expr (N+1) * $T_bist] -from [get_clocks {clkgrpslow}] -to [get_clocks {clkgrp_bist}]
Serial outputs of scan chains from fast clock domain are not synchronized before capturing in slow clock domain,
because serial outputs are passed and held stable for enough time (at least 4 clk_sms periods) before being
sampled, there is no danger that the sampled value will go metastable.
set_max_delay [expr $T_slow - (4 * $T_bist)] -from [get_clocks {clkgrp_bist}] -to [get_clocks {clkgrpslow}]
Where T_slow is period of slow clock.

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DFT OPERATION TABLE
The SMS 4.0 provides a new feature which enables the customization of the circuitry controlling the memory inputs
during DFT operations through DFT operation tables. Customers have the opportunity to define custom DFT
operation tables via .tcl files. The circuitry controlling the DFT operations has three input pins (dm0, dm1, dm2)
which allow to define up to seven custom DFT modes (000 is reserved for Functional/BIST mode). An example of
a DFT operations table and the corresponding .tcl file for it is given below.
Mode RAMSEQ ATPG-func ATPG-bist

dm2,dm1,dm0 111 100 101
TCLKE 0 0 1
CDB 0 reg reg
DFTCLKEN 0 1 1
BISTE 0 0 1
DFTMASK 0 1 1
TEST1 0 0 0
RME 0 0 0
Table 1 DFT operations table
set dft_op_names {ATPG_func 100 ATPG_bist 101 RAMSEQ 111}
set dft_op_table(ATPG_func,enable) {DFTMASK DFTCLKEN}

set dft_op_table(ATPG_func,disable) { TCLKE BISTE TEST1 RME}
set dft_op_table(ATPG_bist,enable) { TCLKE DFTCLKEN BISTE DFTMASK }

set dft_op_table(ATPG_bist,disable) {TEST1 RME}
set dft_op_table(RAMSEQ,enable) {}
set dft_op_table(RAMSEQ,disable) { TCLKE CDB DFTCLKEN BISTE DFTMASK TEST1 RME }
The first line describes the names of the DFT operation modes and their codes (dm2, dm1, dm0).
NOTE: The first pair of elements of this list should specify the DFT mode name and the dm2, dm1, dm0 pins
values which satisfy the design rules. These values will be used to create the test protocol, based on which the test
DRC (design rule checks) will be made. After successfully passing the test DRC on these values the CTL model of
design will be created also.
The following pairs of lines describe the memory pins excluding memory data and address inputs or from the
specific wrapper internal signals (any of available) which should be enabled and disabled, correspondingly, during
a certain DFT mode. In case if the memory does not have internal test logic/DFT logic some wrapper internal
signals (refer to User’s Manual on Wrapper Compiler, chapter 9.3.1 for details.) could be described in this way as
well. Each memory in design could have such a .tcl file defining its DFT operation modes. Different memories
could have the same .tcl file, provided that they have similar pinout and functionality. Further, the paths of .tcl files
should be provided to Wrapper Compiler, in order Wrapper Compiler to generate the corresponding DFT control
circuitry in RTL. It is mandatory for the memories/wrappers grouped under the same processor to have the same
DFT mode names and their corresponding codes (the first line in .tcl file), since the dm2, dm1, dm0 pins for all
wrappers being grouped under the same processor are shared. There is no limitation for grouping
memories/wrappers which do not have a DFT operation table. However, for different processors these pins are not

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shared, and the SOC designer has the opportunity either to propagate them to the upper level separately or to
combine them into one shared bus via STAR Builder. The dm pins can be controlled via TAP.
When Reuse dm0 pin as ATPG scan enable option is active the wrappers dm0 pin should be defined as scan
enable. In the DFT operation table the shift and capture stages should be described as separate modes.
An example of a tcl file for DFT operations table for this option is presented below.
set dft_op_names {ATPG_func_shift 111 ATPG_func_capture 110 ATPG_bist_shiftt 101 ATPG_bist_capture 100 }
set dft_op_table(ATPG_func_shift,enable) {DFTCLKEN TCLKE}

set dft_op_table(ATPG_func_shift,disable) { TEST1 RME}
set dft_op_table(ATPG_func_capure,enable) {DFTCLKEN}
set dft_op_table(ATPG_func_capuret,disable) { TCLKE BISTE TEST1 RME}
set dft_op_table(ATPG_bist_shift,enable) { DFTCLKEN TCLKE}

set dft_op_table(ATPG_bist_shift,disable) {TEST1 RME}
set dft_op_table(ATPG_bist_capure,enable) { DFTCLKEN TCLKE BISTE}
set dft_op_table(ATPG_bist_capure,disable) {TEST1 RME}
The Reuse dm0 pin as ATPG scan enable option defines the wrapper dm0 pin as a test scan enable pin.
Each ATPG_func and ATPG_bist mode is separated into 2 modes: capture and shift. The shift mode is the same for
each mode. During the capture mode it is possible to switch Memory Data, Address, control and clock pins to
functional or BIST inputs.
Setting specific wrapper internal signals in DFT table
If the memory does not have BIST interface on its hard macro then multiplexers will be set on memory data,
address, control and clock inputs. If the memory does not have internal AWT or SWT function, then AWT or SWT
function can be generated in soft wrapper RTL.
In this case the following wrapper internal signals can also be defined in DFT operations file allowing increasing
the ATPG coverage of BIST logic:
bist_en_int Control signal to the multiplexer switching memory data, address and control input signals. If set to
1, the signals from BIST logic take the control over the memory, otherwise the memory is controlled
by the User's input signals. If this signal is not included in a particular array for particular DFT mode,
then the signal will be toggling during that particular mode by default.
tclk_en_int1 Control signal to the multiplexer switching the memory clocks. If set to 1, the BIST clock signal is
provided to the memory, otherwise if set to 0, the functional clock signal is to the memory. If this
signal is not included in particular array for particular DFT mode, then the signal will be set to 1
during that particular mode by default.
Note: During the functional mode this signal is set to 0 to provide the functional clock to the memory.
wt_en_int2 Control signal enabling Write Though Mode. If this signal is not included in a particular array for
particular DFT mode, then the signal will be set to 1 during that particular mode by default, i.e. Write
Though Mode will be enabled.
wr_tclk_en_int Control signal to the multiplexer switching clocks to wrapper DFT related sequential
logic (observable flops, SWT, if available). If set to 1, the BIST clock signal is provided to the
wrapper DFT related logic, otherwise if set to 0, the functional clock signal is provided to the

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wrapper DFT related logic. If this signal is not included in particular array for particular DFT
mode, then the signal will be set to 1 during that particular mode by default.
Note: During the functional mode this signal is set to 1 to provide clk_sms to the wrapper flops.
1
Available if “Multiplexers on user clock” option is enabled.
2
Available if “External Write-Through mode” option is enabled.
The truth table for wrapper internal signals is represented below.
Wrapper Mode bist_en_int wt_en_int tclk_en_int wr_tclk_en_int

Functional Mode 0 0 0 1
BIST mode 1 0 1 1
DFT mode (default
toggling 1 1 1
states)
Table 2 Wrapper internal signals truth table
NOTE: wt_en_int, tclk_en_int and wr_tclk_en_int are not allowed to toggle during any DFT mode.
SYNTHESIS AND SCAN INSERTION PROCEDURE

There are two main stages of synthesis and scan insertion using Synopsys DC/DFT Compilers:
 Data preparation
 Block-level synthesis, scan chains insertion and stitching
Synthesis and scan insertion should be run for the following sequence of modules:
1. Wrappers
2. Processors
3. Server

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WRAPPERS SYNTHESIS AND SCAN INSERTION
During wrapper generation the following tree of synthesis and scan insertion specific files and folders is created:
eda_verify
constr mem_virt_views run_all run_fm_dft rm_folders run_tetramax test_scripts run_lib run_syn run_pt run_fm
mem_exc.sdc std_cells.v wr_pt.tcl
msff_annot.tcl std_cells.lib wr_dft.tcl
<WrName>_dft.tcl std_cells.max wr_syn.tcl
<WrName>_tim.sdc std_cells.fs_lib std_lib.tcl
<WrName>_ env.sdc <MemName>.lib mem_lib.tcl
<MemName>_ ctl.tcl <MemName>.max wr_rtl_gate.fms
<WrName>_ int_ctl.tcl <MemName>_atpg_netlist.v create_mem_ctl.tcl
mem_arcs_dis.tcl wr_rtl_postdft.fms
mem_dt.tcl tetramax.tcl
create_wr_int_ctl.tcl
Figure 9 Files and Folders tree after wrapper generation

Folders
Files
Scripts (test_scripts folder)
File name Description

mem_lib.tcl Memory virtual/real timing library compilation script

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wr_syn.tcl DC synthesis script for Wrappers
wr_pt.tcl PrimeTime STA script for Wrappers
wr_dft.tcl DFTC scan insertion script for Wrappers
tetramax.tcl Tetramax ATPG script for Wrappers
create_mem_ctl.tcl Main DFTC script, which creates memory CTL model. This file is generated
when memories’ MASIS view contains IntScanChain section.
create_wr_int_ctl.tcl DFTC script, which creates CTL model for <wr_name>_int module. This file is
generated when MASIS description of memories contains IntScanChain section
and at least one chain is reused in the Comparator section.
std_lib.tcl Integrated memory std_cells library compilation script
wr_rtl_gate.fms RTL vs. Gate formal equivalence checking script for Synopsys Formality.
wr_rtl_postdft.fms RTL vs. Post-DFT formal equivalence checking script for Synopsys Formality.
Constraints (constr folder)

< WrName>_tim.sdc Timing constraints for wrappers
< WrName>_env.sdc Environment constraints for wrappers
msff_annot.tcl Metastability flip-flop’s timing checks annotation files
mem_arcs_dis.tcl Memory timing arcs’ timing disabling file for using when compiling wrappers
mem_dt.tcl Memory timing arcs’ timing disabling file for using when compiling processor
mem_exc.sdc Memory timing exception file for using when compiling processor
<MemName>_ctl.tcl Script identifying the memory test-related pins, constraints and existing scan
chains. This file is generated when memories’ MASIS view contains
IntScanChain section and is used in create_mem_ctl.tcl main script.
< WrName >_int_ctl.tcl Script identifying the <WrName>_int module test-related pins and constraints.
This file is generated when MASIS view of memories contains IntScanChain
section and it is used in create_wr_int_ctl.tcl main script and at least one chain
is reused in the Comparator section as well as corresponding chains of Scan
Input and Shift Enable pins have Comparator tag in MASIS description.
< WrName >_dft.tcl Script identifying the <WrName> module test-related pins and constraints. This
file is used in wr_dft.tcl main script
Command file and DC/PT/FM setup

run_lib Library compilation run command file
run_syn Main synthesis run command file
run_pt PrimeTime STA run command file

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run_fm RTL vs. Gate Formality verification run command file
run_fm_dft RTL vs. Post-DFT Formality verification run command file
run_tetramax Run Tetramax script.
run_all Runs all “run” command files
.synopsys_dc.setup Synopsys DC setup file
.synopsys_pt.setup Synopsys PT setup file
.synopsys_fm.setup Synopsys FM setup file
For wrapper synthesis and DFT verification purposes the following types of virtual memory description files are
required. Those files are:
1. memory timing model libraries;
2. memory ATPG model;
3. memory Tetramax model;
4. Verilog, Timing, Tetramax and FastScan models of standard cells library.
All off the above-mentioned types are generated based on MASIS description. Those files are located in
eda_verify/mem_virt_views folder. In case if there are no real memory models these virtual models are used for
verification purposes.
mem_virt_views folder

std_cells.v Verilog model of standard cells used in <MemName>_atpg_netlist.v for ATPG
patterns simulation.
std_cells.lib Timing model of standard cells used in <MemName>_atpg_netlist.v for creating
memory CTL model.
std_cells.max Standard cells Tetramax model used in <MemName>_atpg_netlist.v for
Synopsys Tetramax ATPG patterns generation.
std_cells_fs.lib Standard cells Mentor ATPG library used in <MemName>_atpg_netlist.v for
Mentor Fastscan ATPG patterns generation.
<MemName>.lib Virtual memory timing model library.
<MemName>.max Virtual memory core Tetramax model.
<MemName>_atpg_netlist.v Virtual memory combinational logic netlist Verilog description
(test_input/user_input, bypass). If MASIS contains IntScanChain section, then
<MemName>_atpg_netlist.v contains scan chains description also. This file
provides DFT DRC rules for memory and serves as basis for memory CTL
model generation.
DATA PREPARATION, RUN_LIB

 Preparation of timing model for std_cells library
 Preparation of CTL models for memories
 Preparation of timing models for memories

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 Preparation of CTL models for SMS < WrName >_int module
Preliminary SMS synthesis and DFT verification can be done with memory virtual models located in
eda_verify/mem_virt_views folder.
To perform data preparation run run_lib command file from eda_verify directory. As a result, mem_db and logs
folders are created in eda_verify folder. In case if memory MASIS view contains IntScanChain section mem_ctl
folder will be created also.
Memory CTL models <MemName>.ctl are created based on <MemName>_atpg_netlist.v file and std_cells.lib
library.
mem_db folder contains <MemName>.db compiled timing and test model of the memory. This model is based on
the results of <MemName>.lib and <MemName>.ctl compilation.
mem_ctl folder also contains CTL test model of wrapper’s <WrName>_int module when at least one chain is
reused in the Comparator section. This module will be used for stitching memories shared scan chains (BIST and
DFT modes).
logs folder contains compilation log files.
The above mentioned operation can be done with memory real timing and atpg models. For this purpose run_lib
should be invoked with -real option. In this case, the project will be synthesized with real memory timing model
library, path to which should be written manually in <mem_lib.tcl> file in appropriate location. For Synopsys
memories those paths are generated automatically.
Generated memory CTL model is used for scan chain stitching between hard and soft macros. It can be applied as
test model during reading memory Synopsys .lib file. For example,
read_lib <MemoryName>.lib -test_model <MemoryName>.ctl
Generated <ProjName>_int_wr CTL model is used for scan chain stitching between SMS <ProjName>_int_wr
module and other logic. It can be applied as standalone test model for reading in DFT scripts. For example,
read_test_model -format ctl <ProjName>_int_wr.ctl –design <ProjName>_int_wr
NOTE: Some memories can have shared scan chain for functional and DFT purposes, with shared ScanEnable
and ScanIn inputs. Those memories can be differentiated from MASIS description. For not shared memories, ports
described as ScanEnable and DataScanIn in the MASIS’s IntScanChain section have tag None. In general there is
no necessity to create CTL test model for <WrName>_int module. In this case, for shared memories, ports
described as ScanEnable and DataScanIn can have tag Comparator. Here it is necessary to create CTL test
model for <WrName>_int module for further DFT usage purposes. After memory library has been compiled, the
main synthesis phase begins.
MAIN SYNTHESIS RUN_SYN

To perform the main synthesis run run_syn file from eda_verify directory. It will run synthesis and scan insertion
of wrappers. After compilation, syn_out, syn_out_dft and reports subfolders will be created in eda_verify folder.
The following files will be generated in syn_out folder:
Output files after synthesis

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<WrName>.sdf Standard delay format (SDF) file for wrapper netlist
<WrName>.ddc Synopsys .ddc of the memory wrapper
<WrName>.vs Memory wrapper netlist.
Files containing timing and area reports will be generated in reports folder. The synthesis log file will be created in
the logs folder.
SYNTHESIS TIMING EXCEPTIONS

There are false paths in the design and for some memories there are timing arcs that should be disabled during
synthesis and timing analysis.
The list of these timing exceptions are reflected in the corresponding generated files <WrName>_tim.sdc,
<mem_arcs_dis>.tcl, <mem_dt>.tcl, <mem_exc>.sdc in constr folder. <mem_dt>.tcl, <mem_exc>.sdc are
used during processor synthesis. <mem_dt>.tcl is a PrimeTime script and is dedicated for disabling memory some
timing arcs. <mem_exc>.sdc file is a memory exceptions file for using from SMS level.
COMPILATION STRATEGY
Synopsys uses top-down compile strategy for wrappers. Synthesis script is wr_syn.tcl, which is located in the
test_scripts folder.
SCAN INSERTION AND ATPG

Wrapper scan insertion is performed by wr_dft.tcl script which uses < WrName >_dft.tcl constraint file located in
constr folder, and an already generated CTL test model <WrName>_int.ctl and located in the mem_ctl folder.
The sequential run of all the above mentioned scripts can be performed via run_syn file. The following files will be
generated in syn_out_dft folder:
Scan insertion output files

<WrName>_dft.vs Wrapper scan chain inserted netlist Verilog file. It can be used for ATPG and
test pattern simulation.
<WrName>_dft.ctl Wrapper CTL test model. This model can be used for scan insertion from upper
level.
<WrName>_dft.spf Wrapper STIL procedure file for standalone wrappers Tetramax ATPG.

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eda_verify
logs mem_db mem_ctl syn_out reports syn_out_dft
pt.log <MemName>_lib.db <MemName>.ctl <WrName>.ddc timing_bist <WrName>_dft.ctl
lib.log <MemName>.spf <WrName>.vs coverage.rpt <WrName>_dft.spf
mem_ctl.log <WrName>_int.ctl <WrName>.sdf constraint.rpt <WrName>_dft.vs
wr_int _ctl.log <WrName>_int.spf check_timimg.rpt
wr_syn.log exceptions.rpt
wr_dft.log timing_min.rpt
change_names.log timing_max.rpt
design_check_wr.log tetramax
tetramax.log detected.flt
wr_rtl_gate.log undeteced.flt
wr_rtl_vs_dft.log summary_report.rpt
<WrName>_<freq>.rpt
wr_rtl_gate.rpt
wr_rtl_vs_dft.rpt
wr_rtl_vs_dft_ver.status

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Figure 10 Added Files and Folders tree after synthesis’s for wrapper
Folders
Library compilation
Main synthesis
run_pt, run_tetramax, run_fm, run_fm_dft
PROCESSOR SYNTHESIS AND SCAN INSERTION

During Processor generation the following tree of synthesis specific files and folders is created:
eda_verify
constr run_all run_tetramax test_scripts run_syn run_pt run_wrappers run_fm run_fm_dft
mem_exc.sdc sms_pt.tcl
msff_annot.tcl sms_syn.tcl
disable_timing_proc.tcl stp_dft.tcl
<ProcName>_stp_env.sdc stp_syn.tcl
<ProcName>_ stp_tim.sdc tetramax.tcl
<ProcName>_sms_tim.sdc proc_rtl_gate.fms
<ProcName>_sms_env.sdc proc_rtl_postdft.fms
<ProcName>_stp_dft_constraints.tcl
mem_dt.tcl
Figure 11 Files and Folders tree after processor generation
Folders

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Files

sms_syn.tcl DC synthesis script for SMS.
stp_syn.tcl DC synthesis script for Processor.
sms_pt.tcl PrimeTime STA script for SMS.
stp_dft.tcl DFTC scan insertion script for Processor.
tetramax.tcl Tetramax ATPG script for Processor.
proc_rtl_gate.fms RTL vs. Gate formal equivalence checking script for Synopsys Formality.
proc_rtl_postdft.fms RTL vs. Post-DFT formal equivalence checking script for Synopsys Formality.
Constraints and exceptions (constr folder)

<ProjName>_sms_tim.sdc Timing constraints for SMS.
<ProjName>_sms_env.sdc Environment constraints for SMS.
<ProjName>_stp_tim.sdc Timing constraints for STP.
<ProjName>_stp_env.sdc Environment constraints for STP.
<ProjName>_dft_constraints.tcl Script which identifying the Processor test-related pins and constraints. This file
is used in stp_dft.tcl main script
disable_timing_proc.tcl TCL procedure for disabling memory timing arcs.
mem_dt.tcl Memory timing arcs’ timing disabling file.
mem_exc.sdc Memory timing exception file.

run_lib Library compilation run command file.
run_syn Main synthesis run command file.
run_pt PrimeTime STA run command file.
run_fm Formality RTL vs. Gate verification run command file.
run_fm_dft Formality RTL vs. Post-DFT netlist verification run command file.

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run_tetramax Run Tetramax script.
run_wrappers Wrappers compilation run command file.
run_all Runs all “run” run command files.
.synopsys_dc.setup Synopsys DC setup file.
.synopsys_pt.setup Synopsys PT setup file.
.synopsys_fm.setup Synopsys FM setup file.

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After Wrappers compilation is finished, the main synthesis and scan insertion of the Processor can be performed
by running run_syn file from eda_verify directory. This will run synthesis and scan insertion of processor. After
synthesis, folders syn_out and reports will be created in eda_verify. The following files will be generated in
syn_out folder:

<ProjName>_sms.ddc Synopsys.ddc of the SMS.
<ProjName>_sms.vs SMS netlist (wrapper(s) and processor).
<ProjName>_sms.sdf Standard delay format (SDF) file for SMS netlist.
<ProjName>_stp.ddc Synopsys .ddc of the STP.
<ProjName>_stp.vs STP netlist.
<ProjName>_stp.sdf Standard delay format (SDF) file for STP netlist.
Files containing timing and area reports will be generated in the reports folder. The synthesis log file will be
created in the logs folder.
Wrapper synthesis can be run from Processor’s eda_verify folder by running run_wrappers file. If it is preferable
to run the whole process of Wrappers and Processor synthesis and scan insertion from Processor’s eda_verify
folder then run_all file should be run. This run_all file is intended to run all scripts needed to synthesize at first
Wrappers and after that Processor.

There are false paths in the design and for some memories there are timing arcs that should be disabled during
synthesis and timing analysis.
The list of these timing exceptions is reflected in the corresponding generated files <ProjName>_tim.sdc,
<mem_dt>.tcl, <mem_exc>.sdc in constr folder. <mem_dt>.tcl and <disable_timing_proc.tcl> are PrimeTime
scripts and are dedicated for disabling memory some timing arcs. <mem_exc>.sdc is a memory exceptions file.
Synopsys uses bottom-up compile strategy for internal verification. For SMS design each wrapper and STP are
compiled separately, and later are incorporated in the top-level design. The top-level constraints are applied and
the whole design is checked for violations. Synthesis scripts stp_syn.tcl and sms_syn.tcl are located in the
test_scripts directory.
To get the complete top-level constraints to be used in customer’s design scripts, STAR Builder’s Script_Gen plug-
in must be used, which is described in the STAR Builder documentation.

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eda_verify
logs syn_out reports syn_out_dft
pt.log <ProcName>_sms.ddc timing_bist <ProcName>_stp_dft.ctl
<ProcName>_stp_dft.log <ProcName>_sms.vs coverage.rpt <ProcName>_stp_dft.spf
design_check_stp.log <ProcName>_stp.ddc constraint.rpt <ProcName>_stp_dft.vs
<ProcName>_sms.log <ProcName>_stp.vs check_timimg.rpt
<ProcName>_stp.log <ProcName>_sms.sdf exceptions.rpt
change_names.log <ProcName>_stp.sdf timing_min.rpt
design_check_sms.log timing_max.rpt
tetramax.log tetramax
proc_rtl_gate.log detected.flt
proc_rtl_vs_dft.log undeteced.flt
summary_report.rpt
<ProcName>_sms_<freq>.rpt
<ProcName>_stp_<freq>.rpt
proc_rtl_vs_dft.rpt
proc_rtl_gate.rpt
proc_rtl_vs_dft_ver.status
Figure 12 Added Files and Folders tree after synthesis’s for processor
Folders
Main synthesis

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Processor scan insertion is performed by stp_dft.tcl script which uses <ProcName>_constraints.tcl constraint
file located in constr folder. <ProcName>_constraints.tcl is a DFTC script, which contains dm0, dm1, dm2 ports,
asynchronous reset and test clocks description specific commands for processor scan insertion. dm0, dm1 and
dm2 signals’ values are determined by the corresponding ports value of wrappers. This combination provides DFT
DRC for processor. In case if those ports are missing for all of the wrappers or only dm2 port exists, DFT DRC for
processor is provided by dm2 only. After running <ProcName>_dft.tcl script the following files will be generated in
the syn_out_dft folder:

<ProcName>_dft.vs Processor scan chain inserted netlist Verilog file. It can be used for Simulation
by ATPG tools.
<ProcName>_dft.ctl Processor CTL test model. This model can be used for insertion from upper
level.
<ProcName>_dft.spf Processor STIL procedure file for stand alone processor Tetramax ATPG.
Tetramax simulation and fault coverage estimation is done by tetramax.tcl script. Results are located in
eda_verify/reports/tetramax folder.

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SERVER COMPILER’S JPC AND SFP MODULES SYNTHESIS AND SCAN
INSERTION
During JPC/SFP generation the following tree of synthesis specific files and folders is created:
eda_verify
constr run_lib run_fm_dft run_syn run_pt run_fm test_scripts
jpc_sfp_env.sdc fuse_lib.tcl
jpc_sfp_tim.sdc jpc_sfp_pt.tcl
jpc_sfp_dft_constr.tcl jpc_sfp_dft.tcl
jpc_sfp_syn.tcl
jpc_sfp_tmax.tcl
srv_rtl_postdft.fms
srv_sfp_rtl_gate.fms
Figure 13 Files and Folders tree after JPC/SFP generation
Folders
Files

fuse_lib.tcl Efuse library compilation script.
jpc_sfp_syn.tcl DC synthesis script for JPC/SFP.
jpc_sfp_pt.tcl PrimeTime STA script.
jpc_sfp_dft.tcl DFTC JPC/SFP scan insertion script.
jpc_sfp_tmax.tcl Tetramax script for fault coverage estimation.
srv_sfp_rtl_gate.fms RTL vs. Gate formal equivalence checking script for Synopsys Formality.

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srv_rtl_postdft.fms RTL vs. Post-DFT formal equivalence checking script for Synopsys Formality.
Constraints and exceptions (constr folder)

jpc_sfp_tim.sdc Timing constraints.
jpc_sfp _env.sdc Environment constraints.
jpc_sfp_dft_constr.tcl Script which identifying the JPC/SFP test-related pins and constraints. This file
is used in jpc_sfp_dft.tcl main script

run_lib Library compilation run command file.
run_syn Main synthesis run command file.
run_pt PrimeTime STA run command file.
run_fm RTL vs. Gate Formality verification run command file.
run_fm_dft RTL vs. Post-DFT Formality verification run command file.
.synopsys_dc.setup Synopsys DC setup file.
.synopsys_pt.setup Synopsys PT setup file.
.synopsys_fm.setup Synopsys FM setup file.
DATA PREPARATION, RUN_LIB
To perform a data preparation run run_lib file from eda_verify directory. Running run_lib file will create logs and
mem_db folders in eda_verify folder, compile all e-fuses, put the compiled files into the mem_db folder, and the
compilation log file into the logs folder.
After efuse library is compiled, main synthesis phase begins.

To perform the main synthesis run run_syn file from eda_verify directory. It will run synthesis of JPC and SFP
modules. After synthesis, syn_out and reports subfolders will be created in eda_verify folder. The following files
will be generated in syn_out folder:

<ProjName>_jpc_sfp.sdf Standard delay format (SDF) file for JPC and SFP netlist.
<ProjName>_jpc_sfp.ddc Synopsys .ddc of JPC and SFP modules.
<ProjName>_jpc_sfp.vs JPC and SFP netlist.

APNT-00XX-SM-GE
Files containing timing and area reports will be generated in reports folder files. The synthesis log file will be
created in logs folder.

There are false paths in the design and that should be disabled during synthesis and timing analysis. The list of
these timing exceptions is reflected in the corresponding generated files jpc_sfp_tim.sdc in the constr folder.
Synopsys uses top-down compile strategy for JPC and SFP modules. Synthesis script jpc_sfp_syn.tcl is located
in the test_scripts folder.
To get the complete top level constraints to be used in customer’s design scripts, STAR Builder’s Script_Gen plug-
in must be used, which is described in the STAR Builder documentation.
eda_verify
logs mem_db syn_out reports syn_out_dft
pt.log <FuseName>_lib.db <SerName>_jpc_sfp.ddc timing_bist <SerName>_jpc_sfp_dft.ctl
lib.log <SerName>_jpc_sfp.vs coverage.rpt <SerName>_jpc_sfp_dft.spf
<SerName>_jpc_sfp.log constraint.rpt <SerName>_jpc_sfp_dft.vs
<SerName>_jpc_sfp_dft.log check_timimg.rpt
change_names.log exceptions.rpt
design_check.log timing_min.rpt
tetramax.log timing_max.rpt
<SerName>_jpc_sfp_RTL_gate_fm.log tetramax
srv_rtl_vs_dft_fm.log detected.flt
undeteced.flt
summary_report.rpt
<SerName>_jpc_sfp.rpt
<SerName>_jpc_sfp_RTL_gate_fm.rpt
srv_rtl_vs_dft_fm.rpt
srv_rtl_vs_dft_ver_fm.status
Figure 14 Added Files and Folders tree after synthesis for JPC/SFP
Folders

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tetra
max
.tcl
Library compilation
Main synthesis

APNT-00XX-SM-GE
If SFP module exists then scan insertion is done by jpc_sfp_dft.tcl script, which uses jpc_sfp_dft_constr.tcl
constraint file located in constr folder. Otherwise, the corresponding files are named jpc_dft.tcl and
jpc_dft_constr.tcl. jpc_sfp_dft_constr.tcl/jpc_dft_constr.tcl is a DFTC script, which contains dft_mode,
asynchronous reset and test clocks description specific commands for processor scan insertion. After running
jpc_sfp_dft.tcl/jpc_dft.tcl script the following files will be generated in syn_out_dft folder:

sc_jpc_sfp_dft.vs Scan chain inserted netlist Verilog file. It can be used for ATPG and test pattern
simulation.
sc_jpc_sfp_dft.ctl CTL test model. This model can be used for Scan insertion from upper level.
sc_jpc_sfp_dft.spf STIL procedure file for stand alone sc_jpc_sfp module Tetramax ATPG.
Tetramax simulation and fault coverage estimation is done by jpc_sfp_tmax.tcl/jpc_tmax.tcl script. Results are
located in eda_verify/reports/tetramax folder.
STATIC TIMING ANALYSIS

RUNNING PRIMETIME FOR WRAPPERS, PROCESSORS AND JPC AND SFP MODULES
Before performing static timing analysis, ensure that synthesis standard cell library, design and scripts are ready
and paths in the .synopsys_pt.setup file are set correctly.
In order to perform static timing analysis run_pt should be run from eda_verify folder. This step must be done if
further gate level simulation has to be performed, because .sdf data for simulation is being prepared by
PrimeTime. Therefore before project generation syn_fix_hold_enable parameter must be set to “1” in integrator
processor GUI or _custom.glb file for generating portions of the script related to hold time fixing and preparing .sdf
data. After STA is performed by PrimeTime, the following timing reports will be generated in the
reports/timing_bist folder:
Output files after Static Timing Analysis

check_timing.rpt Possible timing problems for design.
timing_max.rpt Maximum path reports.
timing_min.rpt Minimum path reports.
constraint.rpt Constraints violations.
exceptions.rpt Exceptions, ignored exceptions.
coverage.rpt Coverage report.
The pt.log file will be created in logs folder.

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NETLIST SIMULATION
GATE LEVEL SIMULATION WITH SDF BACK ANNOTATION
In SMS Network design synchronizers were used to transfer signals between different clock domains. Signals
crossing clock boundaries through a synchronizer may experience setup and hold violations. When doing gate-
level simulations on a multi-clock design, the library models of flip-flops are modeled with setup and hold time
expressions to match the timing specifications of the actual flip-flops. Libraries typically model flip-flops to drive
“X”s (unknown values) on the flip-flop outputs when a timing violation occurs. When simulating gate-level
synchronizers, setup and hold time violations might cause libraries to issue setup and hold time error messages
and the offending signals are driven to an “X” value. These “X”-values propagate to the rest of the design causing
problems when verifying the functionality of the gate-level design.
The above-mentioned problem can be solved in the following way:
Using Synopsys PrimeTime command to modify the SDF output for the setup and hold time on just the first stages
of the synchronizers’ flip-flop cells in the design (these are flip-flops with vl_ra and vl_a prefixes):
set_annotated_check 0 -setup –hold –clock rise –from register/clock –to register/data
register/clock – flip-flop instance names and clock pin

register/data – flip-flop instance names and data pin
These commands are in the file msff_annot.tcl which is located in the
/compout/views/<ProjName>/<eda_verify>/constr folder.
For generating these portions of code syn_fix_hold_enable parameter must be set to “true” in GUI or “1” in
*custom.glb file.
Gate level simulation is done using the Cadence NCVerilog simulator. There are corresponding lines in wrappers’,
processor’s and JPC and SFP testbenches that invoke the SDF back annotator. In order to invoke the SDF back
annotator, add the following command from the NCVerilog command line: +define GATE_LEVEL.
`ifdef GATE_LEVEL
//======== sdf annotation block ========================
initial
begin
$sdf_annotate(”<eda_verify/syn_out/ProjName>_ModuleName.sdf”,
<instance_name>);
end
//======== sdf annotation block ========================
`endif

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APPENDIX A
$Parameters name in glb/$Parameters name in the GUI = $User_value
List of parameters, default values and brief description of usage:

Note:
int_verif parameter ( Enable EDA verification in GUI) enables or disables
all synthesis parameters in dialog box. Setting this parameter to false
disables eda_verify folder generation.
Parameters name: int_verif

Parameters name in GUI: Enable EDA verification
Default value: TRUE
Description: Enables or disables synthesis, dft constraints
and verification scripts
Parameters name: use_defaults

Parameters name in GUI: Using target library default values
Default value: FALSE
Description: Setting this parameter to FALSE allows modifying default values
Parameters name: syn_lib_file_name

Parameters name in GUI: Target library file name
Default value: ts45nkkhdst_ss
Description: Sets the target library file name
Parameters name: verilog_file_name

Parameters name in GUI: Target library Verilog file name
Default value: ts45nkkhdst.v
Description: Sets the target library Verilog file name
Parameters name: fastscan_file_name

Parameters name in GUI: Target library FastScan model file name
Default value: ts45nkkhdst.atpg

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Description: Sets the target library FastScan model file name
Parameters name: syn_lib_name

Parameters name in GUI: Target library name
Default value: ts45nkkhdst_ss
Description: Sets the target library name
Parameters name: syn_lib_db_path

Parameters name in GUI: Target library db path
Default value: /am/proj_sp013b/lib/virage
Description: Sets the path of target library db file
Parameters name: syn_lib_verilog_path

Parameters name in GUI: Target library Verilog path
Description: Sets the path of target library Verilog file
Parameters name: syn_lib_atpg_path

Parameters name in GUI: Target library Fastscan models path
Description: Sets the path of FastScan models for target library
Parameters name: syn_op_condition

Parameters name in GUI: Operating condition name
Default value: WC_TIMING
Description: Sets the operating condition name
Parameters name: syn_wire_load_select_group

Parameters name in GUI: Wire load group name
Default value: ts45nkkhdst
Description: Sets the wire load group name
Parameters name: syn_driving_cell_name

Parameters name in GUI: Driving cell name

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Default value: SEH_BUF_1
Description: Sets the driving cell name
Parameters name: syn_driving_cell_pin_name

Parameters name in GUI: Driving cell output pin name
Default value: X
Description: Sets the driving cell output pin name
Parameters name: syn_dont_use_cells

Parameters name in GUI: dont use cell list
Default value: SEH_LD*
Description: Sets the dont use cell list
Parameters name: syn_wire_load_mode

Parameters name in GUI: Type of wire load mode
Default value: NULL
Description: Sets the type of wire load mode used for synthesis
Parameters name: syn_max_fanout

Parameters name in GUI: Max fanout value
Default value: 15
Description: Sets the max fanout
Parameters name: syn_pin_load

Parameters name in GUI: Pin load value
Default value: 0.001
Description: Sets the pin load value
Parameters name: syn_max_transition

Parameters name in GUI: Max transitinon value
Default value: 0.5
Description: Sets the max transitinon
Parameters name: syn_clock_uncertainty

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Parameters name in GUI: Clock uncertainty value
Default value: 0.1
Description: Sets the clock uncertainty
Parameters name: syn_input_delay_percent

Parameters name in GUI: Input delay percent
Default value: 0.6
Description: Sets input delay in percentage of clock period for BIST domain
Parameters name: syn_output_delay_percent

Parameters name in GUI: Output delay percent
Default value: 0.6
Description: Sets output delay in percentage of clock period for BIST domain
Parameters name: syn_user_input_delay

Parameters name in GUI: USER domain input delay
Default value: 0.3
Description: Sets input delay for USER domain
Parameters name: syn_user_output_delay

Parameters name in GUI: USER domain output delay
Default value: 0.3
Description: Sets output delay for USER domain
Parameters name: syn_sdf_version

Parameters name in GUI: SDF file version
Default value: 2.1
Description: Sets the SDF file version
Parameters name: TestReadyCompile

Parameters name in GUI: Test ready compilation
Default value: TRUE
Description: Sets for test ready compilation

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Parameters name: syn_fix_hold_enable
Parameters name in GUI: Enable fix hold violations
Description: Enables or disables fix hold violations
Parameters name: env_sdc_enable

Parameters name in GUI: Enable *_env.sdc files
Default value: TRUE
Description: Enables or disables generation of *_env.sdc files
Parameters name: syn_enable_change_names

Parameters name in GUI: Enable change names
Default value: TRUE
Description: Enables or disables change names before writing netlist
Parameters name: syn_custom_name_rule_file_path

Parameters name in GUI: Customer name rule file path
Default value: ./custom_name_rule
Description: Sets the path of customer name rule file
Parameters name: syn_rule_name

Parameters name in GUI: Name rule
Default value: verilog
Description: Specifies a name rule
Parameters name: en_rec_rem_check

Parameters name in GUI: Enable DC recovery and removal timing checks
Description: Enables or disables Synopsys DC recovery and removal timing
check
Parameters name: test_read_test_model

Parameters name in GUI: Disable read test_model

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Description: Disables reading of test_model during read_lib comand
Parameters name: syn_PRESTO_enable

Parameters name in GUI: Enable Presto HDL Compiler
Default value: TRUE
Description: Enables or disables the Presto HDL Compiler
Parameters name: syn_del_unloaded_seq_cells

Parameters name in GUI: Enable delete unload sequential cells
Description: Enables or disables preserve delete unload sequential cells
Parameters name: syn_ungroup_DW

Parameters name in GUI: Enable remove DesignWare hierarchy
Default value: TRUE
Description: Enables or disables remove the DesignWare hierarchy

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If you have further questions you can contact the Synopsys Support Center in the following ways:
 Open a call to your local support center using these pages:

http://www.synopsys.com/Support/GlobalSupportCenters/Pages/default.aspx
https://solvnet.synopsys.com (registration needed).
 Send an e-mail message to support_center@synopsys.com.

APNT-00XX-SM-GE

SMS 4 Synthesis and DFT

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STAR Memory System Synthesis and DFT

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Destination Control Statement

Registered Trademarks (®)

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SMS NETWORK GENERATION

The SMS Network timing options are as follows:

Synopsys, Inc. Page 4 of 40

Figure 1 Wrapper Configurations to Define Clocking and Reset Options

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Synopsys, Inc. Page 6 of 40

The SMS Network DFT options are as follows:

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Figure 3 Wrapper Configuration to Define DFT options

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1'b1 SET SET

1'b1 SET SET

Figure 5 Reset synchronizers for SRAM Wrapper with asynchronous reset

rst_sms SET SET

rst_sms SET SET rst_syncs_int

Figure 6 Reset synchronizers for SRAM Wrapper with synchronous reset

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CLR Q CLR Q CLR Q

CLR Q CLR Q CLR Q

clk_sms CLR Q CLR Q CLR Q

Figure 7 CDC synchronizers for SMS Processor

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CLR Q CLR Q CLR Q

clk_sms CLR Q CLR Q CLR Q

Figure 8 CDC synchronizers for SMS Wrapper

Where T_slow is period of slow clock.

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Mode RAMSEQ ATPG-func ATPG-bist

Table 1 DFT operations table

set dft_op_names {ATPG_func 100 ATPG_bist 101 RAMSEQ 111}

set dft_op_table(ATPG_func,enable) {DFTMASK DFTCLKEN}

set dft_op_table(ATPG_bist,enable) { TCLKE DFTCLKEN BISTE DFTMASK }

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set dft_op_table(ATPG_func_shift,enable) {DFTCLKEN TCLKE}

set dft_op_table(ATPG_bist_shift,enable) { DFTCLKEN TCLKE}

Setting specific wrapper internal signals in DFT table

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The truth table for wrapper internal signals is represented below.

Wrapper Mode bist_en_int wt_en_int tclk_en_int wr_tclk_en_int

SYNTHESIS AND SCAN INSERTION PROCEDURE

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mem_exc.sdc std_cells.v wr_pt.tcl

msff_annot.tcl std_cells.lib wr_dft.tcl

<WrName>_dft.tcl std_cells.max wr_syn.tcl

<WrName>_tim.sdc std_cells.fs_lib std_lib.tcl

<WrName>_ env.sdc <MemName>.lib mem_lib.tcl

<MemName>_ ctl.tcl <MemName>.max wr_rtl_gate.fms

<WrName>_ int_ctl.tcl <MemName>_atpg_netlist.v create_mem_ctl.tcl

Figure 9 Files and Folders tree after wrapper generation

Scripts (test_scripts folder)

File name Description

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Constraints (constr folder)

File name Description

Command file and DC/PT/FM setup

File name Description