9/21/2019 Hold-Time ATPG Test Flow

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Path Delay Fault and Hold Time Testing > Hold-Time ATPG Test Flow

Hold Time ATPG Test Flow

The TestMAX ATPG DSMTest option enables you to use hold time testing to perform test generation to
detect critical path minimum delays. This option generates the most effective tests possible while providing
the highest coverage of critical paths. TestMAX ATPG also includes features to read, manage, and analyze
paths from static timing analysis tools such as PrimeTime.

Most of the fault models supported by TestMAX ATPG are intended to test maximum delays (or setup
times), whether they are delay-based fault models (transition and dynamic bridging) or path-based fault
models (path delay). Even the static fault models (stuck-at and bridging) are simulated so that the fault
effect appears as a setup violation. The hold time fault model is different in that it tests minimum delays. In
other respects, the hold time flow is very similar to the path delay ATPG flow

The hold time fault model is different in that it tests minimum delays. In other respects, the hold time flow is
very similar to the path delay ATPG flow .

The hold time ATPG test flow is the same as the path delay ATPG flow, except that instead of running the
set_faults -model path_delay command, you need to specify the set_faults -model
hold_time command. The hold_time argument specifies the ATPG and fault simulation commands to
use the hold time fault model and must be specified before you add faults.

The standard hold time ATPG flow includes the following commands:

run_drc
set_faults -model hold_time
add_delay_paths hold_path_file
add_faults -all
run_atpg

You can use normal reporting commands such as report_summaries faults and
report_delay_paths. The fault types are reported as FTF (fast to fall) and FTR (fast to rise).

In the hold time ATPG test flow, all set_delay commands are ignored because the hold time path
transition is launched and captured in a single clock cycle. Hold time faults are usually detected by the
basic scan pattern type, although fast-sequential ATPG is also supported. Multiple-clock patterns are
generated when the hold time path must be set up or when its effects are propagated through nonscan
elements such as memories.

You can usually reduce the pattern count by first fault-simulating the stuck-at patterns with the hold time
fault model, and then using ATPG to create new patterns to detect the undetected paths.

All paths must start with a state element (DFF, DLAT, or memory) and must end with an edge-triggered
state element (DFF or edge-triggered memory); only combinational gates can be situated between the
starting and ending elements. The source and destination points must capture on the same edge of the
same clock. If the source and destination points are clocked by different clocks, the clocks must be either
synchronized internal clocks (see “Specifying Synchronized Multi Frequency Internal Clocks”) or equivalent
external clocks (see the description of the add_pi_equivalences command in TestMAX ATPG Online
Help). If these conditions are not satisfied, the path is declared ATPG Untestable (fault status AN).

The edge information provided in the path file is only used for the source point of the path. If the path goes
through XOR gates or multiple paths, then the polarity at the destination point and the path actually taken
by the transition might differ from what was specified.

In the fault modeled by the TestMAX ATPG fault simulator, the launching node makes its transition too
early. The captured node is assumed to be on time, and all off-path inputs are also assumed to be on time.

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If these assumptions result in a 0/1 difference in the output, then the fault is detected. See the
representations of a path delay test pattern in Figure 1 and a hold time test pattern in Figure 2.

Figure 2 Hold Time Test Pattern

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