816
2, MARCH/APRIL 2009
Implementation of a Four-Pole
Dead-Time-Compensated Neutral-Point-Clamped
Three-Phase Inverter With Low
Common-Mode Voltage Output
Robert M. Cuzner, Senior Member, IEEE, Ashish R. Bendre, Member, IEEE,
Peter J. Faill, and Boris Semenov, Member, IEEE
Abstract—This paper describes the implementation of a four-
pole neutral-point-clamped (NPC) three-phase inverter that pro-
duces virtually no common-mode voltage. The low common-mode
voltage output is achieved by constraining the switch states of the
NPC inverter to only those states that produce zero common-mode
voltage in dead-time compensation, which enhances the capability
of the circuit to produce low common-mode voltage by compen-
sating common-mode voltages produced by reverse diode commu-
tations. The low common-mode voltage performance is achieved
at the expense of reduced voltage utilization and loss of dc-link
voltage balance control. In order to overcome this limitation,
a fourth pole and associated control are added to balance the
upper and lower dc-link voltages. This paper describes the control
implementations and simulation results compared to measured
results used in tuning and commissioning of the system. A 450-V
78-kW system is implemented in hardware, and experimental
results are provided, showing its differential mode transient and
steady-state harmonic performance as well as its common-mode
output voltage.
Index Terms—Electromagnetic compatibility, grounding, power
systems, pulse width modulated inverters.
I. I NTRODUCTION
A PPLICATIONS where power electronic converters share
the same ac or dc bus with multiple loads require careful
attention to the interaction with these loads at the point of
common coupling. Whether the application is a variable fre-
quency motor drive, uninterruptible power system, renewable
energy system, or a power conversion system that provides
service power in a shipboard, aircraft, or other transportation
platform, certain interface standards must be met. These in-
terface standards include those that govern the electromag-
netic compatibility, power quality, and transient performance.
Paper IPCSD-08-068, presented at the 2007 Industry Applications Society
Annual Meeting, New Orleans, LA, September 23–27, and approved for
publication in the IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS by
the Industrial Power Converter Committee of the IEEE Industry Applications
Society. Manuscript submitted for review October 31, 2007 and released for
publication September 22, 2008. Current version published March 18, 2009.
R. M. Cuzner and A. R. Bendre are with DRS Power and Control Technolo-
gies, Milwaukee, WI 53216 USA (e-mail: RobertMCuzner@DRS-PCT.com).
P. J. Faill and B. Semenov are with DRS Power Systems, Hudson, MA 01749
USA (e-mail: bsemenov@drs-pt.com).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TIA.2009.2013603
0093-9994/$25.00 © 2009 IEEE
IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 45, NO.
In addition, successful integration of these systems requires
further insight into how the power electronics and associated
loads and sources interact on a common bus. Furthermore,
innovative circuit topologies and control techniques are needed
to make these systems compatible without incurring the cost
and weight of additional components, such as harmonic filters
and electromagnetic interference (EMI) filters.
A neutral-point-clamped (NPC) inverter [1] properly con-
figured, optimized, and controlled can achieve very good
performance from the standpoint of compatibility with a three-
phase ac bus. Previous work has demonstrated how the addi-
tional choices in switching states of the NPC inverter provide
many opportunities for optimizing a system for a particular
desired performance, whether low differential mode harmonic
performance, minimum dc-link ripple current, or low common-
mode output voltage [2]. The focus of this paper is a viable
NPC inverter implementation that produces very low common-
mode voltage output. This paper reports the implementation of
a fully commissioned 450-V 78-kW dc-to-ac inverter, which
can be applied as the power source to an ac grid having
multiple loads (deriving its power from some other dc source,
i.e., battery supply, isolated generator, or ac-to-dc transformer
rectifier).
The control, implementation, and demonstrated performance
of a four-pole three-phase NPC inverter shown in Fig. 1 are the
subject of this paper. The intentional components of this circuit
are represented by dark lines. The lighter lines represent the
equivalent source and load circuits for the surrounding system,
including capacitance to ground. The four-pole NPC inverter
itself does not include any intentional connections to ground.
The neutral point, designated by “N,” is floating with respect to
ground.
This converter produces virtually no common-mode voltage
with respect to ground. The low common-mode voltage output
is achieved by constraining the switch states of the NPC in-
verter. This performance is achieved at the expense of reduced
voltage utilization and loss of dc-link voltage balance control.
A fourth pole and associated control are added to balance the
upper and lower dc-link voltages.
Control implementation and tuning tradeoffs necessary to
achieve the desired performance objectives of a 450-V 78-kW
system are described in this paper. Steady-state harmonic,
CUZNER et al.: IMPLEMENTATION OF A FOUR-POLE NPC INVERTER WITH LOW COMMON-MODE VOLTAGE OUTPUT 817

Fig. 1. Neutral-point inverter with output filter and fourth pole added.

transient, and common-mode voltage performance are also

demonstrated.

II. P ROBLEM OF C OMMON -M ODE V OLTAGE

Common-mode voltage is the sum of the voltages produced
at each power line of a switching power converter measured
with respect to some common point, usually ground. The
production of common-mode voltage is an inherent problem
with power inverters, as has been reported [3], [4], and is a by-
product of the method by which ac voltages are synthesized
from a dc voltage by force-commutated switches, such as
IGBTs or MOSFETs. If the inverter is producing a voltage that
is applied to a motor, this common-mode voltage is a key con-
tributor to the mechanisms which cause bearing failure [5], [6].
If an active rectifier is being implemented or the inverter is
producing or contributing to the voltage on an ac bus, then the
common-mode voltage is a major contributor to conducted EMI
into the grid [7].
Increasingly, dc-to-ac inverters are being proposed to provide
three-phase power to the power grid such as in dc microgrid
systems where a renewable energy source feeds a dc bus and
power from this dc bus is distributed to ac loads through a dc-to-
ac inverter, which also provides a connection to a utility power
grid [8]. Similar systems are being developed for shipboard
integrated power systems [9] and for distributed industrial
power networks [10].
The production of common-mode voltage introduces addi-
tional complications in these types of systems because they in-
variably provide power to a large number of existing loads that
were traditionally fed by sine-wave ac power measured from
both line-to-line and from line-to-ground. The common-mode
voltage can have a very undesirable impact on the voltage-
to-ground stresses applied to the ac loads connected to a dc-
to-ac inverter fed bus, particularly in a floating system, which
maintains electrical isolation between each of the dc bus power
lines and earth ground. Such a floating system is often required
in order to improve fault tolerance.
Fig. 2. DC microgrid system.
This problem of voltage-to-ground stress at the loads is
illustrated by consideration of the dc microgrid system shown
in Fig. 2, where the dc-to-ac inverter consists of a three-phase
NPC inverter with a sine-wave differential mode output filter
(similar to the output filter of Fig. 1). The line-to-line voltage
applied to the ac bus, to which the loads are connected, will
be sinusoidal, but the line-to-ground voltage applied to the
loads will have a common-mode voltage riding on top of it
which causes additional voltage stress for which the load insu-
lation system is usually not designed. The problem is further
compounded by any capacitance to ground that exists at the
load, which when combined with cable inductance between
the source and load can excite a resonance and result in am-
plification of voltage to ground seen at the load. Simulated
voltage to ground at the load is shown in Fig. 3. This additional
voltage stress can lead to insulation breakdown at the loads,
and redesign of the loads to accommodate the higher voltage-
to-ground stresses would be a costly and prohibitive alternative.
Previous work has looked at constraining the switch states
so that no common-mode voltage is produced. In a three-phase
818 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 45, NO. 2, MARCH/APRIL 2009

Fig. 3. Simulated voltage to ground produced by an NPC inverter with NTV

modulation.
Fig. 4. Switching states of an NPC inverter with ZCM states circled.
two-level inverter, it is impossible to produce an output voltage
without producing common-mode voltage unless an additional
pole is added with an additional power pole [11]. The zero
state produced by the three phases connected to the load is
avoided, and the additional pole selects a switch state that
forces the common-mode voltage to be zero. The additional
pole output can be connected to a common output filter point
(i.e., ground) or fed back to the midpoint of the dc-link through
an inductor. Zero common-mode (ZCM) voltage on a two-level
inverter comes with a serious degradation of the differential
mode voltage because the zero states cannot be utilized [12].
The NPC inverter inherently produces low common-mode
voltage when compared to the two-level inverter and provides
an opportunity to eliminate the common-mode voltage through
proper state selection, without the addition of a balancing pole
[2], [13]. This capability is understood by consideration of
the hexagonal representation of the NPC inverter switch states
shown in Fig. 4. Since a minimum of seven independent states
are only required to produce output voltage, redundant states Fig. 5. Simulated voltage to ground produced by an NPC inverter with ZCM
modulation.
offer opportunities to balance the upper and lower dc-link
voltages and provide improvements to the output waveform Comparing this result to Fig. 3, the voltage-to-ground stress
quality, by enabling an effective doubling of frequency. If due to common-mode voltage is eliminated. The advantages of
only the circled states are utilized, then the NPC inverter will ZCM modulation are emphasized when the voltage-to-ground
produce ZCM voltage. This comes at a cost; however, because stresses that are encountered during a ground fault on the dc bus
the voltage utilization is reduced to 86.6% of the full potential and with capacitance to ground at the load in a floating system
utilization of an NPC inverter (impacting differential mode are compared with nearest three vector (NTV) modulation in
waveform quality), there is no possibility of balancing the dc- Fig. 6.
link voltages, and the frequency doubling effect is effectively
lost. These costs can be acceptable if the following are ob-
III. ZCM V OLTAGE M ODULATION
served: 1) The differential mode performance objectives are
still met (see Section VIII). 2) The application is sensitive to The implementation of the ZCM modulation for an NPC
the presence of common-mode voltage, and the use of some inverter involves utilizing only those states which result in the
other means of mitigation, such as common-mode filtering, is sum of the instantaneous voltages produced by each inverter leg
less advantageous to the application. 3) Some other means is (or pole) adding to zero. For example, the NPC inverter pole
provided to balance the dc-link voltages (see Section V). voltage will be either +Vdc /2, 0, or −Vdc /2, where Vdc is the
Fig. 5 shows the voltage to ground applied to the loads in total dc voltage applied to the inverter. If the phase “a” pole has
the dc microgrid system if a ZCM modulation scheme, which selected the “+1” state, the phase “b” pole has selected the “0”
only allows the circled states of Fig. 4 to be selected, is utilized. state, and the phase “c” state has selected the “−1” state, then
CUZNER et al.: IMPLEMENTATION OF A FOUR-POLE NPC INVERTER WITH LOW COMMON-MODE VOLTAGE OUTPUT
Fig. 6. Simulated voltage to ground produced by an NPC inverter with (left) NTV modulation versus (right) ZCM modulation during a ground fault on the dc
bus, with capacitance to ground at the load.
TABLE I
MAPPING FROM TWO-LEVEL INVERTER SWITCH STATES TO
NPC INVERTER ZCM INVERTER SWITCH STATES
the common-mode voltage is
+Vdc −Vdc
Vcm = +0+ = 0.
6 6
These states are those that are circled in Fig. 4. A simple
implementation of this modulation scheme can be arrived at by
recognizing that only seven distinct switch states are allowed
(the zero states of 000 and 111 are redundant), just as is the case
for a two-level inverter. The two-level inverter allows only the
pole voltages of +Vdc /2 and −Vdc /2 corresponding to switch
states of “+1” or “−1.” A mapping between the seven states
of the two-level inverter to the seven “ZCM” states of the NPC
inverter can be obtained from Table I.
The ZCM modulation can be achieved simply by implement-
ing any two-level modulation scheme which ensures full uti-
lization of the dc bus voltage, such as sine-triangle modulation
with third harmonic injection [14] or space vector modulation
(SVM) [15] and then mapping the two-level states into the
three-level states shown in Table I.
An implementation of ZCM modulation using an SVM ap-
proach is shown in Fig. 7. The dwell times at the two adjacent
819
Fig. 7. SVM implementation mapped into ZCM modulator, Sector 6.
states of a two-level inverter are calculated from the reference
vector, having a magnitude “m,” rotating at the angle γ = ωt,
where “ω” is the commanded output frequency and “m” is
the per-unitized command phase voltage. These dwell times,
T1 and T2 , are then converted to the on times for the NPC
inverter upper–upper device and upper–lower device (Q1 and
Q4 in Fig. 1 for each phase). The three pole voltages and the
conversion of T1 , T2 , and T0 to T1, T2 for all three phases
while in designated Sector 6 are shown in Fig. 8.
Table II shows the mapping of T1 , T2 , and T0 into T1/T2
for all six sectors for the SVM implementation.
IV. D EAD -T IME C OMPENSATION
In an actual inverter, it is impossible to completely achieve
ZCM voltage output because dead time “td” must be allowed
for the transition from one inverter switch state to the next to
avoid device shoot-through. Because the actual transition from
one voltage level to another is delayed by the dead time only
when current commutates from a reverse diode to an IGBT but
occurs instantly during the transition from a transistor conduct-
ing to a reverse diode, an asymmetry is created, which produces
a common-mode voltage even when the ZCM states are com-
manded, as shown in Fig. 9. Unless this let-through of common-
mode voltage during switch commutation is overcome, the
value of a ZCM approach is questionable because although
there may be a reduction in the average voltage-to-ground
820 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 45, NO. 2, MARCH/APRIL 2009

Fig. 8. ZCM-modulated NPC inverter pole voltages in Sector 6.

TABLE II
MAPPING FROM TWO-LEVEL INVERTER T1 , T2 TO
ZCM-MODULATED NPC INVERTER T1, T2
Fig. 9. Actual output pole voltages and common-mode voltage including
dead-time effect for Ia > 0, Ib < 0, and Ic > 0.

TABLE III
DEAD-TIME COMPENSATION FOR T1/T2

stresses applied to the load, significant common-mode filtering

is required, and the cost, size, and weight advantages of the
ZCM approach are lost, even for higher power systems.
Previous work has shown that the effects of dead time can
be compensated by delaying the commutation depending on
the sensed polarity of the output current [16]. Table III shows
how the T1/T2 values are delayed to eliminate the production of
common-mode voltage during switch commutations. The com-
pensated gate commands are shown superimposed on the actual
pole voltages in Fig. 10. The dashed lines show transitions for
the uncompensated commands.
Fig. 10. Commanded voltages with dead-time compensation versus actual
output pole voltages for Ia > 0, Ib < 0, and Ic > 0. Original T1, T2 tran-
V. A DDITION OF F OURTH P OLE sitions overlaid by dashed lines.

A key requirement for any NPC implementation is having utilizing the redundant inner switch states in Fig. 4 [2]. For
the ability to balance the voltage across the upper and lower ZCM modulation, only the outer switch states are utilized, so
dc-link buses in Fig. 1. This is typically accomplished by there are no redundant switch states available.
CUZNER et al.: IMPLEMENTATION OF A FOUR-POLE NPC INVERTER WITH LOW COMMON-MODE VOLTAGE OUTPUT
Fig. 11. Simulated fourth-pole voltage and current (I_4th ) for a 500-kW
design.
In order to address the issue of dc-link balancing, the
topology proposed in Fig. 1 has an additional fourth pole,
with its output tied back to the dc-link midpoint through an
inductor [17]. The fourth pole may be implemented with either
a two-level inverter pole or an NPC inverter pole as shown,
depending on the need to control the voltage stress on the
devices. The fourth-pole control is accomplished by measuring
the difference between the upper and lower dc-link voltages
and then commanding either upper devices or lower devices
depending on whether charge must be pulled out of upper
or lower dc link capacitors in order to maintain the balance.
One way to accomplish this is through a delta modulator, as
shown in Fig. 12, which commands either upper devices or
lower devices to be on depending on the voltage error at each
switching frequency period. Fig. 11 shows the simulated fourth-
pole voltage (referenced to the neutral) and the fourth-pole
current. The key to neutral balancing is to use the current I_4th
in the fourth-pole inductor of Fig. 1 to drive the error between
the upper and lower voltages to zero. The controlled current
has a third harmonic of the fundamental component along with
a switching frequency component, as shown in Fig. 11.
When the fourth-pole inductance and switching frequency of
the additional inverter leg are optimized, the fourth-pole current
rating will be approximately 50% of the output current rating.
From a size and weight standpoint, the optimal point is found
by increasing the fourth-pole inductance to the point where the
fourth-pole current controlled to a minimum value and the LI
product of the fourth-pole inductor has reached a global mini-
mum over the range of inductance values, achievable switching
frequencies and control gains.
VI. S IZE AND W EIGHT I MPACTS
An important consideration is whether it will be more ad-
vantageous to utilize common-mode filtering either with a
two-level inverter or with an NPC inverter that utilizes all
of its states rather than to utilize the ZCM modulation along
with the additional hardware and control as proposed in this
paper. This approach is best applied where the common-mode
conducted emission limits extend to a range that includes low-
order harmonics of the switching frequency, such as the CE102
requirements of Mil-Std-461E where the low-end frequency is
821
TABLE IV
SIZE AND WEIGHT COMPARISONS OF FOURTH-POLE COMPONENTS
WITH EMI FILTER COMPONENTS
10 kHz. In order to meet the conducted EMI requirements,
it is necessary to include a second-order common-mode filter
(common-mode inductor with capacitors tied either to chassis
or some return point within the inverter). The main driver to the
size of the EMI filter is the common-mode current produced by
the inverter. Since the common-mode current of the proposed
topology is essentially zero and minimal EMI is produced
in the switching frequency range (assuming that dead-time
compensation is implemented), this EMI filter is not needed.
On the other hand, it is recognized that some EMI filtering will
be required for higher frequencies due to switch commutation;
however, these higher frequencies would not be handled well by
the EMI filter for the conventional two-level or NPC inverter,
so it may be assumed that a second-stage EMI filter would be
required.
Given these assumptions, a determination is made of the
achievable size and weight reduction by comparing the size and
weight of the added fourth-pole inductor, fourth inverter leg,
and associated controls to the size and weight of an EMI filter.
These comparisons were made based on actual designs and
procured hardware for a 250-kW system that is presently being
built. Size and weight of components at other kilowatt levels
were scaled from this design. Table IV shows a comparison
between the size and weight of the added components for the
proposed topology versus EMI filter components that would
otherwise be required. It is clear that this topology is more
beneficial from a size standpoint at power ranges above 100 kW.
The reason for this is that a reasonable assumption that switch-
ing frequency can be doubled for the 100- and 75-kW appli-
cations is made, which allows for a smaller EMI filter. The
anomaly of low improvement in weight at the 100-kW rating
is due to the assumption that the capacitance of the EMI filter
and the control hardware of the proposed topology remain fixed
for all power levels. The result shows that at some point, the
weight, in particular, of the required additional components is
balanced out by the weight of the EMI filter components. The
results of Table IV indicate that the proposed topology is more
advantageous for higher power inverters and is probably not the
best option for lower power inverters.
VII. C ONTROL I MPLEMENTATION
The control block diagram for the system is shown in Fig. 12.
The control is implemented on a hardware platform which
822 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 45, NO. 2, MARCH/APRIL 2009
Fig. 12. Control block diagram.
utilizes an AD 21160 DSP for computational algorithms and
a Xilinx XC2V3000 FPGA for logical operations and gate
synthesis. Control blocks that are implemented by the FPGA
are indicated by light-gray blocks. All other blocks shown are
implemented by the DSP. The software was programmed so that
two kinds of control could be investigated.
The first type of control is a cascaded outer loop voltage
regulator with an inner loop current regulator. The components
of the inner loop current regulator are shown to be highlighted
by the light-gray box in Fig. 12.
Both of these regulators are implemented in the synchro-
nous frame, i.e., the three-phase voltages and currents are
transformed from stationary “abc” frames to “dq” frames
that are synchronous with the instantaneous electrical angle
derived from the commanded frequency. The q-axis voltage
corresponds to the peak output phase voltage of the dc-to-
ac inverter. The q-axis and d-axis current commands to the
inner loop current regulator correspond to the real and reactive
currents, respectively, that must be delivered to the load in
order to satisfy the outer loop voltage regulator. The inner loop
current regulator also includes load decoupling, which has the
measured load currents in the dq reference frame multiplied by
a gain Ko (close to unity) and added to the current regulator
references. These are required to improve the voltage transient
response of the cascaded regulator.
The voltage and current feedbacks used in the controller are
sampled and averaged eight times over one 100-μs interval.
This greatly improves the differential mode output harmonic
performance of the inverter. The “Reg Select” block in Fig. 12
shows how the two types of regulators are selected. If the
“voltage-regulator-only” mode is selected, then the outputs
from which “m” and “γ” are constructed come directly from
the “PI Reg” blocks of the outer loop voltage controller.
If the “cascaded voltage regulator with inner loop current
regulator” is selected, then the outputs of the inner loop current
regulator form “m” and “γ.” The block diagram also shows
how the ZCM modulator, dead-time compensator, and fourth-
pole controller are implemented.
VIII. E XPERIMENTAL R ESULTS
The experimental setup is shown in Fig. 13. The hardware
includes two parallel multiuse H-bridge power electronic mod-
ules which implement the four-pole three-phase NPC inverter
of Fig. 1. The input to this system was a 12-pulse transformer
rectifier. All experimental results are at a 78-kW output power
condition, limited only by the available power source. Fig. 14
shows the input dc line-to-ground voltage from the dc source,
the input dc line-to-line voltage, the output voltage measured
from one output phase to the neutral point (i.e., midpoint of
CUZNER et al.: IMPLEMENTATION OF A FOUR-POLE NPC INVERTER WITH LOW COMMON-MODE VOLTAGE OUTPUT 823

Fig. 13. Test setup.

Fig. 15. Voltage from line to neutral (VLN ) NPC inverter with ZCM modula-
tion, no dead-time compensation, 200 V/Div.

Fig. 14. (Top trace) Input voltage to ground of source Vs_g , (second trace)
line to neutral voltage VLN , (third trace) input voltage Vdc , and (bottom trace)
fourth-pole current I_4th . Note: Volt/Div and A/Div are shown at the bottom. Fig. 16. VLN (zoomed in) without dead-time compensation.

the dc link), and the fourth-pole current. These plots establish

the fact that the voltage to ground and differential voltage
ripple of the input source do not significantly affect the out-
put results and that the fourth-pole current is as predicted in
Fig. 11. This fourth-pole current has a strong low-frequency
component at the third harmonic of the commanded differential
mode output fundamental frequency. The fact that the capacitor
current ripple in an NPC inverter is at the third harmonic of
the fundamental is well known [2], and it should therefore be
no surprise that the current required by the fourth leg of the
inverter to drive the upper and lower dc-link voltages is also
at the third harmonic. The third harmonic current of the fourth
pole has no impact on the differential mode output voltages of
the inverter. It should be noted that the fourth pole has not been
optimized. The implementation shows only proof of concept.
Fig. 15 shows the voltage measured from one output phase to
the neutral (VLN ). For the experimental setup, this was a good
Fig. 17. VLN (zoomed in) with dead-time compensation.
point to use in order to evaluate the ZCM voltage effectiveness.
Although, from a system perspective, the voltage to ground
is important, a voltage-to-ground measurement would not, as to be sorted out. Because the system includes a second-order
effectively, measure this effect because the impact of stray differential mode output filter having a bandwidth of about
capacitance to ground in the experimental setup would need 600 Hz, the differential mode voltage is essentially sinusoidal
824 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 45, NO. 2, MARCH/APRIL 2009

Fig. 18. Line-to-line voltage (VLL ) spectrum, with outer loop voltage Fig. 19. Line-to-line voltage (VLL ) spectrum, with outer loop voltage regula-
regulator/inner loop current regulator. tor only.

(the switching frequency is 2.5 kHz). Any switching frequency

components in VLN in Fig. 15 are then produced by the
common-mode voltage. Disturbances to the otherwise sinu-
soidal voltage occur at each commutation interval where dead
time introduces an asymmetry. Fig. 16 shows the common-
mode voltage of Fig. 15 zoomed in, which has the dead-time
compensation disabled. Fig. 17 shows the same with the dead-
time compensation enabled. A comparison between these two
plots demonstrates that the remaining common-mode voltage is
indeed a result of the blanking time between switch states. Their
effect, and the amplitude of resulting high-frequency content
during the switch state change, is reduced significantly—by
nearly a factor of three—through the introduction of dead-
time compensation (see Table III). However, the common-mode
voltage is not completely eliminated due to the overlap of
voltage that occurs during the commutation sequences of the Fig. 20. Output voltage (VLL ) and current (IL ) during load application
three-phase output voltages. transient, 200 V/Div and 50 A/Div, respectively.
The remainder of the experimental results focuses on op-
timizing the differential mode performance of the system. harmonic is introduced by sensor errors in the current feedbacks
The system produces a three-phase 450-V 60-Hz output with used for the inner current loop of the cascaded regulator.
a dc input voltage of 800 V. This input voltage is higher Fig. 19 shows the output voltage spectrum if “voltage regula-
than is absolutely necessary with a normal NTV-controlled tor only” is selected. Note that the harmonic content is signifi-
NPC inverter or even a two-level inverter due to the fact that cantly reduced with the third harmonic eliminated altogether.
the ZCM modulator only has 86.6% voltage utilization. Still, Comparison between Figs. 18 and 19 demonstrates that the
the experimental results demonstrate that adequate differential cascaded regulator produces an output with poorer waveform
mode performance can be achieved. The key is to implement quality for a given dc input voltage. Therefore, a control
an output controller that most effectively utilizes the available implementation with only an outer voltage loop is preferable
voltage. when combined with the ZCM modulator. The need to handle
Fig. 18 shows the voltage spectrum of the output line-to- transient output fault currents can be handled in another way,
line voltage (VLL ) with the “cascaded voltage regulator with such as by pulse-by-pulse current limiting.
inner loop current regulator.” The power quality objective for Finally, Figs. 20 and 21 show the output voltage and current
the applications being considered for this converter is that the of the system during step load application and removal with
maximum IHD would be 40 dB down from the fundamental and the control configured as “voltage regulator only.” The transient
that the THD is less than 3%. This objective was achieved. The response is very good, and the penalty here for ZCM voltage
most troublesome harmonics are the third, fifth, and seventh. production is not significant.
The fifth and seventh harmonics are due to the fact that the
ZCM modulator only has 86.6% of the dc input to work with
IX. C ONCLUSION
in producing the dynamic voltage required by the regulator to
control output voltages to the desired levels. These harmonics This paper has demonstrated the successful implementation
can be eliminated if the dc-link voltage is increased. The third of a three-phase NPC inverter that produces ZCM voltage.
CUZNER et al.: IMPLEMENTATION OF A FOUR-POLE NPC INVERTER WITH LOW COMMON-MODE VOLTAGE OUTPUT
Fig. 21. Output voltage (VLL ) and current (IL ) during load application
transient, 200 V/Div and 50 A/Div, respectively.
Nearly sinusoidal voltage is produced from each line to a
common point without the need for an additional EMI filter.
With the addition of dead-time compensation, the only sig-
nificant component of common-mode voltage associated with
power semiconductor switching is due to the IGBT rise and
fall rates.
The proposed inverter system is more compatible with ap-
plications such as dc microgrid systems, and shipboard and
electrical distribution systems where the inverter is the source
of power and should not be a significant contributor to system
EMI. This approach also significantly reduces the voltage-to-
ground stresses that would otherwise be applied to loads in
these systems without the need of EMI filtering. This results in a
significant cost, size, and weight for systems of the power levels
being considered. Furthermore, this paper fully addresses the
tradeoffs that occur in achieving the desired differential mode
performance and demonstrates good steady-state harmonic and
transient performance on actual hardware, even with the in-
herent drawbacks in voltage utilization introduced by ZCM
modulation.
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2008/151145 A1, Dec. 11, 2008.
Rober M. Cuzner (M’90–SM’05) received the B.S.
degree in electrical and computer engineering from
Brigham Young University, Provo, UT, in 1988, and
the M.S. degree in electrical and computer engi-
neering from the University of Wisconsin, Madison,
in 1990.
He has 20 years of experience working in power
generation, power conversion, and drive system con-
trols and packaging for both Navy and industrial
applications. He is currently with DRS Power and
Control Technologies, Milwaukee, WI. His research
interests include microgrid protection, distributed generation, power electronics
for power distribution and drive systems, low- and medium-voltage power
conversion system design, high power density packaging of power electronics,
and electric machine design.
Ashish R. Bendre (S’01–M’03) received the Ph.D.
degree in electrical engineering from the University
of Wisconsin, Madison, in 2003, and the M.B.A.
degree from the University of Chicago, Chicago, IL,
in 2008.
He has over 12 years of industrial power converter
design and development experience, primarily with
Pillar Technologies and SoftSwitching Technologies.
He is currently the Director of Research and Devel-
opment for DRS Power and Control Technologies,
Milwaukee WI, where he manages and conducts
research that has focused on naval power conversion. He has authored or
coauthored over 30 journal and conference papers. His primary areas of interest
include power electronics and control design for multilevel converters, dc–dc
converters, and power quality devices.
826 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 45, NO. 2, MARCH/APRIL 2009
Peter J. Faill received the B.S. degree in physics and
mechanical engineering from Columbia University,
New York, NY, in 1987, and the M.S. degree in
theoretical physics from Tufts University, Medford,
MA, in 1992.
He has over 20 years of digital controls design and
development experience, both in semiconductor tool
manufacturing and in PM motor/generator controls.
He is currently a Switching Topologist with DRS
Power Systems, Hudson, MA, where he develops
and implements a wide range of device switching
schemes for PM machines and power conversion.
Boris Semenov (M’90) received the B.Sc. and M.S.
degrees in electrical engineering from St. Petersburg
State Technical University, St. Petersburg, Russia,
in 1982.
He has over 20 years of industrial power converter,
motor drive design, and development experience. In
the past, he was with Ametek, Otis Elevator Com-
pany, and International Rectifier. He is currently with
DRS Power Systems, Hudson, MA, working on the
development and design of high-power conversion
equipment. His primary areas of interest are in power
electronics, high-performance ac drives, intelligent power management, and
power systems.