ERPINA SATYA RAVITEJA

LinkedIn:https://www.linkedin.com/in/erpina-satya-raviteja-74660b80/ |Phone: +1 971-386-9584| Email:

erpina@pdx.edu

OBJECTIVE

Seeking Internship in RTL Design, ASIC/Digital Design, Verification, validation for 3 to 12 months from December, 2017

EDUCATION:

 M.S Electrical and Computer Engineering (Expected to complete by December,2018) GPA: 4/4
Portland State University, Portland, Oregon.
 Courses: Digital Integrated Circuits-1 (A) Microprocessor System Design (A)
ASIC Modelling and Synthesis (A) System Verilog (Current)
Computer Architecture (A) Neural Networks-1 (Current)
 B.TECH Electronics and Instrumentation Engineering, Amrita University, India (2010-2014) GPA: 3.7/4
o Relevant Courses: Digital Logic Design, VLSI, Microcontrollers and Applications, Analog Design

TECHNICAL SKILLS

 RTL Design and Verification: Verilog HDL, System Verilog, System Verilog Assertions
 Programming : C,C++, Tcl, Phyton, LabVIEW, Matlab
 Hardware: Transistor Schematic and Layout Design (Virtuoso, Cadence),
RTL Design, RTL Debug (QuestaSim), Digital Logic Design, Logic Optimization,
Timing Analysis (Synopsys Design Compiler), Analog Circuit Design and Simulation(SPICE),
Board Test and Debug, Veloce Emulator
 Architectures: PDP-11, MIPS
 Operating System: Linux, Windows

EXPERIENCE

ELECTRONICS DESIGN ENGINEER, UTC AEROSPACE SYSTEMS, BANGALORE, INDIA July 2014- Dec, 2016

 Design of Vision System- NI PXIe, LabVIEW Feb, 2016-Dec,2016

o Designed a Smart Camera and NI Vision Development Module based Vision System that detects faults of LEDs present
on a UUT which is undergoing Environmental Stress Screening Test
 Design of Windshield Ice Protection Controller Test Equipment-NI PXIe, LabVIEW Mar,2015-Jan,2015
o Designed an Automated test equipment for Windshield Ice Protection Controller (Used in various platforms) using NI
PXIe platform and LabVIEW

TECHNICAL PROJECTS

 Implementation of Simulator for PDP-11 Processor- System Verilog Spring,2017

o Designed a Simulator that reads ASCII code, executes the instructions and generate a trace file
o Generated a branch trace file based on memory accesses
 Simulation of 8-Way Set Associative Cache – C Spring, 2017
o Designed a 16MB, L3 cache that uses 64 byte lines which can be accessed by 4 processors
o Used LRU replacement policy and MESI protocol to ensure cache coherence
 Design and Simulation- System Verilog Winter,2017
o Designed a real time traffic light controller to control vehicle and pedestrian signals
o Designed an artificial pacemaker that monitors and controls heart contractions
 Compilation and Optimization strategies- Synopsys Design Compiler Winter,2017
o FIFO Design
o Employed various compile and optimization strategies to generate netlist
 Digital Standard Cell Characterization- Cadence Virtuoso Winter,2017
o Designed an Inverter, AOI, Sea of gates in 50nm CMOS technology for various fan-outs
o Calculated delays and validated using DRC, LVS reports.

PUBLICATIONS

Stock Trading Recommender System Based on Temporal Association Rule Mining SAGE Open, April, 2015
 o Our research work as a part of the Motif Discovery in Non-linear Time Series got published as a research paper titled ‘A
Stock Trading Recommender System Based on Temporal Association Rule Mining’ in SAGE Open Journal in the month of
April 2015

HONORS AND ACHIEVEMENTS

INDIAN SCIENCE CONGRESS

o Selected for Indian Science Congress, a National Level Conference and presented our project

MERIT BASED SCHOLARSHIP

o Received scholarship in Bachelors for excelling in studies

SPOT AWARD UTC AEROSPACE SYSTEMS

o Received spot award for significant contribution to WIPC Project

ACTIVITIES

5S |UTC AEROSPACE SYSTEMS

o Registered member of 5S (Lean tool- ACE Operating System) team since February, 2015 in UTC Aerospace Systems,
Bangalore to keep the workplace organized and safe.

TECHNICAL HEAD| ANOKHA, 2014|TECH FEST |ECE |AMRITA UNIVERSITY

o Organized two workshops and five technical events.

VOLUNTEER |YOUTH FOR SEVA

o Volunteer at an NGO called ‘Youth for Seva’, Bangalore

o Taught mathematics and science.