EXPERIMENT NO.

-7
Aim: To design XOR gate using CMOS and Pseudo NMOS technique using CADENCE and
compute the delay between input and output waveforms and compare them.

Tools used: CADENCE Virtuoso.

Theory: XOR gate is a digital logic gate that gives logic true when the number of true inputs
is odd. XOR gate represents inequality function; the output is true if the inputs are not alike
otherwise the output is false.

Application:

 The XOR logic gate can be used as a one-bit adder that adds any two bits together to
output one bit.
 A suitable setup of XOR gates can model a linear feedback shift register, in order to
generate random numbers.

Truth Table: Table 7.1: Truth table of XOR gate.

Input A Input B Output

0 0 0
0 1 1
1 0 1
1 1 0

Fig 7.1: Circuit diagram of a XOR gate using CMOS technique.

 Fig 7.2: Circuit diagram of XOR gate using pseudo NMOS technique.

Circuit Diagram:

Fig 7.3: Circuit diagram of XOR gate using CMOS technique

 Fig 7.4: Test setup for XOR gate using CMOS technique

Fig 7.5: Circuit diagram of XOR gate using pseudo NMOS technique
 Fig 7.6: Test setup for XOR gate using pseudo-NMOS technique

Given Data:

Table 7.2: Simulation setup for XOR gate.

Given specification Values (CMOS tech.) Values ( pseudo-NMOS tech)

(W/L)nmos 2 µm / 180 nm 2 µm / 180 nm
(W/L)pmos 4 µm / 180 nm 4 µm / 180 nm
Vdc 1.8V 1.8V
Vin 0 to 1.8 V 0 to 1.8 V
Input A V1=0 V, V2= 1.8 V, Tf = 1 ns , V1=0 V, V2= 1.8 V, Tf = 1 ns ,
Tr = 1 ns ,Tp = 100ns, Tw = 49 ns Tr = 1 ns ,Tp = 100ns, Tw = 49 ns
Input B V1=0 V, V2= 1.8 V, Tf = 1 ns , V1=0 V, V2= 1.8 V, Tf = 1 ns ,
Tr = 1 ns ,Tp = 50ns, Tw = 24 ns Tr = 1 ns ,Tp = 50ns, Tw = 24 ns
Load Capacitance 1 pF 1 pF

Transient Analysis:-

Table 7.3: Simulated results of XOR gate

Parameter Values (CMOS tech.) Values (pseudo-NMOS tech)

Delay w.r.t A Discharging time=0.965 ns
Charging time= 1.278 ns
Delay w.r.t B Discharging time=0.941 ns
Charging time= 1.274 ns
Average Power Dissipation 42.38 µW
Discharging time=1.358 ns
Charging time= 7.318 ns
Discharging time=1.388 ns
Charging time= 7.289 ns
145.3 µW
Output Waveform:

Fig 7.7: Transient analysis of XOR gate using CMOS tech.

Fig 7.8: Transient analysis of XOR gate using pseudo-NMOS tech.

Result:

We have designed and simulated the XOR gate using CMOS technique and pseudo-NMOS
technique successfully using CADENCE Virtuoso tool. We have calculated the average
power dissipation and worst case delay between the input and output waveforms and
compared their results.