CURRICULAM VITAE

GIRRAJ SINGH TOMAR

#B-85 BANK COLONY,
GOLA KA MANDIR,
GWALIOR (M.P.)
MOB: +91-9009128941
Email Id:-Girraj1545@gmail.com

Objective
To take up a challenging position in a dynamic oriented organization that actualizes my skills and abilities
while providing me with a platform to learn and grow for an organization.

Educational Qualifications
S.NO. Qualification University/Board Division
1. M.Tech.(Embedded System RGTU BHOPAL (M.P.) FIRST
& Vlsi Design)
2. Bechelor of Engineering RGTU BHOPAL (M.P.) FIRST
3. Higher Secondary M.P. Board FIRST

4. High School M.P. Board FIRST

Working Experience
 18 Months Experience in RF Department as Drive TEST Engineer.
 6 + Months Experience in RF Department as Drive Test Engineer.
 6 months as a E-pub developer in novestech Bangalore.

Current Project
 Performing as a DT Linkquest Global Pvt.Ltd. on Vodafone & idea Nokia scft & cluster
project in haryana location and up west location.
 Performing as a DT linkquest Global Pvt. Ltd. On Vodafone BM Project mpcg location.
 Performing as a Drive Test Engineer in TELEYSIA Pvt. Ltd. On VODAFONE 4G at NOKIA
project in GUJRAT location.

Technical Skills
Frameworks -: Struts(2.0,1.0), Hibernate.
Languages -: J2EE( jsp,Servlets),Core java,C.
Database -: Oracle.
Server -: Apache tomcat, Glassfish.
IDE -: Netbeans, Eclipse.
Other Subjects -: Manual testing, DBMS.
Testing tools -: QC, Silk Test,QTP ,Load Runner

Certification
 Completed “Advanced Java with Frameworks” course at Cegonsoft Bangalore.
 Completed “Advanced Software Testing” course at ISM Bangalore.
Paper publications
 Paper Published on “An Efficient Design of Full Adder In Quantum Dot Cellular Automata”
In IJAEGT, Volume – 06, Issue 01, Jan 2018, Dated:- 16-01-2018.

 Paper Published on “A NOVAL MULTI-LOGIC-GATE OPTIMIZATION IN QUANTUM

DOT CELLULAR” In IJAEGT, Volume – 06, Issue 01, Jan 2018, Dated:- 16-01-2018.

Dissertation Work

The full adder circuit is a basic unit in digital arithmetic and logic circuits. In this work an improved
full adder in QCA technology is proposed. This design is considerably declined in terms of cell numbers and
area, compared to other previous full adders and latency is kept at minimum. To design this full adder a
different formulation for sum and carry outputs of full adder has been used.
In the near future, it is expected that the CMOS technology reaches to the end of its road map because of
many serious challenges such as short channel effect, impurity variations, high cost of lithography and more
importantly, the heat. Quantum-dot cellular automata (QCA) are one of the alternative technologies that
enable nanoscale circuit design with high performance and low power consumption features.
Keywords: Quantum-dot cellular automata (QCA). 5-input majority gate. QCADesigner.QCAPro.
Full adder.
Job Function
 Performing For 4G& 3G sites including SCFT.
 Data Drive and swap removal.
 Analysis of drive test files for taking care of External and Internal Interference in the Network. This
involves analysis of RSRP,RSRQ,SINR.
 Handling optimization of new/existing sites and handles problems like Call drop, handover failure,
antenna tilting, reorientation.
 Physical Optimization and Stationary And mobility.
 Antenna Orientation / Tilt changes.
 Check RSRP and quality for good coverage.
 Analysed the Drive test log files using TEMS Investigation. Find the swap, Interference in the sites
during the optimization & resolve the swap ,Soft Handover using drive test data’s.

Personal Strength
 Hard Working, Confident
 Can work effectively in a Group As Well As Single.
 Adaptable in Changing Situations.

Personal Details
Father’s Name : Mr. Sukhadev Singh Tomar
Permanent Address : H.No.267, Shiv Nagar Bhind Road Porsa
MadhyaPradesh-476115.
Date of Birth : 07-08-1989
Language known : English, Hindi.
Declaration
I hereby declare that all statements in this application are true and complete of the best of my knowledge
and belief.
Place: GWALIOR GIRRAJ SINGH TOMAR
Date: