1) A processor is said to operate at 2 GHz clock frequency.

This is equivalent as saying

that the clock cycle of the processor is (answer must be in nanoseconds):
Ans: Clock cycle = 1/f = = 0.5 ns

2) The following assembly instructions are given. Initially registers R1, R2, and R3 have
contents of 50, 3, 1000, respectively. If the rst register is the destination operand, the
next two registers are source operands, and ADD is an opcode for integer addition, what
values in the registers can be expected at the end of the execution of the instructions?

ADD R3, R2, R3

ADD R1, R2, R3
ADD R2, R1, R3
The nal value of R1 is .
The nal value of R2 is .
The nal value of R3 is .

3) Suppose that a machine represents an address using 16 bits. How big is the memory
size that can be addressed?
Group of answer choices

64KB

8KB

16KB

32KB

128KB

4) Suppose that a memory structure is 128 KBytes in size, and is divided into blocks
where each block is 64 bytes. How many bits are needed to address each block?
Group of answer choices

11

12

13

1
 14

5) The following shows a decoder logic with two inputs (A1 and A0) and four outputs
(Y3, Y2, Y1, and Y0). Suppose that enable (E) input is set (to 1 or ON), and A1 is
set while A0 is reset (to 0 or OFF). What would be the output values? Denote each
output as either "0" or "1".

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Output Y3 will be .
Output Y2 will be .
Output Y1 will be .
Output Y0 will be .

6) The following gure shows a multiplexer. Suppose that the selector inputs have the
following values: S0=1 and S1=0. What would be the output O equivalent to?

./media/image4.png

2
 Group of answer choices

D2

D0

D1

D3

7) What is the value of 10101011 XOR 00110101?

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8) The following is a high level diagram of a memory (SRAM) array.

In order to read out the content of the fourth row, what bit values should be input to
Address?

011

010

100

101

9) Compare SRAM with DRAM, and then ll in each answer with either SRAM or
DRAM.
Which of them requires refresh?
Which of them is denser?

3
 Which of them is predominantly used for main memory?
Which of them does not suer from destructive read?
Which of them requires more transistors per cell?

10) What is the result of "1010" concatenated with "1011"?