National Institute of Technology, Raipur, CG- 492010

M.Tech( ETC-VLSI Design and Embedded system) -1st Semester

ET41112VL (ADVANCED VLSI DESGN)
Second Examination (12-OCT-2017 )

Time :01 hr 15min M. Marks: 15

Note: 1) Q1 is compulsory
2) For Q2 and Q3 attempt any one choice.
3) Attempt the questions serially.
4) Assume suitable data wherever necessary Roll No.

Q1. In order to drive a large capacitance (CL= 20 pF) from a minimum size gate (with
input capacitance Ci= 10fF), you decide to introduce a two-staged buffer as shown in
Figure 1. Assume that the propagation delay of a minimum size inverter is 70 ps. Also
assume that the input capacitance of a gate is proportional to its size.

(i) Determine the sizing of the two additional buffer stages that will
minimize the propagation delay.
(ii) If you could add any number of stages to achieve the minimum delay,
how many stages would you insert? What is the delay in this case?
(iii) Compare the power consumption of the methods shown in (a) and (b).

Q2. A CMOS inverter with minimum sized transistors has βn =0.2mA/ V2, βp =
0.1mA/ V2 and Vtn=|Vtp|=0.6V.Assume VDD = 3.3V.
a) What is the inverter gate switching threshold (midpoint) voltage ?
b) What is the resistance for each transistors using our general expression for
MOSFET resistance in saturation?
c) What are the rise and fall times of this circuit if the parasitic capacitance at the
output is 9fF?
d) If a load capacitance, CL = 25fF is added to the output, what are the new rise and
fall times?
e) What are the propagation delays for this circuit considering both parasitic and load
capacitances? (5)
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(ii) Two-input CMOS NAND and NOR gates have been designed with Rn = 1kΩ ,
Rp = 2k Ω , Cout = 8fF, and Cx = 2fF, where Cx is the node capacitance between the
series transistors.
a) Calculate the worst-case rise and fall times for this NAND gate.
b) Calculate the best-case rise time for this NAND gate.
c) Calculate the worst-case rise time for a 2-input CMOS NOR gate. (2,2,1)

Q3. a) Determine the activity coefficient of a 2-input CMOS NOR, NAND and XOR
gate (1.5)
b) Calculate the dynamic power consumption of a 2-input CMOS NOR, NAND and
XOR gate that drives a 12fF output capacitance at 100MHz from a 2V supply. (1.5)
c) If the quiescent (static) current in the NOR gate is 4nA, what percentage of the total
power is due to dynamic power in the NOR gate? (2)
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Briefly, explain the CMOS inverter DC transfer characteristics with appropriate
diagram and highlighting the mode of operation of transistor with the help of voltage
equations. Also, explain the noise margin levels for ideal and practical case. (3,2)