Manual MSE5010

MSE 5010
HARDWARE DESCRIPTION
M5010/EN FT/A11 Version A

TECHNICAL DOCUMENTATION M5010/EN FT/A11
Chapter No (if applicable)
MSE 5010 Page 2/103
MSE 5010
Original signed by Date Name Visa

Established 02/12/02/2004 Monique Wils
Checked 02/12/02/2004 Gwenaelle Secretan
Approved 02/12/02/2004 Vianney Vannson
MSE 5010 REF : M5010/EN FT/A11
VOLUME X (Volume Title) Page 3/103
CONTENTS
1. EQUIPMENT ARCHITECTURE 8
1.1 Board slots 8

2. BOARDS 10
2.1 Classified Board Description 10
2.2 Board Appearance 12
2.3 SL16 13
2.4 SLQ4/SLD4/SL4 17
2.5 SLQ1/SL1 22
2.6 SEP1/EU04/EU08/OU08/TSB8/ TSB4 27
2.7 SPQ4/MU04 33
2.8 PD3/PL3/D34S/C34S 39
2.9 PQ1/PQM/PD1/D75S/D12S/D12B 45
2.10 EGS2 51
2.11 EFS4/EFS0/ETF8 56
2.12 CXL1/CXL4/CXL16 62
2.13 EOW 69
2.14 AUX 72
2.15 PIU Erreur ! Signet non défini.
2.16 FAN 77
3. CABLES 79
3.1 75Ω
Ω E1 Cable 79
3.2 120Ω
Ω E1/T1 Cable 82
3.3 E3/DS3 Cable 85
3.4 Power Cable 86
3.5 PGND Cable 88
3.6 75Ω
Ω Clock Cable 89
3.7 120Ω
Ω Clock Cable 90
3.8 Network Cable 91
3.9 Boolean Input/Output Cable 94
3.10 OAM Serial Port Cable 95
This document is the property of AREVA and must not be used, copied or communicated to parties without authorisation
3.11 S1 ~ S4/F&f Cable 97
3.12 Fiber 98
4. INDICATOR DESCRIPTION FOR EQUIPMENT AND BOARD 99
4.1 Board Indicator Description 99

5. POWER CONSUMPTION AND WEIGHT 101
6. ACRONYMS AND ABBREVIATIONS 102
PAGE BLANCHE ("Blank Page")
MODIFICATIONS PAGE
Version DATE COMMENTS

A 03/02/2004 ORIGINAL ISSUE
1. EQUIPMENT ARCHITECTURE
The MSE 5010 is composed of power supply unit, fan unit, boards and cables, as shown in Fig 1-1.
Fig 1-1 MSE 5010
1.1 Board slots

The slot assignment of the MSE 5010 subrack is shown in Fig 1-2
slot14
slot15 slot18 (PIU)
slot16
slot17 slot19 (PIU)
slot1 slot11 slot6

slot2 slot12 slot7
slot20 slot13
slot3 slot8
(FAN)
slot4 slot9
slot5 slot10 (AUX)
Fig 1-2 Slot assignment of the MSE 5010
Boards and their corresponding slots of the MSE 5010 are shown in Table 1-1.
Board Full name Slot available

SL16 STM-16 optical interface board slot 11~13
SLQ4 4 × STM-4 optical interface board slot 11~13
SLD4 2 × STM-4 optical interface board slot 11~13
SLQ1 4 × STM-1 optical interface board slot 11~13
Board Full name Slot available

SEP1 STM-1 electrical processing board slot 11~13
SPQ4 E4/STM-1 electrical interface board slot 12, 13
PL3 3 × E3/DS3 processing board slot 12, 13
PD3 6 × E3/DS3 processing board slot 12, 13
PQ1 63 × E1 processing board slot 11~13
PQM 63 × E1/T1 processing board slot 11~13
PD1 32 × E1 processing board slot 1, 2, 3, 11, 12,

13, 6, 7, 8
EGS2 2-Port Gigabit Ethernet optical interface slot 11~13

board with Lanswitch
EFS0 Fast Ethernet Interface Board with slot 12~13

Lanswitch
EFS4 4-Port Fast Ethernet processing board slot 11~13

with Lanswitch
CXL16 STM-16 system control, cross-connect, slot 4, 5

optical interface board


AUX System auxiliary process board slot 10
EOW Engineering Order Wire slot 9
Table 1-1 Processing boards and their corresponding slots
2. BOARDS
2.1 Classified Board Description

In terms of functions, boards can be classified into the following types:
SDH interface unit
PDH interface unit
Ethernet interface unit
System control, cross-connect, optical interface board
Engineering Order Wire
Auxiliary interface unit
Power unit
Fan unit
Other functional unit
Table 2-1 shows the corresponding relationship between the functional units and boards.
Unit name Board Full name

SL16 STM-16 optical interface board
SLQ4 4 × STM-4 optical interface board
SLD4 2 × STM-4 optical interface board
SL4 STM-4 optical interface board
SLQ1 4 × STM-1 optical interface board

SDH interface
unit SL1 STM-1 optical interface board
SEP1 8 × STM-1 line processing board
EU04 4 × STM-1 electrical interface board
EU08 8 × STM-1 electrical interface board
OU08 8 × STM-1 optical interface board
PDH interface SPQ4 4 × E4/STM-1 processing board

unit
MU04 4 x E4/STM-1 interface board
PD3 6 × E3/DS3 processing board
PL3 3 × E3/DS3 processing board
C34S 3 × E3/DS3 PDH interface switching board
D34S 6 × E3/DS3 PDH interface switching board
PQM 63 × E1/T1 processing board
PQ1 63 × E1 processing board
PD1 32 × E1 processing board
Unit name Board Full name

D75S 32 × 75Ω E1/T1 PDH interface switching board
D12S 32 × 120Ω E1/T1 PDH interface switching

board
D12B 32 × 75Ω/120Ω E1/T1 PDH interface board
TSB4 4 × PDH interface switching & bridging board
TSB8 8 × PDH interface switching & bridging board
EGS2 2-port Gigabit Ethernet optical interface board

with Lanswitch
EFS4 4-port Fast Ethernet processing board with

Ethernet Lanswitch
interface unit
EFS0 Fast Ethernet processing board with Lanswitch
ETF8 8 x 10/100M Ethernet twisted pair interface

board
CXL16 STM-16 system control, cross-connect, optical

interface board
System control,
cross-connect, CXL4 STM-4 system control, cross-connect, optical
optical interface interface board
board
CXL1 STM-1 system control, cross-connect, optical
interface board
Engineering EOW Engineering Order Wire

Order Wire
System AUX System auxiliary interface board

auxiliary
interface unit
Power unit PIU Power interface unit
Fan unit FAN Fan control unit
Table 2-1 Corresponding relationship between functional units and boards
2.2 Board Appearance

The appearances of some MSE 5010 boards are shown in Fig 2-1.
1. Board name 2.Ejector lever 3. Indicator

4. Front panel 5. PCB
Fig 2-1 The boards appearance
Caution:
Always wear an ESD wrist strap when holding the board, and make sure the
ESD wrist strap is well grounded, thus to prevent the static electricity from
damaging the board.
Warning:
It is strictly forbidden to stare into the optical interface board and the optical
interface, lest the laser beam inside the optical fiber would hurt your eyes.
2.3 SL16
SL16 is the STM-16 optical interface board, responsible for STM-16 optical signal processing.
SL16 can be seated in Slot 11~ 13.
2.3.1 Functions and Principles
2.3.1.1 Functions
Receive/transmit one channel of STM-16 optical signal.

Support VC-4-4c, VC-4-8c, and VC-4-16c concatenated services.
Support I-16, S-16.1, L-16.1, L-16.2 and L-16.2Je optical modules for
different transmission distances.
Support fixed wavelength output, so that it can be connected with the
multiplex unit of WDM equipment directly without using the wavelength
conversion unit.
Support various protection schemes such as two-fiber and four-fiber
bidirectional MSP ring, linear MSP and SNCP.
Support shared optical path protection of MSP ring and SNCP ring, and
that of two MSP rings.
Provide abundant alarm and performance events for convenient
equipment management and maintenance.
Support inloop and outloop at optical interfaces for fast fault location.
Support ALS function, avoiding laser injury to human body during
maintenance.
Support on-line query of the board information and the optical power.
Support configuration of such bytes as D1-D3, D4 -D12 (DCC), E1
and E2 (ECC) to transparent transmission or into other unused
overhead bytes.
Support smooth software upgrade and expansion.
2.3.1.2 Principles
Fig 2-2 shows the functional diagram of SL16.
Active cross-
Data and connect board
1 x STM-16 Interface SDH signal
clock
optical signal unit processing
recovery
unit Standby cross-
unit
connect board
Overhead Control and

Timing unit
processing unit communication unit
SCC
Overhead bus
Cross-connect
Clock signal and timing unit
Power module -48V
Fig 2-2 Functional diagram of SL16
The STM-16 optical signal is accessed at the interface unit and sent to the SDH signal processing unit after data
and clock signal extraction at data and clock recovery unit. The SDH signal processing unit implements frame
search, SOH termination and insertion, overhead byte extraction, pointer justification and POH monitoring to the
incoming signals and then sends them to overhead processing unit for further processing. After that, the signals are
re-timed with the system clock, and then multiplexed into 622M data signals after cross-connect and finally sent to
the cross-connect and timing unit.
The timing unit extracts the clock signal at line side and receives system clock and frame header from the active
and standby cross-connect boards. It also provides clock signal for other modules on the board. The control and
communication unit mainly functions control, communication and service configuration of the board. The power
module provides all modules of the board with DC power supply with required voltage.
The overhead processing unit extracts the overhead bytes from the one channel of overhead signal it receives, and
sends the extracted bytes to SCC and its paired board through the overhead bus according to related sequence
and clock requirements. In transmit direction, the overhead processing unit re-arranges the received overhead
signals from SCC or its paired board and then inserts them into the SOH.
2.3.2 Front Panel

The front panel of SL16 is shown in Fig 2-3.
Fig 2-3 The front panel of SL16
The indicator of SL16 is shown in Table 2-2
Color and
Indicator Description
status
On, green The board works normally.
On, red The board hardware fails.
On for 100ms The board hardware is mismatched.

Board and off for
hardware
100ms
indicator-STAT
alternatively,
red
Off The board is not powered on, or the

service is not configured.
Service On, green The service is activated.

activation
indicator-ACT Off The service is not activated.
On, green Upload of board software to FLASH or the

FPGA upload is normal, or the board
software initialization is normal.
On for 100ms Board software is being uploaded to

Board software and off for FLASH or FGPA
indicator- 100ms
PROG alternatively, The board software is initializing, and is in
green BIOS boot stage.
The board software in FLASH or the FPGA

Board software On, red configuration is lost, resulting in upload
indicator- and initialization failure.
PROG
Off No power supply.
Color and
status
On, green Service is normal, no service alarm occurs.
Service alarm On, red Critical or major alarm occurs to service.

indicator-SRV
On, yellow Minor or remote alarm occurs to service.
Off No service configured or no power supply.
Table 2-2 The indicator description of SL16
2.3.3 Interface
The optical interface of SL16 is LC.
2.3.4 Board Configuration

Before using SL16 for running service, parameters should be set for it through NM.
Configuration should be provided to the following bytes for the line board:
J1
J1 is the path trace byte. Successive transmission of the higher order access point identifier through J1 at the
transmit end helps the receive end learn that its connection with the specified transmit end is in continuous
connection status. When J1 mismatch is detected at receive end, the corresponding VC-4 path will generate HP-
TIM alarm.
C2
C2 is the signal label byte, indicating the multiplexing structure of VC-4 frame and the payload property. It is
required that the C2 bytes transmitted matches those received. Once mismatch is detected, the corresponding VC-
4 path will generate HP-SLM alarm and insert all “1”s into the C4 in downstream stations.
2.3.5 Technical Parameters
Description
Parameter
SL16
Rate 2488320kbit/s
Processing Process 1 × STM-16 standard service or concatenated

capability service
Line code NRZ

pattern
Connector LC
Size (mm) 262.05 × 220 × 25.4
Weight (kg) 1.100
Power 20
consumption
(W)
Optical module I-16 S-16.1 L-16.1 L-16.2 L- V- U-

type 16.2Je 16.2Je 16.2Je
Wavelength 1310 1310 1310 1550 1550 1550 1550

(nm)
Description
Parameter
SL16
Transmission 0~2 2~15 15~40 40~80 80~10 80~14 140~1
distance (km) 0 0 70
Launched -10 ~ - -5 ~ 0 -2 ~ 3 -2 ~ 3 5~7 NA NA

power (dBm) 3
Receiver -21 -21 -30 -30 -31.5 -31.5 -38

sensitivity
(dBm)
2.4 SLQ4/SLD4/SL4
SLQ4 is the 4 × STM-4 optical interface board; SLD4 is the 2 × STM-4 optical interface board; SL4 is the 1 × STM-
4 optical interface board. All are responsible for STM-4 optical signal processing.
Table 2-3 shows the difference between these three optical interface boards.
Comparison SL4 SLD4 SLQ4

Processing 1 × STM-4 2 × STM-4 4 × STM-4
capability
Slot available Slot 11 ~ 13 Slot 11 ~13 Slot 11 ~ 13
Table 2-3 Comparison between SLQ4, SLD4 and SL4
2.4.1.1 Functions
SLQ4, SLD4 and SL4 can access and process 4, 2 and 1 × STM-4
optical signal respectively.
Support VC-4-4c concatenated services.
Support I-4, S-4.1, L-4.1, L-4.2 and Ve-4.2 optical interfaces for
Support various protection schemes such as two-fiber and four-fiber
bidirectional MSP, linear MSP, and SNCP.
maintenance.
Support on-line query of the board information.
Support configuration of such bytes as D1-D3, D4-D12 (DCC), E1 and
E2 (ECC) to transparent transmission or into other unused overhead
bytes.
2.4.1.2 Principles
Fig 2-4 shows the functional diagram of SLQ4/SLD4/SL4.
Active cross-
4/2/1 x STM-4 Interface SDH signal
clock
recovery
unit Standby cross-
unit
connect board

Timing unit
SCC
Overhead bus
Cross-connect
Power module -48V
Fig 2-4 Functional diagram of SLQ4/SLD4/SL4
The 4/2/1 × STM-4 optical signals are accessed at the interface unit and sent to the SDH signal processing unit
after data and clock signal extraction at data and clock recovery unit. The SDH signal processing unit implements
frame search, SOH termination and insertion, overhead byte extraction, pointer justification and POH monitoring to
the incoming signals and then sends them to overhead processing unit for further processing. After that, the signals
are re-timed with the system clock, and then multiplexed into 622M data signals after cross-connect and finally sent
to the cross-connect and timing unit.
The overhead processing unit extracts the overhead bytes from the two channels of overhead signals it receives,
and sends the extracted bytes to SCC and its paired board through the overhead bus according to related
sequence and clock requirements. In transmit direction, the overhead processing unit re-arranges the received
overhead signals from SCC or its paired board and then inserts them into the SOH.
2.4.2 Front Panel

The front panel of SLQ4, SLD4 and SL4 is shown in Fig 2-5, and the indicator description is shown in Table 2-4
Fig 2-5 Front panel of SLQ4, SLD4 and SL4
Indicator Color and status Description

Board On, red The board hardware fails.

hardware On for 100ms and The board hardware is mismatched.
indicator- off for 100ms
STAT
alternatively, red
Off The board is not powered on.
Service On, green The service is activated, and the board is

activation in operation.
indicator- Off The service is not activated, and the board
ACT can be swapped.

On for 100ms and Board software is being uploaded to

off for 100ms FLASH or FGPA
alternatively,
Board green
software
On for 300ms and The board software is initializing, and is in
indicator-
off for 300ms BIOS boot stage.
PROG
alternatively,
green
On, red The board software in FLASH or the

FPGA configuration is lost, resulting in
upload and initialization failure.
On, green Service is normal, no service alarm

occurs.
Service
alarm On, red Critical or major alarm occurs to service.
indicator-
SRV On, yellow Minor or remote alarm occurs to service.
Off No service is configured.
Table 2-4 description of SLQ4, SLD4 and SL4
2.4.3 Interface
SLQ4, SLD4 and SL4 provide LC optical interfaces.

Before using SLQ4, SLD4 and SL4 for running service, parameters should be set for it through NM.
J1
TIM alarm.
C2
Description
Parameter
SLQ4 SLD4 SL4
Rate 622080kbit/s
Processing 4 × STM-4 2 × STM-4 1 × STM-4

capability
Line code NRZ

pattern
Connector LC
Size (mm) 262.05 × 220 × 25.4
Weight (kg) 1.036 1.032 1.030
Power 16 15 14.5
consumption
(W)
Optical module I-4 S-4.1 L-4.1 L-4.2 Ve-4.2

type
Wavelength 1310 1310 1310 1550 1550

(nm)
Transmission 2~15 2~15 15~40 40~80 80~100

distance (km)
Launched -15 ~ -8 -15 ~ -8 -3 ~ 2 -3 ~ 2 -3 ~ 2

power (dBm)
Received -31 -31 -30 -30 -33

sensitivity
(dBm)
2.5 SLQ1/SL1
SLQ1 is the 4 × STM-1 optical interface board;
SL1 is the 1 × STM-1 optical interface board.
Both are responsible for STM-1 optical signal processing
Table 2-5 shows the difference between these two optical interface boards.
Comparison SL1 SLQ1

Processing capability 1 × STM-1 4 × STM-1
Slot available Slot 11 ~ 13 Slot 11 ~ 13
Table 2-5 Comparison between SLQ1 and SL1
2.5.1.1 Functions
SLQ1 and SL1 access and process four and one channel of STM-1
optical signal respectively.
Support Ie-1, I-1, S-1.1, L-1.1, L-1.2 and V-1.2 optical interfaces for
Support various protection schemes such as two-fiber unidirectional
MSP, linear MSP and SNCP.
maintenance.
Support configuration of such bytes as D1-D3, D4-D12 (DCC), E1 and
E2 (ECC) to transparent transmission or into other unused overhead
bytes.
2.5.1.2 Principles
Fig 2-6 shows the functional diagram of SLQ1/SL1.
Active cross-
4/1 x STM-1 Interface SDH signal
clock
recovery
unit Standby cross-
unit
connect board

Timing unit
SCC
Overhead bus
Cross-connect
Power module -48V
Fig 2-6 Functional diagram of SLQ1/SL1
The 4/1 × STM-1 optical signals are accessed at the interface unit and sent to the SDH signal processing unit after
data and clock signal extraction at data and clock recovery unit. The SDH signal processing unit implements frame
search, SOH termination and insertion, overhead byte extraction, pointer justification and POH monitoring to the
incoming signals and then sends them to overhead processing unit for further processing. After that, the signals are
re-timed with the system clock, and then multiplexed into 622M data signals after cross-connect and finally sent to
the cross-connect and timing unit.
2.5.2 Front Panel

The front panel of SLQ1 and SL1 is shown in Fig 2-7, and the indicator description is shown in Table 2-6
Fig 2-7 Front panel of SLQ1 and SL1

Board On, red The board hardware fails.

hardware The board hardware is mismatched.
On for 100ms and
STAT alternatively, red
Service On, green The service is activated, and the board

activation is in operation.
indicator- Off The service is not activated, and the
ACT board can be swapped.
On, green Upload of board software to FLASH or

the FPGA upload is normal, or the
board software initialization is normal.

alternatively,
Board green
software
On for 300ms and The board software is initializing, and is
indicator-
off for 300ms in BIOS boot stage.
PROG
alternatively,
green


occurs.
Service
indicator- On, yellow Minor or remote alarm occurs to
SRV service.
Table 2-6 Indicator description of SLQ1 and SL1
2.5.3 Interface
The interface of SLQ1 and SL1 is LC.

using SLQ1 and SL1 for running service, parameters should be set for it through NM.
J1
TIM alarm.
C2
Description
Parameter
SLQ1 SL1
Rate 155520kbit/s
Processing 4 × STM-1 1 × STM-1

capability
Line code NRZ

pattern
Connector LC
Size (mm) 262.05 × 220 × 25.4
Weight (kg) 1.036 1.030
Power 15.5 14
consumption
(W)
Optical module I-1 S-1.1 L-1.1 L-1.2 Ve-1.2

type
Wavelength 1310 1310 1310 1550 1550

(nm)
Transmission 2~15 2~15 15~40 40~80 80~100

distance (km)
Launched -15 ~ -8 -15 ~ -8 -5 ~ 0 -5 ~ 0 -3 ~ 2

power (dBm)
Received -31 -31 -34 -34 -34

sensitivity
(dBm)
2.6 SEP1/EU04/EU08/OU08/TSB8/ TSB4
SEP1 is the 8 × STM-1 line processing board, with two STM-1 electrical interfaces on the front panel.
EU08 is the 8 × STM-1 electrical interface board;
EU04 is the 4 × STM-1 electrical interface board;
OU08 is the 8 × STM-1 optical interface board;
TSB8 is the 8 × PDH interface switching & bridging board; and
TSB4 is the 4 × PDH interface switching & bridging board.
Table 2-7 shows the differences between SEP1, EU04, EU08, OU08, TSB8 and TSB4.
Board Boards equipped Function

None Accessing and processing 2 x STM-1 electrical signal
EU08 Accessing and processing 8 x STM-1 electrical signal
EU04 Accessing and processing 4 x STM-1 electrical signal
SEP1 OU08 Accessing and processing 8 x STM-1 optical signal
EU08 and TSB8 Accessing and processing 8 x STM-1 electrical signal, realizing the 1:1
EPS to SEP1 board.
EU04 and TSB4 Accessing and processing 4 x STM-1 electrical signal, realizing the 1:1
EPS to SEP1 board.
Table 2-7 Comparison between SEP1, EU04, EU08, OU08, TSB8 and TSB4
2.6.1.1 Functions
SEP1 can process 8 × STM-1 services.

Support various protection schemes such as linear MSP, MSP and
SNCP.
maintenance.
Support configuration of such bytes as D1-D3, D4 –D12, (DCC), , E1
overhead bytes.
2.6.1.2 Principles
The functional diagram of SEP1 and TSB8 is shown in Fig 2-8 and Fig 2-9 respectively.
Active cross-
2/4/8 x STM-1 Data and connect board
SDH signal
optical/electrical Interface clock
unit recovery processing
signals
unit unit Standby cross-
connect board

Timing unit processing unit communication unit
SCC
Overhead bus
Clock signal Cross-connect

and timing unit
Power module -48V
Fig 2-8 Functional diagram of SEP1
TSB8
Signal
selector
Working Protection
SEP1 SEP1
Allocation
drive 8¡ STM-1
Á
Electrical signal
Fig 2-9 Functional diagram of TSB8
The interface unit of SEP1 is EU04, EU08 and OU08, which accesses STM-1 signals and sends them to SDH
signal processing unit after data and clock signal extracting at data and clock recovery unit. The SDH signal
processing unit implements frame search, SOH termination and insertion, overhead byte extraction, pointer
justification and POH monitoring to the incoming signals and then sends them to overhead processing unit for
further processing. After that, the signals are re-timed with the system clock, and then multiplexed into 622M data
signals after cross-connect and finally sent to the cross-connect and timing unit.
TSB8 enables EPS of SEP1. The signal selector of the TSB8 selects one out of the three groups of received
signals from the working SEP1 and sends them to the protection SEP1. The allocation drive allocates the signals
from the protection SEP1 to the working SEP1.
2.6.2 Front Panel

The front panel of SEP1, EU04, EU08, OU08, TSB8 and TSB4 is shown in Fig 2-10 , and the indicator description
is shown in tabe 2-8.
Fig 2-10 The front panel of SEP1, EU04, EU08, OU08, TSB8 and TSB4


Board hardware The board hardware is mismatched.
On for 100ms and off for
indicator-STAT
100ms alternatively, red
Off The board is not powered on, or the service is not

configured.
Service On, green The service is activated. (In EPS protection mode, the
activation board is in working status.)
indicator-ACT
Off The service is not activated. (In EPS protection mode,
the board is in protection status.)
On, green Upload of board software to FLASH or the FPGA

upload is normal, or the board software initialization is
normal.
On for 100ms and off for Board software is being uploaded to FLASH or FGPA
100ms alternatively,
green
Board software
On for 300ms and off for The board software is initializing, and is in BIOS boot
indicator-PROG
300ms alternatively, stage.
green
On, red The board software in FLASH or the FPGA

configuration is lost, resulting in upload and
initialization failure.
Service alarm On, green Service is normal, no service alarm occurs.
indicator-SRV On, red Critical or major alarm occurs to service.
Table 2-9 Indicator description of SEP1
2.6.3 Interface
There are two pairs of 75Ω SMB interface on the panel of SEP1. The
board can access 2 x STM electrical signals when it is used
independently.
SEP1 board can also cooperate with EU08, EU04 or OU08 to realize
different functions.
Table 2-10 shows the comparison between EU08, EU04 and OU08.
Board EU08 EU04 OU08

Item
Interface Number 8 4 8
Access Capability 8×STM-1 electrical 4×STM-1 electrical 8×STM-1 optical signal

signal signal
Interface Type 8 pairs of SMB electrical 4 pairs of SMB electrical 8 pairs of SC or LC

interface interface optical interface
Table 2-10 Comparison between EU08, EU04 and OU08
TSB8 and TSB4 enable EPS of SEP1. The specific protection principle
is shown in Fig 2-11.
SLOT 14 SLOT16
Signal
of
TSB8 EU04 Switch
Control
System
Control
Unit
SLOT 4/5
Protection Working
SEP1 SEP1
8 × STM-1(E4)
Failure
Service
SLOT12 SLOT13
Fig 2-11 EPS of SEP1
When a working SEP1 failure is detected, the cross-connect and timing unit will ask EU04 to transfer the signal to
TSB8, and thus to bridging the signals of EU04 and protection SEP1.
Note:
EPS is a scheme at device level. When the working board fails, the accessed
signal will be protected by being bridged to the protection board. By this way,
triggering of more complex protection at network level such as MSP and
SNCP can be avoided, improving the equipment reliability.

Before using SEP1 for running service, parameters should be set for it through NM.
J1
TIM alarm.
C2
Description
Parameter
SEP1 EU08 EU04 OU08 TSB8 TSB4
Rate 155520kbit/s
2× 8× 4× 8× STM- None None

Access STM-1 STM-1 STM-1 1 optical
capability electrica electrica electrica signals
l signals l signals l signals
Processing 8× None None None EPS EPS

capability STM-1
Line code CMI or NRZ

pattern
Connector SMB SMB SMB LC, SC None None
Size (mm) 262.05 262.05 × 110 × 22

× 220 ×
25.4
Weight (kg) 0.950 0.410 0.405 0.410 0.279 0.279
Power 17 11 6 6 5 2.5
consumption
(W)
Optical module None 1-1 S-1.1 None

type
Wavelength None 1310 None

(nm)
Transmission None 0~15 None

distance (km)
Launched None -15 ~ -8 None

power (dBm)
Receiver None -38 None

sensitivity
(dBm)
2.7 SPQ4/MU04
SPQ4 is the 4 × E4/STM-1 processing board; and MU04 is the 4 x E4/STM-1 interface board.
SPQ4 can work with MU04 to access and process 4 × E4/STM-1 electrical signals; and SPQ4 and MU04 can work
with TSB4 to provide 1:1 EPS to SPQ4.
SPQ4 can be seated in Slot 12 ~ 13, MU04 in Slot 14, 16, and TSB4 in Slot 14, 16.
2.7.1.1 Functions
Access and process 4 × E4/STM-1 electrical signals. All paths can be

set for either E4 or STM-1 service as desired.
MU04 provides 75Ω SMB unbalanced interface.

The STM-1 service supports such protection schemes as MSP and
SNCP, while the E4 service supports path protection (PP).
Support SOH byte processing, including B1, B2, K1, K2, M1, F1 and
D1-D3, D4-D12 (DCC).
Support POH byte processing, including J1, B3, C2, G1 and H4.
Support inloop and outloop at electrical interfaces for fast fault location.
Support configuration of such bytes as D1-D3, D4-D123 (DCC), E1
overhead bytes.
2.7.1.2 Principles
Fig 2-12 shows the functional diagram of SPQ4.
Mapping/
demapping Active cross-
4 x E4/STM-1 . Data and unit Bus connect board
Interface clock conversion
electrical . unit recovery unit
signals Overhead
. unit Standby cross-
processing
unit connect board
Control and
communication unit Other boards
Power module -48V
Fig 2-12 Functional diagram of SPQ4
The interface unit for SPQ4 is MU04, at which the 4 × E4/STM-1 electrical signals are accessed. Then the data
signals extracted by the data and clock recovery unit are sent to the mapping/demapping unit and overhead
processing unit for signal processing, SOH byte termination and insertion, and overhead data extraction.
The control and communication unit communicates with the SCC and others boards through the Ethernet port to
collect and report alarm and performance events, and interpret and process the configuration command sent by
NM.
The power module provides all modules on the board with required DC power supply and monitors the power
supply status.
TSB4 enables EPS of SPQ4. The signal selector of the TSB4 selects one out of received signals from working
SPQ4 and sends them to the protection SEP1. The allocation drive allocates the signals from the protection SPQ4
to working SPQ4.
2.7.2 Front Panel

The front panel of SPQ4 and MU04 is shown in 0, and the indicator description of SPQ4 is shown in Fig 2-13
Fig 2-13 The front panel of SPQ4 and MU04
Table 2-10 Indicator description of SPQ4


Board
hardware On for 100ms and off for The board hardware is mismatched.
indicator-STAT 100ms alternatively, red

On, green The service is activated. (In EPS

protection mode, the board is in working
Service status.)
activation
indicator-ACT Off The service is not activated. (In EPS
protection mode, the board is in
protection status.)

the FPGA upload is normal, or the board
On for 100ms and off for Board software is being uploaded to

100ms alternatively, FLASH or FGPA
green
Board software
indicator- On for 300ms and off for The board software is initializing, and is
PROG 300ms alternatively, in BIOS boot stage.
green

Service alarm On, green Service is normal, no service alarm

indicator-SRV occurs.
On, red Critical or major alarm occurs to service.
Off No service configured or no power

supply.
2.7.3 Interface
MU04 provides 75Ω SMB unbalanced interface, with the maximum

transmission distance reaching 70m.
MU04 and TSB4 enable EPS for SPQ4. The specific protection
principle is shown in Fig 2-14.
SLOT 14 SLOT16
signal of
switching
TSB 4 MU04
control
System
Control
Unit
SLOT 4/5
protecting working
SPQ4 SPQ4
failure 4 x E 4 service
SLOT12 SLOT13
Fig 2-14 EPS of SPQ4
When a working SPQ4 failure is detected, the cross-connect and timing unit will ask MU04 to transfer the signals to
TSB4, thus to bridging the signals of MU04 and protection SPQ4.
The slot assignment of SPQ4, MU04 and TSB4 is shown in Table 2-11
Board Protection group 1

Protection SPQ4 Slot 12
TSB4 Slot 14
Working SPQ4 Slot 13
MU04 Slot 16
Table 2-11 Slot assignment of SPQ4, MU04 and TSB4
Note:
EPS is a scheme at device level. When the working board fails, the accessed
signal will be protected by being bridged to the protection board. By this way,
triggering of more complex protection at network level such as MSP and
SNCP can be avoided, improving the equipment reliability.

Before using SPQ4 for running service, parameters should be set for it through NM. Configuration should be
provided to the following bytes:
J1
TIM alarm.
C2
Description
Parameter
SPQ4 MU04
Rate 139264kbit/s or 155520kbit/s
Processing Process 4 × E4/STM-1 Access 4 × E4/STM-1

capability electrical signals electrical signals
Line code CMI

pattern
Connector None SMB
Size (mm) 262.05 × 220 × 25.4 262.05 × 110 × 44
Weight (kg) 0.910 0.405
Power 24 2
consumption
(W)
2.8 PD3/PL3/D34S/C34S
PD3 is the 6 × E3/DS3 processing board;

PL3 is the 3 × E3/DS3 processing board.
D34S is the 6 × E3/DS3 PDH interface switching board,
C34S is the 3 × E3/DS3 PDH interface switching board.
Table 2-12 shows the difference between PD3 and PL3.
Board
PD3 PL3
Comparison
Processing capability 6 × E3/DS3 3 × E3/DS3
Available slots Slot 12, 13 Slot 12, 13
Interface board D34S C34S
Table 2-12 Comparison between PD3 and PL3
2.8.1.1 Functions
PD3 can process 6 × E3/DS3 signals, and PL3 can process 3 ×

E3/DS3 signals.
D34S provides 6 × 75Ω unbalanced E3/DS3 interfaces.
C34S provides 3 × 75Ω unbalanced E3/DS3 interfaces.

PD3/PL3 supports 1:1 EPS and SNCP, with the switching time less
than 50ms.
Support setting and query of all POH bytes at VC-3 level.
2.8.1.2 Principles
Fig 2-15 shows the functional diagram of PD3/PL3.
Active cross-
Mapping/ connect board
3/6 x E3/DS3 Interface Bus
demapping
electrical unit conversion
unit
signals unit Standby cross-
connect board
Control and
Timing unit communication unit
Cross-connect
and timing unit
Clock signal
Power module -48V
Fig 2-15 Functional diagram of PD3/PL3
The interface unit accesses E3/DS3 electrical signals through D34S/C34S and recovers the data and clock signals.
Also, the interface unit performs decoding/encoding and jitter suppressing to the signals, generates and detects
pseudo-random binary sequence (PRBS), and detects and inserts part of the alarms. The mapping/demapping unit
maps/demaps the E3/DS3 signal, processes the lower order overhead, suppresses the jitter, and generates and
detects the PRBS. The bus conversion unit converts the low speed bus at board side into the high speed bus at
protection board side.
The timing unit receives the 38M clock signal and 2K frame header from the active and standby cross-connect and
timing units at the same time and performs the clock frequency conversion and drive of the board. Additionally, the
8K line reference clock signal is for board status checking. It is sent to the active and standby cross-connect boards
and indicates whether the board works normal and whether the board is in position.
The control and communication unit mainly functions control, communication and service configuration of the
board. The power module provides all modules of the board with DC power supply with required voltage.
2.8.2 Front Panel

The front panel of PD3, PL3, D34S and C34S is shown in Fig 2-16, and the indicator description of PD3 and PL3 is
shown in Table 2-13
Fig 2-16 The front panel of PD3, PL3, D34S and C34S
Color and
status

Board and off for
hardware
100ms
indicator-STAT
alternatively,
red


activation

the FPGA upload is normal, or the board

and off for FLASH or FGPA
100ms
alternatively,
green
Board software
indicator- On for 300ms The board software is initializing, and is
PROG and off for in BIOS boot stage.
300ms
alternatively,
green


occurs.

indicator-SRV
Off No service configured or no power

supply.
Table 2-13 Indicator description of PD3/PL3
2.8.3 Interface
Interface description of D34S and C34S is shown in Table 2-14
Board name D34S C34S

Access capacity 6 × E3/DS3 3 × E3/DS3
Interface 75Ω unbalanced interface
Interface Type SMB angle female
Processing PD3 PL3

Board Equipped
Slot available Slot 14, 16
Table 2-14 Interface description of D34S and C34S
PD3/PL3, D34S/C34S and TSB8/TSB4 can work together to provide 1:1 EPS. Fig 2-17 shows the 1:1 EPS of
PD3.The protection PD3 can be seated in Slot 12, and the working PD3 in Slot 13. D34S is in Slot 16, and TSB8 is
in Slot 14.
When a working PD3 failure is detected, the cross-connect and timing unit will ask the interface board to switch the
service from service bus to protection bus for protection.
SLOT 14 SLOT16
Signal of
TSB8 Switching
D34S
control
System
Control
unit
SLOT 4/5
protecting working
PD3 PD3
failure 6 ?&E3 service
SLOT12 SLOT13
Fig 2-17 1:1 EPS of PD3

Before using PL3/PD3 for running service, parameters should be set for it through NM. Configuration should be
provided to the following bytes:
J2
It is the VC-3 path trace byte. Successive transmission of the lower order access point identifier through J1 helps
the receive end learn that its connection with the transmit end in this path is in continuous connection status.
2.8.5 Technical Specifications
Description
Parameter
PL3 PD3 D34S C34S
Processing 3 × E3/DS3 6 × E3/DS3 0 0

capability
Access 0 0 6 × E3/DS3 3 × E3/DS3

Capability
Line code E3:HDB3, DS3:B3ZS

pattern
Connector None None SMB SMB
Size (mm) 262.05 × 220 × 25.4 262.05 × 110 × 22
Weight (kg) 0.995 1.120 0.381 0.310
Power 15 19 2 2
consumption
(W)
2.9 PQ1/PQM/PD1/D75S/D12S/D12B
PQ1 is the 63 × E1 processing board;

PQM is the 63 × E1/T1 processing board;
PD1 is the 32 × E1 processing board;
D75S is the 32 × 75Ω E1/T1 PDH interface switching board;
D12S is the 32 × 120Ω E1/T1 PDH interface switching board;
D12B is the 32 × 75Ω/120Ω E1/T1 PDH interface board.
D75S, D12S and D12B can work as interfaces boards to receive/transmit E1/T1 service for PQ1/PQM/PD1. D75S
and D12S can also work as switching boards to implement EPS for PQ1/PQM/PD1.
Table 2-15 shows the difference between PQ1, PD1 and PQM.
Board name
PQ1 PQM PD1
Comparison
Processing capability 63 × E1 63 × E1/T1 32 × E1
Interface board 2 × D75S or 2 × 2 × D12S D75S or

(Providing EPS) D12S D12S
Interface board (NOT 2 × D12B 2 × D12B D12B

providing EPS)
Table 2-15 Comparison between PQ1, PD1 and PQM
2.9.1.1 Functions
D75S provides 32 × 75Ω unbalanced E1 interfaces; D12S provides 32

× 120Ω balanced E1/T1 interfaces; and D12B provides 32 × 75Ω/120Ω
E1/T1 interfaces.
PQM processes 63 × E1/T1 signals, each of which can be configured
as either E1 or T1 independently through software. PQ1 processes 63
× E1 signals. PD1 processes 32 × E1 signals.
PQ1/PQM/PD1 supports 1:N (N ≤ 2) EPS, PP and SNCP, with the

switching time less than 50ms.
2.9.1.2 Principles
0ig 2-18 shows the functional diagram of PQ1/PQM/PD1.
Frame Active cross-

header Mapping/ Bus connect board
E1/T1 electrical
.. Interface
extraction demapping conversion
signals unit
. & insertion unit unit
unit Standby cross-
connect board
Control and
Timing unit communication
unit
Cross-connect
Power module -48V
Fig 2-18 Functional diagram of PQ1/PQM/PD1
The interface unit accesses 63 × E1/T1 electrical signals through the interface board and recovers the data and
clock signals. Also, the interface unit performs decoding/encoding and jitter suppressing to the signals, generates
and detects PRBS, and detects and inserts part of the alarms. The frame header extraction & insertion unit extracts
and inserts the frame header of T1 signal, and pass through the E1 service in both the transmit and receive
directions. The mapping/demapping unit maps/demaps the E1/T1 signal, processes the lower order overhead,
suppresses the jitter, and generates and detects the PRBS. The bus conversion unit converts the low speed bus at
board side into the high speed bus at protection board side.
The timing unit receives the 38M clock signal and 2K frame header from the active and standby cross-connect and
timing units at the same time and performs the clock conversion and drive of the board. Additionally, the 8K line
reference clock signal is for board status checking. It is sent to the active and standby cross-connect boards and
indicates whether the board works normal and whether the board is in position.
board. The power module provides all modules of the board with DC power supply with required voltage.
2.9.2 Front Panel

The front panel of PQ1, PQM, PD1, D75S, D12S and D12B is shown in Fig 2-19, and the indicator description of
PQ1, PD1 and PQM is shown in Table 2-16.
Fig 2-19 Front panel of PQ1, PQM, PD1, D75S, D12S and D12B
Color and
status

Board and off for
hardware
100ms
indicator-STAT
alternatively,
red


activation


and off for FLASH or FGPA
100ms
alternatively,
green
Board software
indicator- On for 300ms The board software is initializing, and is in
PROG and off for BIOS boot stage.
300ms
alternatively,
green


occurs.
indicator-SRV
Table 2-16 Indicator description of PQ1, PD1 and PQM
2.9.3 Interface
Table 2-17 shows the difference between D75S, D12S and D12B.
Comparison
D75S D12S D12B
Board name
Service accessed 32×E1 32×E1/T1 32 × E1/T1
Interface 75Ω unbalanced 120Ω balanced 75Ω

interface interface unbalanced
interface and
120Ω balanced
interface
Interface type DB44 DB44 DB44
Slot Slot 14 ~ 16 Slot14 ~ 17 Slot14 ~ 17
Table 2-17 Comparison between D75S, D12S and D12B
PQ1/PQM/PD1 and D75S/D12S can be provided with 1:2 EPS. Fig 2-20 shows the EPS of PQ1.Slot 11 is for
protection PQ1, while Slot 12 - 13 is for working PQ1/PQM/PD1. Slot 14 ~ 15 and 15 ~ 17 is for interface board
D75S/D12S.
When a working PQ1 fails, the cross-connect unit will ask the interface board to switch the service to protection
PQ1 for protection.
SLOT 14 SLOT16
Signal
D75S of
D75S
Switch
Control
System
Control
Unit
SLOT 4/5
Protecting Working Working
PQ1 PQ1 PQ1
Failure E1 Service
SLOT11 SLOT12 SLOT13
Fig 2-20 1:2 EPS of PQ1

Before using PQ1/PQM/PD1 for running service, parameters should be set for it through NM.
Configuration should be provided to the following byte for PQ1/PQM/PD1:
J2
It is the VC-12 path trace byte. Successive transmission of the lower order access point identifier through J1 helps
the receive end learn that its connection with the transmit end in this path is in continuous connection status.
Description
Parameter
PQ1 PQM PD1 D75S D12S D12B
Process Process Process Access Access Access

Processing
63 × E1 63 × 32× E1 32 × E1 32 × 32 ×
capability
E1/T1 E1/T1 E1/T1
Line code E1: HDB3, T1: B8ZS, AMI

pattern
Connector None None None DB44 DB44 DB44
Size (mm) 262.05 × 220 × 262.05 262.05 × 110 × 22

25.4 × 110 ×
25.4
Weight (kg) 1.010 1.010 0.505 0.354 0.354 0.310
Power 19 22 19 5.5 9 1
consumption
(W)
2.10 EGS2
EGS2 is the 2-port Gigabit Ethernet (GE) optical interface board with Lanswitch.
EGS2 can transparently transmit and converge the GE service. When working together with EFS0 and EFS4, the
FE service can be converged into GE service and the Layer 2 switching can be performed.
EGS2 can be seated in Slot 11 - 13.
2.10.1.1 Functions
Provides 2 × LC 1000BASE-SX/LX Ethernet optical interfaces with

auto-negotiation function, that is, they can be set to enabled or
disabled. The transmission distance of the interfaces is 500m
(multimode) or 10km (single-mode), or you can select the 40km or
70km optical module as required in practice.
Support bandwidth adjustment at granularity of 64kbit/s and service
mapping into VC-12 or VC-3 level. The service supports global
functional plane (GFP), link access procedure-SDH (LAPS) and high-
level data link control (HDLC) encaPSUlation.
Support Link Capacity Adjustment Scheme (LCAS), achieving higher
transmission bandwidth utility.
Support the Ethernet Layer 2 switching, rapid spanning tree protocol
(RSTP), and point-to-point and point-to-multipoint multiprotocol label
switching (MPLS) Layer 2 virtual private network (VPN).
Support IEEE 802.1q-compliant and IEEE 802.1p-compliant virtual
local area network (VLAN) and VLAN convergence.
Support Layer 2-based convergence and point-to-multipoint
convergence.
EGS2 can work with EFS0 and EFS4 to converge the FE service into
GE service.
Support the port-based and port + VLAN-based flow classification, and
the priority setting and queue adjusting of flow.
Support IEEE802.3X-compliant flow control.
Support inloop and outloop of all kinds for fast fault location.
2.10.1.2 Principles
Fig 2-21 shows the functional diagram of EGS2.
Front panel Backplane
Interface Service Mapping

processing processing Encapsulation
module module
module module
-48V
Control and Power module
communication module
Fig 2-21 Functional diagram of EGS2
In receive direction:
The interface processing module accesses the 1000BASE-SX/LX signals from external Ethernet equipments such
as Ethernet switch and router and performs decoding and serial/parallel conversion to the signals. Then, the
signals are sent to the service processing module for frame delimitation, preamble field code stripping, cyclic
redundancy code (CRC) termination and Ethernet performance statistics. And flow classification is performed
according to the service type and configuration requirement (message formats MPLS, L2 MPLS VPN and
Ethernet/VLAN are supported), and Tunnel and VC double labels are added according to the service for mapping
and transfer. At the encapsulation module, the HDLC, LAPS or GFP encapsulation is performed to the Ethernet
frame. After that, the services are mapped into VC-3 or VC-12 at the mapping module and then sent to the cross-
connect unit.
In transmit direction:
The VC-3 or VC-12 signals from the cross-connect unit are demapped and sent to the encapsulation module for
decapsulation. The service processing module determines the route according to the level of the equipment, and
performs flow classification according to the service type and configuration requirement. Also, frame delimitation,
adding preamble field code, CRC calculation and performance statistics are performed by the service processing
module. Finally, the signals are sent out from the Ethernet interface after serial/parallel conversion and encoding at
interface processing module.
Control and communication module
board.
Power module
The power module provides all modules of the board with DC power supply with required voltage.
2.10.2 Front Panel

The front panel of EGS2 is shown in Fig 2-22 . The indicator description is shown in Table 2-17.
Fig 2-22 The front panel of EGS2

Board On, green The board works normally.

hardware On, red The board hardware fails.
indicator-
STAT On for 100ms and off The board hardware is mismatched.
for 100ms
alternatively, red
Off The board is not powered on, or the service

is not configured.

activation
indicator- Off The service is not activated.
ACT

On for 100ms and off Board software is being uploaded to FLASH

for 100ms or FGPA
Board alternatively, green
software
On for 300ms and off The board software is initializing, and is in
indicator-
for 300ms BIOS boot stage.
PROG
alternatively, green


Service
indicator- On, yellow Minor or remote alarm occurs to service.
SRV
On, green The GE port is connected with the opposite

equipment, and the link is established.
LINK*
Off The GE port is not connected with the
opposite equipment, and the link is not
available.
On for 100ms and off There is data exchanged between the GE

for 100ms port and opposite equipment.
ACT* alternatively, orange
Off There is no data exchanged between the GE

port and opposite equipment.
Table 2-17 Front panel and indicator description of EGS2
2.10.3 Interface
EGS2 supports the small-form pluggable (SEP) LC optical interface, and 1000Base-SX and 1000Base-LX
interfaces. The interface transmission distance reaches 500m (multimode) or 10km (single-mode). Table 2-18
shows the interface characteristics of EGS2.
Connector LC
Optical interface type 1000Base-SX or 1000Base-LX
Specifications IEEE 802.3z-compliant
Line code Manchester coding (10M), MLT-3 or NRZI
Table 2-18 Interface characteristics of EGS2

Before using EGS2 for running service, parameters should be set for it through NM.
Configuration should be provided to the following bytes:
J1
TIM alarm.
C2
Ethernet port working mode
The Ethernet ports of the interconnected equipments are generally required to work in the same fixed mode. If not,
packet loss or rate decrease will happen, and even complete service interruption will be resulted when the traffic is
heavy.
Parameter Description
Board EGS2
Rate 1000Mbit/s
Processing capability 2 × 1000Mbit/s Ethernet signals
Line code pattern Manchester coding (10M), MLT-3 or NRZI
Connector LC (SFP)
Size (mm) 262.05 × 220 × 25.4
Weight (kg) 1.041
Power consumption (W) 39
Optical module type 1000Base-SX 1000Base-LX
Transmission distance (km) 0~0.5 0~10
Mean launched power (dBm) -9.5 ~ 0 -9 ~ -3
Receiver sensitivity (dBm) -17 -20
Central wavelength (nm) 850 1310
2.11 EFS4/EFS0/ETF8
EFS4 is the 4-ports fast Ethernet processing board with Lanswitch,
EFS0 is the fast Ethernet processing board with Lanswitch.
They are responsible for transparent transmission, convergence and Layer 2 switching of the Ethernet signal.
Table 2-19 shows the difference between EFS4 and EFS0.
Board name
EFS4 EFS0
Comparison
Processing capability 4 × 10M/100M 8 × 10M/100M
Interface board None ETF8
Ports at panel 4 0
Slot available Slot 11 ~ 13 Slot 12 ~ 13
Table 2-19 Comparison between EFS4 and EFS0
2.11.1.1 Functions
EFS4 provides 4 × 10Base-T/100Base-TX ports (RJ-45) with auto-

negotiation function, that is, they can be set to enabled or disabled. The
transmission distance is up to 100m.
ETF8 provides 8 × 10Base-T/100Base-TX ports (RJ-45) with auto-

negotiation function, that is, they can be set to enabled or disabled. The
transmission distance is up to 100m.
EFS4 can process 4 × 10M/100M Ethernet services. EFS0 can
process 8× 10M/100M Ethernet services, support 64kbit/s bandwidth
adjustment and service mapping into VC-12 or VC-3 level. The service
supports GFP, LAPS and HDLC encapsulation.
Support LCAS, achieving higher transmission bandwidth utility.
Support the Ethernet Layer 2 switching, RSTP, and point-to-point and
point-to-multipoint MPLS Layer 2 VPN.
Support IEEE 802.1q-compliant and IEEE 802.1p-compliant virtual
local area network (VLAN) and VLAN convergence.
Support Layer 2-based convergence and point-to-multipoint
convergence.
EFS4 and EFS0 can work with EGS2 to converge the FE service into
GE service.
Support the port-based and port + VLAN-based flow classification, and
the priority setting and queue adjusting of flow.
Support IEEE802.3X-compliant flow control.
Support inloop and outloop of all kinds for fast fault location.
2.11.1.2 Principles
Fig 2-23 shows the functional diagram of EFS0.
Interface Service
processing Encapsulation Mapping
processing
module (ETF8) module module
module
Control and -48V

communication Power module
module
Fig 2-23 Functional diagram of the EFS0
In receive direction:
The interface processing module accesses the 10/100BASE-TX signals from external Ethernet equipments such as
Ethernet switch and router and performs decoding and serial/parallel conversion to the signals. Then, the signals
are sent to the service processing module for frame delimitation, preamble field code stripping, cyclic redundancy
code (CRC) termination and Ethernet performance statistics. And flow classification is performed according to the
service type and configuration requirement (message formats MPLS, L2 MPLS VPN and Ethernet/VLAN are
supported), and Tunnel and VC double labels are added according to the service for mapping and transfer. At the
encapsulation module, the HDLC, LAPS or GFP encapsulation is performed to the Ethernet frame. After that, the
services are mapped into VC-3 or VC-12 at the mapping module and then sent to the cross-connect unit.
In transmit direction:
The VC-3 or VC-12 signals from the cross-connect and timing unit are demapped and sent to the encapsulation
module for decapsulation. The service processing module determines the route according to the level of the
equipment, and performs flow classification according to the service type and configuration requirement. Also,
frame delimitation, adding preamble field code, CRC calculation and performance statistics are performed by the
service processing module. Finally, the signals are sent out from the Ethernet interface after serial/parallel
conversion and encoding at interface processing module.
Control and communication module
board.
Power module
The power module provides all modules of the board with DC power supply with required voltage.
2.11.2 Front Panel

The front panel of EFS0, EFS4 and ETF8 is shown in Fig 2-24 and the indicator description is shown in Table 2-20
Fig 2-24 The front panel of EFS0, EFS4 and ETF8


Board
hardware On for 100ms and The board hardware is mismatched.
STAT alternatively, red


activation
indicator- Off The service is not activated.
ACT


alternatively,
Board green
software
On for 300ms and The board software is initializing, and is in
indicator-
off for 300ms BIOS boot stage.
PROG
alternatively,
green


occurs.
Service
indicator-
SRV On, yellow Minor or remote alarm occurs to service.

T
Table 2-20 Indicator description of EFS0, EFS4
2.11.3 Interface
EFS4 provides 4 Ethernet ports, and ETF8 provides the EFS0 with 8 ports. Table 2-21 shows the ports
characteristics.
Type RJ-45
Impedance 100Ω
Specifications IEEE 802.3-compliant
Line code Manchester coding (10M), MLT-3 or NRZI
Table 2-21 Ethernet ports characteristics
Two indicators for each interface, their meanings shown in Table 2-22
Color Meaning Silkscreen Description

Green link LINK* On: link is established;
Off: no link is established.
Orange activity ACT* Flash: There is data

transmitted/received; Off: there is no
data transmitted/received.
Table 2-22 Meanings of LED indicators on RJ-45 connector

Before using EFS4 or EFS0 for running service, parameters should be set for it through NM.
Configuration should be provided to the following bytes:
J1
TIM alarm.
C2
Ethernet port working mode
The Ethernet ports of the interconnected equipments are generally required to work in the same fixed mode. If not,
packet loss or rate decrease will happen, and even complete service interruption will be resulted when the traffic is
heavy.
Description
Parameter
EFS4 EFS0 EFT8
Rate 10Mbit/s, 100Mbit/s
Processing capability 4× 8× None

10M/100M 10M/100M
Accessing capability 4× 0 8×
10M/100M 10M/100M
Line code pattern Manchester coding (10M), MLT-3 or NRZI
Connector RJ-45 None RJ-45
Size (mm) 262.05 × 262.05 × 262.05 ×

220 × 25.4 220 × 25.4 110 × 50
Weight (kg) 0.980 0.984 0.370
Power consumption (W) 33 33 2
2.12 CXL1/CXL4/CXL16
CXL1, CXL4 and CXL16 are boards integrating the functions of the SDH processing unit, system control &
communication unit, cross-connect unit and timing unit at levels of STM-1, STM-4 and STM-16 respectively. Table
2-23 shows a comparison between CXL1, CXL4 and CXL16.
Board name CXL1 CXL4 CXL16
Ling processing
1×STM-1 1×STM-4 1×STM-16
capacity
Cross-connect
capacity (higher 40G/5G 40G/5G 40G/5G
order / lower order)
Clock function Same
System control
Same
function
Table 2-23 Comparison between CXL1, CXL4 and CXL16
2.12.1.1 SDH processing unit
The CXL1, CXL4 and CXL16 boards are responsible for receiving and
transmitting one channel of optical signal at STM-1, STM-4 and STM-
16 level respectively. Their optical interfaces are compliant with ITU-T
Recommendation G.957. Frame structures are compliant with ITU-T
Recommendation G.707, and the jitter specifications compliant with
ITU-T Recommendation G.825 and G.958.
The CXL1 supports S-1.1, L-1.1, L-1.2, and Le-1.2 optical modules for
The CXL4 supports S-4.1, L-4.1, L-4.2, and Le-4.2 optical modules for
The CXL16 supports 1-16, S-16.1, L-16.1, and L-16.2 optical modules
for different transmission distances.
The CXL16 supports VC-4-4c, VC-4-8c and VC-4-16c concatenated
services.
The CXL16 can connect with the optical multiplex board of wavelength
division equipment without wavelength converter.
Support various protection schemes, such as 2-fiber or 4-fiber
bidirectional MSP ring, linear MSP and SNCP.
Provide inloop and outloop at optical interfaces and VC-4 level for fast
fault locating.
maintenance.
Support the on-line query of board information and optical power.
Support smooth upgrade and capacity expansion of software.
2.12.1.2 System control & communication unit
Configure and groom services, monitor service performance, and

collect performance event and alarm information.
Provide 10M and 100M compatible Ethernet NM interface.
Provide F&f interface through AUX board for TDA, COA and DCU
management.
Provide two 4M HDLC emergency paths for realizing MSP and SNCP.
Provide the OAM interface through AUX board, support remote
maintenance of the Modem of RS-232 DEC.
Provide 30 DCC to realize the transmit link for network management.
Support fan alarm and management function.
Provide PIU with lightening protection and in-position detection
functions.
2.12.1.3 Functions of cross-connect unit
Implement 40G VC-4 full cross-connect, and 5G VC-12/VC-3 full cross-

connect.
Realize flexible service grooming, including loopback, cross-
connection, group-broadcasting and broadcasting.
Ensure the normal running of other services after provisioning or
removing a certain service.
Support SNCP at VC-3 and VC-12 levels.
Support AU4-4C, AU4-8C and AU4-16C concatenated services.
Support 1+1 hot backup, revertively and non-revertively. The default is

non-revertive.
2.12.1.4 Timing unit
Provide standard system synchronization clock.

Input two channels of 2048kHz or 2048kbit/s timing signals, and
support the function of selecting external timing source.
Output two channels of 2048kHz or 2048kbit/s timing signals.
Provide SSM and the function of extracting, inserting and processing
clock ID.
2.12.1.5 Principle
Take CXL16 as an example. Fig 2-27 shows the system diagram of CXL16.The CXL16 integrates SDH processing
unit, cross-connect unit SCC and timing unit at STM-16 level.
F ro n t P a n e l S T M -1 6 S D H B a c k p la n e
p ro c e s s in g u n it
c ro s s -c o n n e c t u n it
SCC
tim in g u n it
Fig 2-27 CXL16 system diagram
2.12.2 Front Panel

Fig 2-26 shows the front panels of CXL1, CXL4 and CXL16. 0 shows the relevant description.
Fig 2-26 Front panels of CXL1, CXL4 and CXL16
Indicator status:
Color and
status

Board
hardware On for 100ms
indicator - and off for 100 The board hardware is mismatched.
STAT ms, red
The board is not powered on, or service

Off
is not configured.
Service The cross-connect unit is in active

On, green
activation status.
indicator of
cross-connect The cross-connect unit is in standby
Off
unit - ACTX status.
Service On, green The SCC is in active status.

activation
indicator of Off The SCC is in standby status.
SCC - ACTC
Upload of board software or the FPGA

On, green in FLASH is normal, or the board
On for 100ms
Broad software is being uploaded to
and off for 100
FLASH or FGPA.
ms, green
Board software
indicator - On for 300 ms
The board software is initializing, and is
PROG and off for 300
in BIOS boot stage.
ms, green
The board software in FLASH or FPGA

On, red is lost, resulting in upload and
Service alarm Service operates normally on the cross-

On, green
indicator of connect unit.
cross-connect
Switching (for example, EPS) occurs to
unit - SRVX On, red
the service on the cross-connect unit.
Service alarm Service operates normally on the line

On, green
indicator of line unit. No alarm occurs.
Indicator status:
Color and
status
unit - SRVL Critical or major alarm occurs to the
On, red
service on the line unit.
Minor or remote alarm occurs to the

On, yellow
service on the line unit.
The line service is not configured or

Off
there is no power supply.
On, yellow Alarm is cut off permanently.

ALMC
Off Alarm is provided normally.
Table 2-24 Front panel and its description of CXL16
2.12.3 Interfaces
The CXL1, CXL4 and CXL16 use LC connectors.

Before using CXL for running services, set parameters through the NM.
Line board needs the following setting:
J1 byte
J1 is the path trace byte. It is used to transmit continuously the higher order access point identifier. The receive end
verifies the continuous connecting of the intended transmit end by this byte. When J1 is detected to be mismatch at
the receive end, the corresponding VC-4 path generates an HP-TIM alarm.
C2 byte
C2 is the signal label byte, indicating the multiplexing structure of VC frame and the payload property. C2 from the
transmit end should match that at the received end. If mismatch is detected, the corresponding VC-4 path
generates an HP-SLM alarm. Also C4 will be set to all “1” in downstream stations.
Description
Parameter
CXL1 CXL4 CXL16
Rate 155520kbit/s 622080kbit/s 2488320kbit/s
Processing Line, SCC, cross-connect and timing

capability
Connector LC
Size (mm) 262.05 x 220 x 25.4
Weight (kg) 1.118 1.117 1.119
Power 38 38 39
consumption
CXL1
Optical S-1.1 L-1.1 L-1.2 Le-1.2

module type
Wavelength 1310 1310 1550 1550

(nm)
Transmission 2 - 15 15 - 40 40 - 80 80 - 100
distance (km)
Launched -15 - -8 -5 - 0 -5 - 0 -3 - 2
Optical Power
(dBm)
Receiver -31 -34 -34 -34

Sensitivity
(dBm)
CXL4
Optical S-4.1 L-4.1 L-4.2 Le-4.2

module type
Wavelength 1310 1310 1550 1550

(nm)
Transmission 2 - 15 15 - 40 40 - 80 80 - 100
distance (km)
Launched -15 - -8 -3 - 2 -3 - 2 -3 - 2
Optical Power
(dBm)
Receiver -31 -30 -30 -33

Sensitivity
(dBm)
CXL16
Optical I-16 S-16.1 L-16.1 L-16.2

module type
Wavelength 1310 1310 1310 1550

(nm)
Description
Parameter
CXL1 CXL4 CXL16
Transmission 0-2 2 - 15 15 - 40 40 - 80
distance (km)
Launched -10 - -3 -5 - 0 -2 - 3 -2 - 3
Optical Power
(dBm)
Receiver -21 -21 -30 -30

sensitivity
(dBm)
2.13 EOW
EOW offers order wire phone and data interfaces. EOW is seated in Slot 9.
2.13.1.1 Functions
It provides:
One orderwire phone
Four broadcast data interfaces S1~S4
2.13.1.2 Principles
Fig 2-27 shows the functional diagram of EOW.
Overhead
processing
unit
System control &
communication
Orderwire
unit
phone
Broadcast
data and
Ring orderwire ～ S1
generaating&reset phone unit
S4
, clock unit
Backplane
Fig 2-27 The functional diagram of EOW
2.13.2 Front Panel

The appearance of EOW is shown in Fig 2-28. Its interface description is listed in Table 2-24. The indicator STAT
on the front panel is described in Table 2-25.
Fig 2-28 The front panel of EOW
Interface Description
PHONE Orderwire Phone Interface
S1 Serial 1
S2 Serial 2
S3 Serial 3
S4 Serial 4
Table 2-24 Description of the EOW interface on the front panel

Board On for 100ms and The board hardware is mismatched.

hardware off for 100ms
status alternatively, red
indicator-
STAT Off The board is not powered on or service is
not configured.
Off The cross-connect unit is in protection

status.


Board alternatively, green
software
status On for 300ms and The board software is initializing, and is in
indicator- off for 300ms BIOS boot stage.
PROG alternatively, green


Table 2-25 Description of the indicators of EOW
2.13.3 Interface
The orderwire phone interface of EOW is RJ-11, the interface of S1 – S4 is the type of RJ-45.
Board name EOW
Processing capability Orderwire phone & data access
Size (mm) 110×220×25.4
Weight (kg) 0.4
Power consumption (W) 10
2.14 AUX
AUX is the system auxiliary interface board, seated in slot 10.
2.14.1.1 Functions
Provides one ETH interface for NM.

Provides one COM interface for debugging.
Monitors two independent -48V power and reports the result of over-
voltage when the voltage exceeds -72V or under-voltage when the
voltage is under -38.4V.
Provides the function of three inputs & one output Boolean value.
Provides the backup power of 3.3V, 80W for all the boards and
monitors the 3.3V backup power.
Provides the function of sound alarm.
Provides the operation administration and maintenance (OAM)
interface which can be used as serial interface of NM, supporting
remote maintenance of the Modem of RS-232 data connected
equipment (DCE) and the X.25 protocol.
Manages the serial interface of F&f which is the same as OAM
interface for managing external devices such as TDA, COA and DCU.
Provides two BITS clock input interfaces and two BITS clock output
interfaces.
2.14.1.2 Principles
Fig 2-29 shows the functional diagram of AUX.
OAM Interface
F&f module
CLK Clock bus

External clock
input/output modul
ETH
Communications 2 interfa ces of NM
COM module
Boolean value of 3 inputs and 1 output

ALM Power monitoring Two -48V power monitoring
module 3.3V backup power monitoring
Fig 2-29 The functional diagram of AUX
Interface module
The interface module provides access of OAM and F&f. OAM and F&f use the same serial port, and are led out on
the front panel through RJ-45 interface.
External clock input/output module
The external clock input/output module performs access and processing of two building integrated timing supply
systems (BITS), and outputs two clock signals. The input and output share one RJ-45 interface with the impedance
of 120Ω.
Communication module
The module provides on the front panel one NT interface (ETH) and one debugging interface (COM), which pass
through RJ-45 interface.
Power monitoring module
The power monitoring module monitors two -48V power and 3.3V backup power, accomplishes the Boolean value
of three inputs and one output, and is led out on the front panel through RJ-45 interface.
2.14.2 Front Panel

The front panel of AUX is shown in Fig 2.30.
Fig 2-30 The front panel of AUX
2.14.3 Interface
The interface provided by AUX is shown in Table 2.26
COM Debugging interface, RJ-45
ETH NM interface, RJ-45
CLK External clock input/output interface,
RJ-45
ALM Boolean value input/output, RJ-45
OAM/F&f Serial interface for NM or OAM, RJ-45

Table 2-26 Description of AUX interfaces
Board name AUX
Processing System control, inter-board communication,

capability orderwire, and power detection
Size (mm) 110×220×25.4
Weight (kg) 0.4
Power consumption 15
(W)
2.15 PIU
PIU is the power interface board.
It functions power access, lightening protection and filtering, and can be seated in Slot 18 and 19.
2.15.1.1 Functions
Provides lightning protection function and report the alarm of lightning

protection failure.
Enhances the electro magnetic compatibility (EMC) of the system by
filtering and shielding the power supply.
Supports 1+1 hot backup protection. Each PIU can provide power for
the whole equipment independently.
Supports the protection to the output/input clock with the impedance of
75Ω.
2.15.1.2 Principles
Fig 2-31 shows the functional diagram of PIU.
NEG(-) NEG(-)
Protection Filtering
unit unit
RTN(+) RTN(+)
Power
detection
Clock input Clock output

Clock
LED protection
indicator
Fig 2-31 Functional diagram of PIU
Power access unit

The power access unit accesses the -48V power for the system.
Protection unit
It is applied for over current protection and lightening protection.
Filtering unit
The filtering unit uses the electromagnetic interference (EMI) filter to filter the EMI signal to guarantee the stable
operation of the equipment.
Power detection
The PIU detects and reports the status of the input power which will be displayed by the indicator on its front panel.
Clock protection
The PIU can protect one input clock resource and output it.
2.15.2 Front Panel

The PIU front panel is shown in Fig 2-32, the indicator of PIU is shown in Table 2-27
Fig 2-32 The front panel of PIU
Indicator Color and Description

status
Power off No power inputs.
indicator-
POWER on Power inputs normally.
Table 2-27The indicator of PIU
2.15.3 Interface
The interfaces on PIU board is shown in
表 1-1 The interface description of PIU
PWR The interface of -48V power inputs.
POWER The indicator of power.
CLK IN The clock inputs.
CLK OUT The clock outputs.
Board PIU
Input voltage -48V
Protecion tube F7 250V-20A-0.00355Ω
Size (mm) 108 × 110 × 41.5
Weight (kg) 1.151
Power 1.5
consumption (W)
2.16 FAN
The FAN board contains 6 fans and is used for heat dissipation of the equipment.
The FAN board can be installed in Slot 20.
2.16.1 Functions and Principle
2.16.1.1 Functions
Provides the power for the fans.

Detects the status of fans running and reports the result.
Indicates the status of the fan board.
Supports the function of hot plugging.
2.16.1.2 Principle
Block diagram of the FAN unit is shown in Fig 2-33 , followed by the brief introduction of these units.
£ -4 8V 1
GND GND
£ -4 8V 2
P ow er
GND 1 S tart
input F ans
unit
GND 2 unit £ -4 8V £ -4 8V
GND
£ -48V
F ans status
alarm signal
S tatus
step dow n detection
unit £ -4 8V unit GND
Fig 2-33 Block diagram of the FAN
Status detection unit

It detects the on/off state of the fans. When any one of the six fans stops, an alarm will be reported to the CXL
board, the indicator of the FAN will be on.
2.16.2 Front Panel

The front panel of FAN is shown in Fig 2-34
Fig 2-34 The FAN front panel
There are two indicators, one handle and one Electrostatic Discharge (ESD) jack on the FAN front panel. Handle
Used to draw out the air filter and FAN board.
Table 2-29 gives a description to the indicator of the FAN board.
Indicator Status Description

On One of the fans stops running
ALM
Off The fans are normal.
RUN On The power input to this board is normal.
Off No power inputs to this board.
Table 2-29 Description of indicators of FAN
2.16.3 Interface
ESD jack: Used to insert static wrist.
Item Description
Number of fans 6
Dimensions (mm) 220 × 120 × 25.4
Weight 1.010kg
Power consumption (W) 20W
3. CABLES
This chapter introduces the architecture and pin assignments of cables of the MSE 5010.
The following cables are used for the MSE 5010:
75Ω E1 cable
120Ω E1/T1 cable
75Ω E3/DS3 cable

Power cable
PGND cable
Clock cable
Network cable
Alarm cable
Data cable
Fiber
3.1 75Ω
Ω E1 Cable
3.1.1 Structure
Structure of the 75Ω cable is shown in Fig 3-1

Metal screw
W1~W4
Fig 3-1 Structure of the 75Ω E1 cable
The pin assignments of the DB78 connector for 75Ω E1 cable are shown in Fig 3-2.
1 20
21 39
40 59
60 78
Fig 3-2 Pin assignments of DB78 connector for 75Ω E1 cable
The 75Ω E1 cable comprises four coaxial cables, namely W1, W2, W3 and W4.
Each coaxial cable is composed of eight cores, numbered 1 through 8 on the sheath respectively. Fig 3-3 shows
the arrangement of these eight cores.
2
8 3
1 4
7
6 5
Fig 3-3 Arrangement of the eight cores
3.1.2 Pin Assignments
The 75Ω E1 cable is terminated with a DB78 connector, for connecting the 75Ω E1 electrical interface board of the
MSE 5010.
Table 1-1shows the pin assignments of DB78 connector for 75Ω E1 cable.
Pin Core Pin Core

Cable Signal Remarks Cable Signal Remarks
No. No. No. No.
2 Tip 4 Tip
1 R1 1 R5
22 Ring 24 Ring
31 Tip 33 Tip
2 T1 2 T5
12 Ring 14 Ring
41 Tip 43 Tip
3 R2 3 R6
61 Ring 63 Ring
70 Tip 72 Tip
4 T2 4 T6
W1 51 Ring W2 53 Ring
3 Tip 5 Tip
5 R3 5 R7
23 Ring 25 Ring
32 Tip 34 Tip
6 T3 6 T7
13 Ring 15 Ring
42 Tip 44 Tip
7 R4 7 R8
62 Ring 64 Ring
71 Tip 8 T4 73 Tip 8 T8
W1 52 Ring 8 T4 W2 54 Ring 8 T8
W3 6 Tip W4 8 Tip
1 R9 1 R13
26 Ring 28 Ring
35 Tip 37 Tip
2 T9 2 T13
16 Ring 18 Ring
45 Tip 47 Tip
3 R10 3 R14
65 Ring 67 Ring
Pin Core Pin Core

Cable Signal Remarks Cable Signal Remarks
No. No. No. No.
74 Tip 76 Tip
4 T10 4 T14
55 Ring 57 Ring
7 Tip 9 Tip
5 R11 5 R15
27 Ring 29 Ring
36 Tip 38 Tip
6 T11 6 T15
17 Ring 19 Ring
46 Tip 48 Tip
7 R12 7 R16
66 Ring 68 Ring
75 Tip 77 Tip
8 T12 8 T16
56 Ring 58 Ring
able 1-1 Pin assignments of the DB78 connector for 75Ω E1 cable
Cable Type SFYZTP-75-2-1 × 8

Core number 8
Connector DB78
Length 10m, 15m, 20m, 30m, 40m
3.2 120Ω
Ω E1/T1 Cable
3.2.1 Structure
Structure of the 120Ω E1/T1 cable is shown in Fig 3-4

Metal screw
W1~W4
Fig 3-4 Structure of the 120Ω E1/T1 cable
The pin assignments of the DB78 connector for 120Ω E1/T1 cable are shown in Fig 3-5.
1 20
21 39
40 59
60 78
Fig 3-5 Pin assignments of DB78 connector for 120Ω E1/T1 cable
The 120Ω E1/T1 cable comprises four twisted pairs, namely W1, W2, W3 and W4.
Each twist-pair cable is composed of eight twisted pairs, numbered 1 through 8 on the sheath respectively.
The 120Ω E1/T1 cable is terminated with a DB78 connector, for connecting the 120Ω E1/T1 electrical interface
board of the MSE 5010.
Table 3-2 shows the pin assignments of DB78 connector for the 120Ω E1/T1 cable.
Pin Core Pin Core

Cable Core color Remarks Cable No Core color Remarks
No. No. No.
.
2 Blue 6 Blue
Pair1 R1 Pair1 R9
22 White/Blue 26 White/Blue
41 Orange 45 Orange
Pair2 R2 Pair2 R10
61 White/Orange 65 White/Oran
ge
3 Green Pair 7 Green
R3 Pair 3 R11
3
23 White/Green 27 White/Gree
n
42 Brown Pair 46 Brown
R4 Pair 4 R12
4
62 White/Brown 66 White/Brow
W1 W2
n
4 Gray Pair 8 Gray Pair 5 R13
R5
24 White/Gray 5 28 White/Gray
43 Red Pair 47 Red
R6 Pair 6 R14
6
63 White/Red 67 White/Red
5 Black Pair 59 Black
R7 Pair 7 R15
7
25 White/Black 29 White/Black
44 Yellow Pair 48 Yellow
R8 Pair 8 R16
64 White/Yellow 8 68 White/Yello
w
31 Blue 35 Blue
Pair1 T1 Pair1 T9
12 White/Blue 16 White/Blue
70 Orange 74 Orange
W3 Pair2 T2 W4 Pair2 T10
51 White/Orange 55 White/Oran
ge
32 Green Pair 36 Green
T3 Pair 3 T11
13 White/Green 3 17 White/Gree
n
W3 71 Brown Pair W4 75 Brown
T4 Pair 4 T12
4
52 White/Brown 56 White/Brow
n
33 Gray Pair 37 Gray
T5 Pair 5 T13
5
14 White/Gray 18 White/Gray
72 Red Pair 76 Red
T6 Pair 6 T14
53 White/Red 6 57 White/Red
34 Black Pair 38 Black
T7 Pair 7 T15
7
15 White/Black 19 White/Black
Pin Core Pin Core

Cable Core color Remarks Cable No Core color Remarks
No. No. No.
.
73 Yellow Pair 77 Yellow
T8 Pair 8 T16
54 White/Yellow 8 58 White/Yello
w
Table 3-2 Pin assignments of the DB78 connector for 120Ω E1/T1 cable
Cable Type SEYPVPV-120-8 × 2 × 0.5
Core number 8
Connector DB78
Length 10m, 15m, 20m, 30m, 40m
3.3 E3/DS3 Cable
3.3.1 Structure
Structure of the 75Ω E3/DS3 cable is shown in Fig 3-6
1. Coaxial connector -SMB-75Ω-straight/plug- female -RG59

2. Main tag 3. Coaxial cable
Fig 3-6 Structure of the 75Ω E3/DS3 cable
Cable Type RG59/U
Connector SMB
Length 15m, 30m
3.4 Power Cable
3.4.1 Structure
Structure of the power cable is shown in Fig 3-7.
Injection molding screw
A3
A2
A Main tag Tag 1
A1
X
Fig 3-7 Structure of the -48V/-60 DC power cable

The power cable is terminated with a 3-core connector, for connecting the power board of the MSE 5010.
The power cable is composed of two wires. Table 3-3 shows the pin assignments of the 3-core connector.
Cable Pin Core color

W1 A1 (-48V/-60V) Blue
W2 A3 (ground) Black
Table 3-3 Pin assignments of the 3-core connector for power cable
Cable Type UL2562-18AWG
Connector 3 pin plug
Length 15m, 30m
3.5 PGND Cable
3.5.1 Structure
Structure of the PGND Cable is shown in Fig 3-8
Heat shri nk t ube Mai n l abel
OT t ermi nal
Fig 3-8 Structure of the PGND grounding Cable
3.6 75Ω
Ω Clock Cable
3.6.1 Structure
Structure of the 75Ω clock cable is shown in Fig 3-9
1. Coaxial connector -SMB-75Ω-straight/plug-female

2. Heat-shrink tube 3. Main tag
Fig 3-9 Structure of the 75Ω clock cable
The 75Ω clock cable is terminated with an SMB connector, for connecting the 75Ω clock interface board of the
MSE 5010.
3.7 120Ω
Ω Clock Cable
3.7.1 Structure
Structure of the 120Ω clock cable is shown in Fig 3-10
1. label 1(R) and 2. communication 3. main label 4. network interface

label 2(T) cable connector -RJ45
plug
Fig 3-10 Structure of the 120Ω clock cable
The 120Ω clock cable is terminated with a DB9 connector, for connecting the 120Ω clock interface board of the
MSE 5010. Table 3-4 shows the pin assignments of the DB9 connector.
X1 Color Relation Label
X1.1 Blue Pair EXT3R-
X1.2 White/Blue EXT3R+
X1.3 Orange Pair EXT4R-
X1.6 White/Orange EXT4R+
X1.4 Green Pair EXT3R-
X1.5 White/Green EXT3R+
X1.7 Brown Pair EXT4R-
X1.8 White/Brown EXT4R+
Table 3-4 Pin assignments of the DB9 connector for 120Ω clock cable
Communication cable-120Ω-SEYFVP-26AWG-2 pairs-

Cable Type
PANTONE WARM GREY 1U
Length 5m, 10m, 20m, 30m, 40m,50m, 70m, 100m
3.8 Network Cable
3.8.1 Structure
Structure of the network cable is shown in Fig 3-11
Fig 3-11 Structure of the network cable
Both ends of the network cable are terminated with RJ-45 connectors, for connecting the NM computer and the
MSE 5010 NM interface.
Fig 3-12 shows the RJ-45 connector.
PIN #8
PIN #1
Fig 3-12 RJ-45 connector

The network falls into straight through cable and crossover cable.
Straight through cable: Connects the NM computer and the MSE 5010
through HUB.
Crossover cable: Directly connects the NM computer and the MSE
5010.
3.8.2.1 Straight through network cable

Table 3-5 shows the pin assignments of the X1 connector for straight through cable.
X1 connector pin No. 8-core twisted pair X2 connector pin No.
1 White/orange 1
2 Orange 2
3 White/green 3
4 Blue 4
5 White/blue 5
6 Green 6
7 White/brown 7
8 Brown 8
Table 3-5 Pin assignments of the X1 connector for straight through cable
3.8.2.2 Crossover Network Cable

Table 3-6 shows the pin assignments of the crossover cable.
X1 connector pin No. 8-core twisted pair X2 connector pin No.

1 White/ orange 3
2 Orange 6
3 White/ green 1
4 Blue 4
5 White/ blue 5
6 Green 2
7 White/ brown 7
8 Brown 8
Table 3-6 Pin assignments of the X1 connector for crossover cable
Cable Type CC4P0.5P445U(S)
Connector RJ-45
Length 10m, 20m
3.9 Boolean Input/Output Cable
3.9.1 Structure
The structure of the Boolean input/output cable is shown in Fig 3-13
1. Network port connector - RJ-45 2. Main tag L: 10m, 20m, 30m
Fig 3-13 Boolean input/output cable
3.9.2 Pin assignment

The pin assignment of the Boolean input/output cable is shown in Table 3-7.
Connector X1 Color Relationship Alarm output Alarm input

X1.1 Blue EMERGENCY ALARM + SW_INPUT 1+
Pair
X1.2 White/Blue EMERGENCY ALARM - SW_INPUT 1-
X1.3 Orange MAIN ALARM + SW_INPUT 2+

Pair
X1.6 White/Orange MAIN ALARM - SW_INPUT 2-
X1.4 Green AUXILIARY ALARM 1+ SW_INPUT 3+

Pair
X1.5 White/Green AUXILIARY ALARM 1- SW_INPUT 3-
X1.7 Brown AUXILIARY ALARM 2+ SW_INPUT 4+

Pair
X1.8 White/Brown AUXILIARY ALARM 2- SW_INPUT 4-
Table 3-7 Pin assignment of Boolean input/output cable
3.9.3 Technical parameters
Twisted pair-120Ω-SEYVPV-0mm-24AWG-8
Model
cores-PANTONE 430U
Core number 8
Core diameter 0.5mm
Length 10m, 20m, 30m
3.10 OAM Serial Port Cable

The OAM serial port cable connects with the OAM interface of AUX, externally providing a DB25 connector.
3.10.1 Structure
The structure of the OAM serial port cable is shown in Fig 3-14
1. Network port connector - RJ-45 2. Main tag 3. Cable connector - DB25 - male
Fig 3-14 OAM serial port cable
3.10.2 Pin assignment

The pin assignment of the OAM serial port cable is shown in Table 3-8
Connector X1 Connector X1 Relationship Function

X1.1 Single RTS
X1.2 X2.20 Single DTR
X1.3 X2.2 Single TD
X1.4
X2.7 pair GND
X1.5
X1.6 X2.3 Single RD
X1.7 Single DSR
X1.8 Single CTS

Table 3-8 Pin assignment of OAM serial port cable
3.10.3 Technical parameters
Model
Twisted pair-120Ω-SEYVPV-0mm-24AWG-8 cores-
PANTONE 430U
Length 5000mm
3.11 S1 ~ S4/F&f Cable
3.11.1.1 Structure
The structure of the S1 ~ S4/F&f cable is shown in Fig 3-15
1. Network port connector - RJ-45 2. Main tag 3. Cable connector - DB9 male
Fig 3-15 S1~S4/F&f cable
3.11.1.2 Pin assignment

The pin assignment of the S1 ~ S4/F&f cable is shown in Table 3-9
Connector X1 Connector X2 Relationship Function

X1.3 X2.6 RX+
Pair
X1.6 X2.7 RX-
X1.1 X2.8 TX+

Pair
X1.2 X2.9 TX-
X1.5 X2.5 GND

Pair
X1.4 X2.3 RS232RX
X1.8 X2.2 Single RS232TX

Table 3-9 Pin assignment of S1 ~ S4/F&f cable
3.11.1.3 Technical parameters
Model
Twisted pair-120Ω-SEYVPV-0mm-24AWG-8 cores-
PANTONE 430U
Length 15m
3.12 Fiber
3.12.1 Structure
Structure of the fiber is shown in Fig 3-16
Fig 3-16 Structure of the fiber
Cable Type Optical connector-LC/PC-single mode
Connector LC/PC
Length 2m, 5m, 15m, 20m, 25m, 30m, 35m, 50m
4. INDICATOR DESCRIPTION FOR EQUIPMENT AND BOARD
4.1 Board Indicator Description
4.1.1.1 Board hardware indicator-STAT
Status Description
On for 100ms and The board hardware is mismatched.

off for 100ms
alternatively, red
4.1.1.2 Service activation indicator-ACT
Status Description
On, green The service is activated, and the board is in service.
Specifically, the board is in working status and the service is
active in EPS mode; and the indicator is normally on in the case
of no EPS provided.
Off The service is not activated, and the board can be swapped.
4.1.1.3 Board software indicator-PROG
Status Description
On, green Upload of board software to FLASH or the FPGA
upload is normal, or the board software initialization is
normal.
On for 100ms and Board software is being uploaded to FLASH or FGPA

off for 100ms
On for 300ms and The board software is initializing, and is in BIOS boot
off for 300ms stage.

4.1.1.4 Service alarm indicator-SRV
Status Description
On, red Critical or major alarm occurs to service.
4.1.1.5 Power monitoring indicators and alarm cut indicator of SCC
Indicator name Status Description

Indicator for - On, green -48V power supply A is normal.
48V power
supply A On, red, or off -48V power supply A is faulty (lost or
(PWRA) failed).
Indicator for - On, green -48V power supply B is normal.

48V power
supply B On, red, or off -48V power supply B is faulty (lost or
(PWRB) failed).
Indicator for - On, green The 3.3V protection power is normal.

48V power
supply C On, red The 3.3V protection power is lost.
(PWRC)
Alarm cut On, green Currently in permanent alarm cut-off

indicator status.
(ALMC)
Off Give sound warning upon alarm.
4.1.1.6 Ethernet indicators of AUX
Indicator name Meaning Status and description
Green LINK On: link is established;

Link status indication
indicator Off: no link is established.
Flash: there are data

Data transmitted/received;
Orange ACT
receiving/transmission
indicator Off: there is no data
indication
transmitted/received.
4.1.1.7 Ethernet port indicator of interface board
Status Description Remarks

The green and yellow The Ethernet cable is
-
indicators are off. not connected.
The green indicator is on, The Ethernet cable is

and the yellow indicator connected, but no data -
does not flash. is transmitted.
The flashing
The green indicator is on, The Ethernet cable is frequency of yellow
and the yellow indicator connected, and data is indicator depends on
flashes. transmitted. the transmission of
Ethernet data.
5. POWER CONSUMPTION AND WEIGHT
Power Weight Power Weight

Board consumpti (kg) Board consumpti (kg)
on (W) on (W)
SL16 20 1.100 PD1 20 0.505
SLQ4 16 1.036 D75S 5.5 0.354
SLD4 15 1.032 D12S 9 0.354
SL4 14.5 1.030 D12B 1 0.310
SLQ1 15.5 1.036 TSB8 5 0.279
SL1 14 1.030 TSB4 2.5 0.279
SEP1 17 0.950 EGS2 39 1.041
EU04 6 0.405 EFS0 33 0.984
EU08 11 0.410 EFS4 33 0.980
OU08 6 0.410 ETF8 2 0.370
SPQ4 24 0.910 CXL1 38 1.118
MU04 2 0.405 CXL4 38 1.117
PD3 19 1.120 CXL16 39 1.119
PL3 15 0.995 AUX 11 0.959
D34S 2 0.381 EOW 10 0.4
C34S 2 0.310 FAN 20 1.5
PQM 22 1.010 PIU 8 1.151
PQ1 19 1.010
6. ACRONYMS AND ABBREVIATIONS
Abbreviation Full name

ADM Add/Drop Multiplexer
ALS Automatic Laser Shutdown
BIOS Basic Input/Output System
BITS Building Integrated Timing Supply System
CMI Coded Mark Inversion
DCC Data Communication Channel
DCE Data Connection Equipment
DTE Data Terminal Equipment
EMC Electromagnetic Compatibility
E/O Electrical/optical conversion
EPL Ethernet Private Line
EPLAN/EPLn Ethernet Private LAN
ETSI European Telecommunication Standards Institute
EVPL Ethernet Virtual Private Line
EVPLAN/ENPLn Ethernet Virtual Private LAN
FE Fast Ethernet
FPGA Field Programmable Gate Array
GE Gigabit Ethernet
GFP Generic Framing Procedure
HDB3 High Density Bipolar of order 3 code
HDLC High Digital Link Control
IEEE Institute for Electrical and Electronic Engineers
IP Internet Protocol
International Telecommunication Union-

ITU-T
Telecommunication Sector
L2 Layer 2
LAN Local Area Network
LAPS Link Access Procedure-SDH
LCAS Link Capacity Adjustment Scheme
LSP Label Switch Path
MAC Media Access Control
MADM Multi Add/Drop Multiplexer
Abbreviation Full name

MAN Metropolitan Area Network
MSTP Multi Service Transmission Platform
NE Network Element
NG-SDH Next Generation - Synchronous Digital Hierarchy
NM Network Management
NRZ Non Return to Zero
NRZI Non Return to Zero Inverted
OAM Operation, Administration & Maintenance
O/E optical /Electrical conversion
OSN Optical Switch Node
P Provider
PDH Plesiochronous Digital Hierarchy
PE Provider Edge
RSTP Rapid Spanning Tree Protocol
SCC System Control & Communication
SDH Synchronous Digital Hierarchy
SFP Small Form-factor Pluggable
SNCP Sub-Network Connection Protection
STM-N Synchronous Transport Module Level-N
TDM Time Division Multiplex
TM Terminal Multiplexer
EPS Tributary protection switching
VC Virtual Container
VLAN Virtual LAN
VLL Virtual Leased Line
VPLS Virtual Private LAN Service
VPN Virtual Private Network
VP Virtual Path
WAN Wide Area Network

Manual MSE5010

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MSE 5010

M5010/EN FT/A11 Version A

Original signed by Date Name Visa

1.1 Board slots 8

2.1 Classified Board Description 10

2.2 Board Appearance 12

2.6 SEP1/EU04/EU08/OU08/TSB8/ TSB4 27

2.15 PIU Erreur ! Signet non défini.

3.3 E3/DS3 Cable 85

3.4 Power Cable 86

3.5 PGND Cable 88

3.8 Network Cable 91

3.9 Boolean Input/Output Cable 94

3.10 OAM Serial Port Cable 95

3.11 S1 ~ S4/F&f Cable 97

4.1 Board Indicator Description 99

PAGE BLANCHE ("Blank Page")

Version DATE COMMENTS

Fig 1-1 MSE 5010

1.1 Board slots

slot1 slot11 slot6

Fig 1-2 Slot assignment of the MSE 5010

Board Full name Slot available

SLQ4 4 × STM-4 optical interface board slot 11~13

SLD4 2 × STM-4 optical interface board slot 11~13

SL4 STM-4 optical interface board slot 11~13

SLQ1 4 × STM-1 optical interface board slot 11~13

SL1 STM-1 optical interface board slot 11~13

Board Full name Slot available

SPQ4 E4/STM-1 electrical interface board slot 12, 13

PL3 3 × E3/DS3 processing board slot 12, 13

PD3 6 × E3/DS3 processing board slot 12, 13

PQ1 63 × E1 processing board slot 11~13

PQM 63 × E1/T1 processing board slot 11~13

PD1 32 × E1 processing board slot 1, 2, 3, 11, 12,

EGS2 2-Port Gigabit Ethernet optical interface slot 11~13

EFS0 Fast Ethernet Interface Board with slot 12~13

EFS4 4-Port Fast Ethernet processing board slot 11~13

CXL16 STM-16 system control, cross-connect, slot 4, 5

CXL4 STM-4 system control, cross-connect, slot 4, 5

CXL1 STM-1 system control, cross-connect, slot 4, 5

AUX System auxiliary process board slot 10

EOW Engineering Order Wire slot 9

Table 1-1 Processing boards and their corresponding slots

2.1 Classified Board Description

Unit name Board Full name

SLQ4 4 × STM-4 optical interface board

SLD4 2 × STM-4 optical interface board

SL4 STM-4 optical interface board

SLQ1 4 × STM-1 optical interface board

SEP1 8 × STM-1 line processing board

EU04 4 × STM-1 electrical interface board

EU08 8 × STM-1 electrical interface board

OU08 8 × STM-1 optical interface board

PDH interface SPQ4 4 × E4/STM-1 processing board

PD3 6 × E3/DS3 processing board

PL3 3 × E3/DS3 processing board

C34S 3 × E3/DS3 PDH interface switching board

D34S 6 × E3/DS3 PDH interface switching board

PQM 63 × E1/T1 processing board

PQ1 63 × E1 processing board

PD1 32 × E1 processing board