Sumatorul elimentar:

Codul in Verilog:

module lab3a(SlagA,SlagB,Cin,SummaOut,Cout);

input SlagA,SlagB;

input Cin;

output SummaOut;

output Cout;

assign SummaOut = SlagA^SlagB^Cin;

assign Cout = (SlagA&SlagB)^(SlagA^SlagB)&Cin;

endmodule

testare:

module lab3a_TB();

parameter wordlength = 1;

reg [wordlength-1:0] A;

reg [wordlength-1:0] B;

reg Cin;

reg [wordlength:0] AB;

wire [wordlength-1:0] Sout;

wire Cout;

lab3a DUT(A,B,Cin,Sout,Cout);

initial

begin

$monitor("A=%b, B=%b, Cin=%b, SumMod=%b, CoutMod=%b, ControlSum=%b",

A,B,Cin,Sout,Cout,AB);

end

always

begin

#10;

A=$random;

B=$random;

Cin=$random;

AB=A+B+Cin;

end
endmodule

Screenshots:

Sumatorul cu calcul transportului inlantuit:

Codul in verilog:

module lab3b(A,B,Cin, Sout, Cout);

input [3:0] A,B;

input Cin;

output [3:0] Sout;

output Cout;

wire [3:0] Cbus;

lab3a S0(A[0], B[0], 1'b0, Sout[0], Cbus[0]);

lab3a S1(A[1], B[1], Cbus[0], Sout[1], Cbus[1]);

lab3a S2(A[2], B[2], Cbus[1], Sout[2], Cbus[2]);

lab3a S3(A[3], B[3], Cbus[2], Sout[3], Cout);

endmodule

testare:

module lab3b_TB();

parameter wordlength = 4;

reg [wordlength-1:0] A;

reg [wordlength-1:0] B;

reg Cin;

reg [wordlength:0] AB;

wire [wordlength-1:0] Sout;

wire Cout;

lab3b DUT(A,B,Cin,Sout,Cout);

initial

begin

$monitor("A=%b, B=%b, Cin=%b, SumMod=%b, CoutMod=%b, ControlSum=%b",

A,B,Cin,Sout,Cout,AB);

end

always

begin

#10;

A=$random;

B=$random;

Cin=$random;

AB=A+B+Cin;

end

endmodule

Screenshots:

Modulul de calcul transportului anticipat:

Codul in Verilog:

module lab3c(A,B,Cin,C,P,G);

parameter wordlength = 4;

input [wordlength :0] A;

input [wordlength :0] B;

input Cin;

output [wordlength :0] C,P,G;

assign P[0]=0;

assign G[0]=0;

assign P[1]=A[1]^B[1];

assign G[1]=A[1]&B[1];

assign P[2]=A[1]^B[1];

assign G[2]=A[1]&B[1];

assign P[3]=A[1]^B[1];

assign G[3]=A[1]&B[1];

assign P[4]=A[1]^B[1];

assign G[4]=A[1]&B[1];

assign C[0] = Cin;

assign C[1] = P[1]*Cin+G[1];

assign C[2] = P[2]*C[1]+G[2];

assign C[3] = P[3]*C[2]+G[3];

assign C[4] = P[4]*C[3]+G[4];

module lab3b(A,B,Cin, Sout, Cout);

input [3:0] A,B;

input Cin;

output [3:0] Sout;

output Cout;

wire [3:0] Cbus;

lab3c C0(A, B, Cin , Cbus);

lab3a S0(A[0], B[0], Cbus[0], Sout[0], 1'bz);

lab3a S1(A[1], B[1], Cbus[1], Sout[1], 1'bz);

lab3a S2(A[2], B[2], Cbus[2], Sout[2], 1'bz);

lab3a S3(A[3], B[3], Cbus[3], Sout[3], 1'bz);

endmodule

endmodule

Testare:

module lab3c_TB();
parameter wordlength = 4;

reg [wordlength-1:0] A;

reg [wordlength-1:0] B;

reg Cin;

reg [wordlength:0] AB;

wire [wordlength-1:0] Sout;

wire Cout;

lab3c DUT(A,B,Cin,Sout,Cout);

initial

begin

$monitor("A=%b, B=%b, Cin=%b, SumMod=%b, CoutMod=%b, ControlSum=%b",

A,B,Cin,Sout,Cout,AB);

end

always

begin

#10;

A=$random;

B=$random;

Cin=$random;

AB=A+B+Cin;

end

endmodule

Screenshots: