4075 PDF

SEMICONDUCTOR TECHNICAL DATA

% !%$ $
%& "# $#
The B Series logic gates are constructed with P and N channel % !%$ $
enhancement mode devices in a single monolithic structure (Complemen-
tary MOS). Their primary use is where low power dissipation and/or high
noise immunity is desired.

• Supply Voltage Range = 3.0 Vdc to 18 Vdc
% !%$ $
• All Outputs Buffered
• Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range. % !%$ $
• Double Diode Protection on All Inputs Except: Triple Diode Protection
on MC14011B and MC14081B
• Pin–for–Pin Replacements for Corresponding CD4000 Series B Suffix

Devices (Exceptions: MC14068B and MC14078B) "! !%$ $

"! !%$ $

!%$ $
L SUFFIX P SUFFIX D SUFFIX
CERAMIC
CASE 632
PLASTIC
CASE 646
SOIC
CASE 751A

% !%$ $
ORDERING INFORMATION

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MC14XXXBCP Plastic
MC14XXXBCL Ceramic
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MC14XXXBD SOIC % !%$ $
TA = – 55° to 125°C for all packages.

MAXIMUM RATINGS* (Voltages Referenced to VSS) "! !%$ $
Symbol Parameter Value Unit
VDD DC Supply Voltage – 0.5 to + 18.0 V

Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V "! !%$ $
lin, lout Input or Output Current (DC or Transient), ± 10 mA

per Pin
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ !%$ $

PD Power Dissipation, per Package† 500 mW
Tstg Storage Temperature – 65 to + 150 _C

TL Lead Temperature (8–Second Soldering) 260 _C
* Maximum Ratings are those values beyond which damage to the device may occur. % !%$ $
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C
% !%$ $
This device contains protection circuitry to guard against damage
due to high static voltages or electric fields. However, precautions must
be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Vin and
Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage
level (e.g., either VSS or VDD). Unused outputs must be left open.
REV 3
1/94
MOTOROLA CMOS LOGIC DATA

Motorola, Inc. 1995 MC14001B
7
LOGIC DIAGRAMS
NOR NAND OR AND
MC14001B MC14011B MC14071B MC14081B

Quad 2–Input NOR Gate Quad 2–Input NAND Gate Quad 2–Input OR Gate Quad 2–Input AND Gate
1 1 1 1
3 3 3 3
2 2 2 2
5 5 5 5
2 INPUT
4 4 4 4
6 6 6 6
8 8 8 8
10 10 10 10
9 9 9 9
12 12 12 12
11 11 11 11
13 13 13 13
MC14025B MC14023B MC14075B MC14073B

Triple 3–Input NOR Gate Triple 3–Input NAND Gate Triple 3–Input OR Gate Triple 3–Input AND Gate
1 1 1 1
2 9 2 9 2 9 2 9
8 8 8 8
3 INPUT
3 3 3 3
4 6 4 6 4 6 4 6
5 5 5 5
11 11 11 11
12 10 12 10 12 10 12 10
13 13 13 13
MC14002B MC14012B MC14072B MC14082B

Dual 4–Input NOR Gate Dual 4–Input NAND Gate Dual 4–Input OR Gate Dual 4–Input AND Gate
2 2 2 2
3 1 3 1 3 1 3 1
4 4 4 4
4 INPUT
5 5 5 5
9 9 9 9
10 13 10 13 10 13 10 13
11 11 11 11
12 12 12 12
NC = 6, 8 NC = 6, 8 NC = 6, 8 NC = 6, 8
MC14078B MC14068B
8–Input NOR Gate 8–Input NAND Gate
VDD = PIN 14
2 2
VSS = PIN 7
3 3
4 4 FOR ALL DEVICES
8 INPUT
5 5
13 13
9 9
10 10
11 11
12 NC = 6, 8 12 NC = 6, 8
MC14001B MOTOROLA CMOS LOGIC DATA

8
PIN ASSIGNMENTS
MC14001B MC14002B MC14011B MC14012B

Quad 2–Input NOR Gate Dual 4–Input NOR Gate Quad 2–Input NAND Gate Dual 4–Input NAND Gate
IN 1A 1 14 VDD OUTA 1 14 VDD IN 1A 1 14 VDD OUTA 1 14 VDD

IN 2A 2 13 IN 2D IN 1A 2 13 OUTB IN 2A 2 13 IN 2D IN 1A 2 13 OUTB
OUTA 3 12 IN 1D IN 2A 3 12 IN 4B OUTA 3 12 IN 1D IN 2A 3 12 IN 4B
OUTB 4 11 OUTD IN 3A 4 11 IN 3B OUTB 4 11 OUTD IN 3A 4 11 IN 3B
IN 1B 5 10 OUTC IN 4A 5 10 IN 2B IN 1B 5 10 OUTC IN 4A 5 10 IN 2B
IN 2B 6 9 IN 2C NC 6 9 IN 1B IN 2B 6 9 IN 2C NC 6 9 IN 1B
VSS 7 8 IN 1C VSS 7 8 NC VSS 7 8 IN 1C VSS 7 8 NC
MC14023B MC14025B MC14068B MC14071B

Triple 3–Input NAND Gate Triple 3–Input NOR Gate 8–Input NAND Gate Quad 2–Input OR Gate
IN 1A 1 14 VDD IN 1A 1 14 VDD NC 1 14 VDD IN 1A 1 14 VDD

IN 2A 2 13 IN 3C IN 2A 2 13 IN 3C IN 1 2 13 OUT IN 2A 2 13 IN 2D
IN 1B 3 12 IN 2C IN 1B 3 12 IN 2C IN 2 3 12 IN 8 OUTA 3 12 IN 1D
IN 2B 4 11 IN 1C IN 2B 4 11 IN 1C IN 3 4 11 IN 7 OUTB 4 11 OUTD
IN 3B 5 10 OUTC IN 3B 5 10 OUTC IN 4 5 10 IN 6 IN 1B 5 10 OUTC
OUTB 6 9 OUTA OUTB 6 9 OUTA NC 6 9 IN 5 IN 2B 6 9 IN 2C
VSS 7 8 IN 3A VSS 7 8 IN 3A VSS 7 8 NC VSS 7 8 IN 1C
MC14072B MC14073B MC14075B MC14078B

Dual 4–Input OR Gate Triple 3–Input AND Gate Triple 3–Input OR Gate 8–Input NOR Gate
OUTA 1 14 VDD IN 1A 1 14 VDD IN 1A 1 14 VDD NC 1 14 VDD

IN 1A 2 13 OUTB IN 2A 2 13 IN 3C IN 2A 2 13 IN 3C IN 1 2 13 OUT
IN 2A 3 12 IN 4B IN 1B 3 12 IN 2C IN 1B 3 12 IN 2C IN 2 3 12 IN 8
IN 3A 4 11 IN 3B IN 2B 4 11 IN 1C IN 2B 4 11 IN 1C IN 3 4 11 IN 7
IN 4A 5 10 IN 2B IN 3B 5 10 OUTC IN 3B 5 10 OUTC IN 4 5 10 IN 6
NC 6 9 IN 1B OUTB 6 9 OUTA OUTB 6 9 OUTA NC 6 9 IN 5
VSS 7 8 NC VSS 7 8 IN 3A VSS 7 8 IN 3A VSS 7 8 NC
MC14081B MC14082B
Quad 2–Input AND Gate Dual 4–Input AND Gate
IN 1A 1 14 VDD OUTA 1 14 VDD

IN 2A 2 13 IN 2D IN 1A 2 13 OUTB
OUTA 3 12 IN 1D IN 2A 3 12 IN 4B
OUTB 4 11 OUTD IN 3A 4 11 IN 3B
IN 1B 5 10 OUTC IN 4A 5 10 IN 2B
IN 2B 6 9 IN 2C NC 6 9 IN 1B
VSS 7 8 IN 1C VSS 7 8 NC NC = NO CONNECTION
MOTOROLA CMOS LOGIC DATA MC14001B

9
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ – 55_C 25_C 125_C
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
VDD
Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit
Output Voltage “0” Level VOL 5.0 — 0.05 — 0 0.05 — 0.05 Vdc
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
Vin = 0 or VDD 10 9.95 — 9.95 10 — 9.95 —
15 14.95 — 14.95 15 — 14.95 —
Input Voltage “0” Level VIL Vdc
(VO = 4.5 or 0.5 Vdc) 5.0 — 1.5 — 2.25 1.5 — 1.5
(VO = 9.0 or 1.0 Vdc) 10 — 3.0 — 4.50 3.0 — 3.0
(VO = 13.5 or 1.5 Vdc) 15 — 4.0 — 6.75 4.0 — 4.0
“1” Level VIH Vdc
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 — 3.5 2.75 — 3.5 —
(VO = 1.0 or 9.0 Vdc) 10 7.0 — 7.0 5.50 — 7.0 —
(VO = 1.5 or 13.5 Vdc) 15 11 — 11 8.25 — 11 —
Output Drive Current IOH mAdc
(VOH = 2.5 Vdc) Source 5.0 – 3.0 — – 2.4 – 4.2 — – 1.7 —
(VOH = 4.6 Vdc) 5.0 – 0.64 — – 0.51 – 0.88 — – 0.36 —
(VOH = 9.5 Vdc) 10 – 1.6 — – 1.3 – 2.25 — – 0.9 —
(VOH = 13.5 Vdc) 15 – 4.2 — – 3.4 – 8.8 — – 2.4 —
(VOL = 0.4 Vdc) Sink IOL 5.0 0.64 — 0.51 0.88 — 0.36 — mAdc
(VOL = 0.5 Vdc) 10 1.6 — 1.3 2.25 — 0.9 —
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —
Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Input Capacitance Cin — — — — 5.0 7.5 — — pF
(Vin = 0)
Quiescent Current IDD 5.0 — 0.25 — 0.0005 0.25 — 7.5 µAdc
(Per Package) 10 — 0.5 — 0.0010 0.5 — 15
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 — 1.0 — 0.0015 1.0 — 30
Total Supply Current**† IT 5.0 IT = (0.3 µA/kHz) f + IDD/N µAdc
(Dynamic plus Quiescent, 10 IT = (0.6 µA/kHz) f + IDD/N
Per Gate, CL = 50 pF) 15 IT = (0.9 µA/kHz) f + IDD/N
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.001 x the number of exercised gates per
package.

10
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ B–SERIES GATE SWITCHING TIMES
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)
VDD
Characteristic Symbol Vdc Min Typ # Max Unit
Output Rise Time, All B–Series Gates tTLH ns
tTLH = (1.35 ns/pF) CL + 33 ns 5.0 — 100 200
tTLH = (0.60 ns/pF) CL + 20 ns 10 — 50 100
tTLH = (0.40 ns/PF) CL + 20 ns
15 — 40 80
Output Fall Time, All B–Series Gates tTHL ns
tTHL = (1.35 ns/pF) CL + 33 ns 5.0 — 100 200
tTHL = (0.60 ns/pF) CL + 20 ns 10 — 50 100
tTHL = (0.40 ns/pF) CL + 20 ns
15 — 40 80
Propagation Delay Time tPLH, tPHL ns
MC14001B, MC14011B only
tPLH, tPHL = (0.90 ns/pF) CL + 80 ns 5.0 — 125 250
tPLH, tPHL = (0.36 ns/pF) CL + 32 ns 10 — 50 100
All Other 2, 3, and 4 Input Gates
8–Input Gates (MC14068B, MC14078B)
* The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
14 VDD 20 ns 20 ns
VDD
INPUT 90%
INPUT 50%
PULSE 10% 0V
OUTPUT tPHL tPLH
GENERATOR
CL 90% VOH
* 50%
OUTPUT 10%
INVERTING VOL
tTHL tTLH
tPLH tPHL
7 VSS OUTPUT VOH
90%
NON–INVERTING 50%
* All unused inputs of AND, NAND gates must be connected to VDD. 10% VOL
All unused inputs of OR, NOR gates must be connected to VSS. tTLH tTHL
Figure 1. Switching Time Test Circuit and Waveforms

11
CIRCUIT SCHEMATIC
NOR, OR GATES
MC14001B, MC14071B
One of Four Gates Shown
VDD
14 VDD
1, 6, 8, 13
*
2, 5, 9, 12
3, 4, 10, 11
MC14025B, MC14075B
One of Three Gates Shown
7 VSS VDD
VSS
1, 3, 11
* Inverter omitted in MC14001B
2, 4, 12
14 VDD
*
MC14002B, MC14072B
One of Two Gates Shown VSS
9, 6, 10
VDD VDD
3, 9
8, 5, 13
2, 10
7 VSS
14 VDD
VSS
* * Inverter omitted in MC14025B
VSS 1, 13
5, 11 SAME AS
4, 12 ABOVE
7 VSS
VDD MC14078B
Eight Input Gate
2
14 VDD
VSS
4 SAME AS
5 ABOVE
SAME AS 13
9
10 ABOVE
11 SAME AS
12 ABOVE
7 VSS

12
CIRCUIT SCHEMATIC
NAND, AND GATES
MC14011B, MC14081B
One of Four Gates Shown
14 VDD
MC14023B, MC14073B
3, 4, 10, 11
One of Three Gates Shown
VDD 2, 5, 9, 12
1, 6, 8, 13
7 VSS
2, 4, 12 14 VDD
1, 3, 11
VSS
*
VDD
9, 6, 10
MC14012B, MC14082B
8, 5, 13
One of Two Gates Shown
VDD
7 VSS
VSS
14 VDD
MC14068B
VDD Eight Input Gate 2, 10
*
3, 9
VSS
1, 13
4, 12 SAME AS
VDD 5, 11 ABOVE
2
* Inverter omitted in MC14012B 7 VSS
VSS
5 SAME AS
4 ABOVE
14 VDD
VSS
VDD
9 SAME AS
13
10 ABOVE
11 SAME AS
12 ABOVE
7 VSS
VSS

13
TYPICAL B–SERIES GATE CHARACTERISTICS
N–CHANNEL DRAIN CURRENT P–CHANNEL DRAIN CURRENT

(SINK) (SOURCE)
5.0 – 10
– 9.0
4.0 – 8.0 TA = – 55°C
ID , DRAIN CURRENT (mA)

– 7.0
TA = – 55°C – 40°C
3.0 – 6.0
– 40°C
– 5.0
+ 85°C + 25°C + 25°C
2.0 – 4.0 + 85°C
+ 125°C
– 3.0 + 125°C
1.0 – 2.0
– 1.0
0 0
0 1.0 2.0 3.0 4.0 5.0 0 – 1.0 – 2.0 – 3.0 – 4.0 – 5.0
VDS, DRAIN–TO–SOURCE VOLTAGE (Vdc) VDS, DRAIN–TO–SOURCE VOLTAGE (Vdc)
Figure 2. VGS = 5.0 Vdc Figure 3. VGS = – 5.0 Vdc
20 – 50
18 – 45
TA = – 55°C
16 – 40
14 – 40°C – 35
12 + 25°C – 30 TA = – 55°C
+ 85°C
10 – 25 – 40°C
8.0 + 125°C – 20 + 25°C
+ 85°C
6.0 – 15
4.0 – 10 + 125°C
2.0 – 5.0
0 0
0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10 0 – 1.0 – 2.0 – 3.0 – 4.0 – 5.0 – 6.0 – 7.0 – 8.0 – 9.0 – 10
Figure 4. VGS = 10 Vdc Figure 5. VGS = – 10 Vdc
50 – 100
45 – 90
40 – 80
35 TA = – 55°C – 70
30 – 40°C – 60
TA = – 55°C
25 + 25°C – 50 – 40°C
20 + 85°C – 40 + 25°C
+ 125°C + 85°C
15 – 30
+ 125°C
10 – 20
5.0 – 10
0 0
0 2.0 4.0 6.0 8.0 10 12 14 16 18 20 0 – 2.0 – 4.0 – 6.0 – 8.0 – 10 – 12 – 14 – 16 – 18 – 20
Figure 6. VGS = 15 Vdc Figure 7. VGS = – 15 Vdc

These typical curves are not guarantees, but are design aids.
Caution: The maximum rating for output current is 10 mA per pin.

14
TYPICAL B–SERIES GATE CHARACTERISTICS (cont’d)
V out , OUTPUT VOLTAGE (Vdc) VOLTAGE TRANSFER CHARACTERISTICS
V out , OUTPUT VOLTAGE (Vdc)

SINGLE INPUT NAND, AND SINGLE INPUT NAND, AND
5.0 MULTIPLE INPUT NOR, OR MULTIPLE INPUT NOR, OR
10
4.0 8.0
SINGLE INPUT NOR, OR SINGLE INPUT NOR, OR
3.0 MULTIPLE INPUT NAND, AND 6.0 MULTIPLE INPUT NAND, AND
2.0 4.0
1.0 2.0
0 0
0 1.0 2.0 3.0 4.0 5.0 0 2.0 4.0 6.0 8.0 10
Vin, INPUT VOLTAGE (Vdc) Vin, INPUT VOLTAGE (Vdc)
Figure 8. VDD = 5.0 Vdc Figure 9. VDD = 10 Vdc
16 DC NOISE MARGIN
SINGLE INPUT NAND, AND
14 MULTIPLE INPUT NOR, OR The DC noise margin is defined as the input voltage range
V out , OUTPUT VOLTAGE (Vdc)
from an ideal “1” or “0” input level which does not produce
12
output state change(s). The typical and guaranteed limit val-
SINGLE INPUT NOR, OR
10 MULTIPLE INPUT NAND, AND
ues of the input values VIL and VIH for the output(s) to be at a
fixed voltage VO are given in the Electrical Characteristics
8.0 table. VIL and VIH are presented graphically in Figure 11.
Guaranteed minimum noise margins for both the “1” and
6.0
“0” levels =
4.0 1.0 V with a 5.0 V supply
2.0 2.0 V with a 10.0 V supply
2.5 V with a 15.0 V supply
0
0 2.0 4.0 6.0 8.0 10
Vin, INPUT VOLTAGE (Vdc)
Figure 10. VDD = 15 Vdc
Vout VDD Vout VDD
VO VO
VO VO
VDD VDD
0 Vin 0 Vin
VIL VIH VIL VIH

VSS = 0 VOLTS DC
(a) Inverting Function (b) Non–Inverting Function
Figure 11. DC Noise Immunity

15
OUTLINE DIMENSIONS
L SUFFIX
CERAMIC DIP PACKAGE
CASE 632–08
ISSUE Y
–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
14 9 Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
–B– 3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
1 7 4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
C L BODY.
INCHES MILLIMETERS
DIM MIN MAX MIN MAX
A 0.750 0.785 19.05 19.94
B 0.245 0.280 6.23 7.11
–T– C 0.155 0.200 3.94 5.08
SEATING
K D 0.015 0.020 0.39 0.50
PLANE F 0.055 0.065 1.40 1.65
G 0.100 BSC 2.54 BSC
F G N M J 0.008 0.015 0.21 0.38
K 0.125 0.170 3.18 4.31
D 14 PL J 14 PL L 0.300 BSC 7.62 BSC
M 0_ 15_ 0_ 15_
0.25 (0.010) M T A S
0.25 (0.010) M T B S N 0.020 0.040 0.51 1.01
P SUFFIX
PLASTIC DIP PACKAGE
CASE 646–06 NOTES:
ISSUE L 1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE
POSITION AT SEATING PLANE AT MAXIMUM
14 8 MATERIAL CONDITION.
2. DIMENSION L TO CENTER OF LEADS WHEN
B FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD
1 7 FLASH.
4. ROUNDED CORNERS OPTIONAL.
INCHES MILLIMETERS
A DIM MIN MAX MIN MAX
A 0.715 0.770 18.16 19.56
F L B 0.240 0.260 6.10 6.60
C 0.145 0.185 3.69 4.69
D 0.015 0.021 0.38 0.53
F 0.040 0.070 1.02 1.78
C G 0.100 BSC 2.54 BSC
H 0.052 0.095 1.32 2.41
J J 0.008 0.015 0.20 0.38
N K 0.115 0.135 2.92 3.43
L 0.300 BSC 7.62 BSC
SEATING
PLANE K M 0_ 10_ 0_ 10_
H G D M N 0.015 0.039 0.39 1.01

16
OUTLINE DIMENSIONS
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751A–03
ISSUE F NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
–A– Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
14 8 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
–B– P 7 PL 5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
1 7
0.25 (0.010) M B M PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
MILLIMETERS INCHES
G R X 45 _ F DIM MIN MAX MIN MAX
C A 8.55 8.75 0.337 0.344
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
–T– F 0.40 1.25 0.016 0.049
K M J G 1.27 BSC 0.050 BSC
SEATING D 14 PL
PLANE J 0.19 0.25 0.008 0.009
0.25 (0.010) M T B S A S K 0.10 0.25 0.004 0.009
M 0_ 7_ 0_ 7_
P 5.80 6.20 0.228 0.244
R 0.25 0.50 0.010 0.019
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided
in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters,
including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent
rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant
into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a
situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application,
Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or
unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered
trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
How to reach us:

USA/EUROPE/Locations Not Listed: Motorola Literature Distribution; JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center,
P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 or 602–303–5454 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–81–3521–8315
MFAX: RMFAX0@email.sps.mot.com – TOUCHTONE 602–244–6609 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park,
INTERNET: http://Design–NET.com 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298
*MC14001B/D*
◊
MC14001B/D
17

4075 PDF

Hochgeladen von

Dokumentinformationen

Originaltitel

Copyright

Verfügbare Formate

Dieses Dokument teilen

Dokument teilen oder einbetten

Freigabeoptionen

Stufen Sie dieses Dokument als nützlich ein?

Sind diese Inhalte unangemessen?

Copyright:

Verfügbare Formate

4075 PDF

Hochgeladen von

Copyright:

Verfügbare Formate



SEMICONDUCTOR TECHNICAL DATA

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ  !%$  $

MOTOROLA CMOS LOGIC DATA

NOR NAND OR AND

MC14001B MC14011B MC14071B MC14081B

MC14025B MC14023B MC14075B MC14073B

MC14002B MC14012B MC14072B MC14082B

MC14001B MOTOROLA CMOS LOGIC DATA

MC14001B MC14002B MC14011B MC14012B

IN 1A 1 14 VDD OUTA 1 14 VDD IN 1A 1 14 VDD OUTA 1 14 VDD

MC14023B MC14025B MC14068B MC14071B

IN 1A 1 14 VDD IN 1A 1 14 VDD NC 1 14 VDD IN 1A 1 14 VDD

MC14072B MC14073B MC14075B MC14078B

OUTA 1 14 VDD IN 1A 1 14 VDD IN 1A 1 14 VDD NC 1 14 VDD

IN 1A 1 14 VDD OUTA 1 14 VDD

MOTOROLA CMOS LOGIC DATA MC14001B

MC14001B MOTOROLA CMOS LOGIC DATA

Figure 1. Switching Time Test Circuit and Waveforms

MOTOROLA CMOS LOGIC DATA MC14001B

MC14001B MOTOROLA CMOS LOGIC DATA

MOTOROLA CMOS LOGIC DATA MC14001B

N–CHANNEL DRAIN CURRENT P–CHANNEL DRAIN CURRENT

ID , DRAIN CURRENT (mA)

Figure 2. VGS = 5.0 Vdc Figure 3. VGS = – 5.0 Vdc

ID , DRAIN CURRENT (mA)

Figure 4. VGS = 10 Vdc Figure 5. VGS = – 10 Vdc

ID , DRAIN CURRENT (mA)

Figure 6. VGS = 15 Vdc Figure 7. VGS = – 15 Vdc

MC14001B MOTOROLA CMOS LOGIC DATA

V out , OUTPUT VOLTAGE (Vdc) VOLTAGE TRANSFER CHARACTERISTICS

V out , OUTPUT VOLTAGE (Vdc)

Figure 8. VDD = 5.0 Vdc Figure 9. VDD = 10 Vdc

Figure 10. VDD = 15 Vdc

Vout VDD Vout VDD

VIL VIH VIL VIH

Figure 11. DC Noise Immunity

MOTOROLA CMOS LOGIC DATA MC14001B

MC14001B MOTOROLA CMOS LOGIC DATA

How to reach us:

Das könnte Ihnen auch gefallen

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ !%$ $