Geetha Shishu Shikshana Sangha (R)

(Affiliated to VTU, Belagavi, Approved by AICTE, New Delhi & Govt. of Karnataka)
K R S Road, Metagalli, Mysuru – 570016
Accredited with Grade ‘A’ by NAAC
Department of Electronics and Communication Engineering
Accredited Branches by NBA, New Delhi UG – ECE (Validity: 01.07.2017 – 30.06.2020)

Semester & Year: 6th Sem 2020 Faculty Name: Padma R

Subject with Code: Digital System Design using Verilog ( 17EC663)

Course Outcomes:
After the completion of the course the student will be able to

CO1: Construct the combinational and sequential circuits, using discrete gates and programmable logic
devices.

CO2: Design a semiconductor memory for specific chip design

CO3: Understand the Various fabrication steps involved in the manufacturing of IC’s.
CO4: Synthesize different types of I/O controllers that are used in embedded system.
CO5: Learn IC Design methodology and ways to optimize and test it.

Course
Chapter Sub Titles Days Outcomes
Title
Introduction and Methodology:
 Digital Systems and Embedded Systems, 1
 Real-World Circuits 2
 Models 3 CO1

 Design Methodology . 4

 Combinational Basics: Combinational Components and Circuits 5

Module1
 Combinational Basics: Combinational Components and Circuits 6
7
 Verification of Combinational Circuits.
8
 Verification of Combinational Circuits.
9
 Sequential Basics: Sequential Datapaths
10
 Control Clocked Synchronous Timing Methodology
 Memories: Concepts 11

Module2 Memory Types 12-15 CO2

Error Detection and Correction 16-20

Implementation Fabrics: Integrated Circuits 21-23

Programmable Logic Devices 24-26
Module 3 CO3
Packaging and Circuit boards 27-28
Interconnection and Signal integrity 29-30
I/O interfacing: I/O devices 31-32
I/O controllers 33-34
Module 4 Parallel Buses 35-36 CO4
Serial Transmission 37-38
I/O software 39-40
Design Methodology: 41-42
Design flow 43-44
Module 5 Design optimization 45-46 CO5
Design for test 47-48
Nontechnical Issues 49-50

TEXT BOOKS:Text Book: Peter J. Ashenden, “Digital Design: An Embedded Systems Approach
Using VERILOG”, Elesvier, 2010

Signature of the Faculty HOD ECE