Dr.

Bonomali Khuntia
Berhampur University
Oct’2019
 Carry Look-Ahead Adder
Refer page no. 372, CO by Hamacher

 Avoids the slow carry-ripple affect of the parallel adder

circuit

 Carry ripple is very intuitive, but inefficient – must

sequence through all low order bit positions.

 A less intuitive, but more efficient method calculates

the carries in advance: carry look-ahead.
 Implement a Full Adder using two Half-Adders.

Carry propagate function & P  A  B

i i i
Carry generate function
Gi  Ai Bi

Si  Pi  Ci
Ci 1  Pi Ci  Gi

C1=P0C0+G0
C2=P1P0C0+P1G0+G1
C3=P2C2+G2=P2P1P0C0+P2P1G0+P2G1+G2
C4=P3C3+G3=P3P1P0C0+P3P2P1G0+P3P2G1+P3G2+G3
A 4-bit Carry Look-Ahead Adder

B cell B cell B cell B cell

PG=P3P2P1P0
GG=G3+P3G2+P3P2G1+P3P2P1G0
 A 4-bit Carry Look-Ahead Adder(Contd…)
 The gate delays for the n-bit ripple adder is given
as 2n for cn bits and 2n−1 for sn−1 for the circuit as shown
below:

 But, for a 4-bit Carry Look Ahead Adder we have 3 gate

delays for all carry bits and 4 gate delays for all sum bits,
while it is stated as 7 and 8 in case of ripple adders.
 Integer Arithmetic

1. Addition/Subtraction with:
 Sign & Magnitude Numbers
 Two’s Complement Numbers
2. Multiplication, Booth’s Algorithm
3. Floating Point Representation

Computer Arithmetic: Chapter 10, CA By Morris Mano

 Addition and Subtraction
with Signed-Magnitude Number

Signed-Magnitude Number Signed-

Number
 A sign-magnitude number Z Magnitude
can be represented as (As, A) +3 0 11
where As is the sign of Z and
A is the magnitude of Z. +2 0 10
 The leftmost position, As, is +1 0 01
the sign bit.
+0 0 00
 The sign bit is either positive
= 0 or negative = 1 -0 1 00
-1 1 01
-2 1 10
-3 1 11
 Eight Conditions for Signed-Magnitude
Addition/Subtraction
ADD SUBTRACT Magnitudes
Operation
Magnitudes A> B A< B A= B
(+A) + (+B) + (A + B)
(+A) + (-B) + (A – B ) - (B – A ) + (A – B )
(-A) + (+B) - (A – B ) + (B – A ) + (A – B )
(-A) + (-B) - ( A + B)
(+A) - (+B) + (A – B ) - (B – A ) + (A – B )
(+A) - (-B) + (A + B)
(-A) - (+B) - ( A + B)
(-A) - (-B) - (A – B ) + (B – A ) + (A – B )

Semester Exam Qn. (2016) : 16 Marks

 Addition and Subtraction
with Signed-Magnitude Number
Addition (subtraction) Algorithm

 When the sign of A and B are identical (different),

add the magnitudes and attach the sign of A to the
result.

 When the signs of A and B are different (identical),

compare the magnitudes and subtract the smaller
number from the larger.
 Choose the sign of result to be same as A if A>B
 or the complement of sign of A if A<B
 if A=B subtract B from A and make the sign of result
positive
 Examples
Example of adding two +3 0 011
magnitudes when the
result is the sign of both
+ +2 0 010
operands: +5 0 101

Example of adding two -3 1 011

magnitudes when the result + +2 0 010
is the sign of the larger
-( +3 011
magnitude:
- +2) 010
- 1 1 001
 Summary of Addition and Subtraction
with Signed-Magnitude Number
 The signs use an exclusive OR gate where if the output is 0,
then the signs are the same.
 Hence, add the magnitudes of the same signed numbers.
If the sum is an overflow, then a carry is stored in E where
E = 1 and transferred to the flip-flop AVF, add-overflow.
 Otherwise, the signs are opposite and subtraction is
initiated and stored in A.
 No overflow can occur with subtraction so the AVF is
cleared.
 If E = 1, then A > B.
 However, if A = 0, then A = B and the sign is made positive.
 If E = 0, then A < B and sign for A is complemented.
 Hardware Implementation

Bs B Register

M (ModeControl)
AVF Complementer

E Parallel Adder
Output Carry Input Carry

As A Register Load Sum

Simple procedure require magnitude comparator, an adder, two subtractor however

alternative reveals that using 2’s complement for operation requires only an adder and a
complementor

M=0 output = A+B M=1 output = A+B’+1= A-B

Flowchart of Addition and Subtraction
with Signed-Magnitude Data
 Addition and Subtraction
with Signed Two’s Complement Data
Algorithm
 Signed 2’s Complement Representation
 Addition :
 Addition of two numbers in signed 2’s complement form
consists of adding the numbers with the sign bits treated
the same as the other bits of the number. Carry out of sign
bit is discarded.
 Sum is obtained by adding the content of AC and BR
(including the sign bit). Overflow bit is set to 1 if EX-OR
of last two carries is 1.

Subtraction :
 Here Subtraction consists of first taking the 2’s
complement of the subtrahend and then adding it to
minuend.

 Subtraction done by adding the content of AC to 2’s

Complement of BR.
THANK YOU