Laboratory practice 11.
Binary Counters
Jesús Alejandro Marrufo Reyes
Guillermo Antonio Matos Uc
Carlos Andrés Solis Pech
Pablo Alberto Villoria Quiñones
Mérida, México
Faculty of Engineering UADY
Abstract — This laboratory practice consisted in design and
implement one binary counter using a hierarchical structured
VHDL code. The objective of the circuit was to modify the
frequency of the FPGA clock signal from 50 MHz to 1 Hz in
order to count from the number 0 to 9 in binary and show the
result in four different leds and also obtain its decimal
representation in one 7-segment display.
I. INTRODUCTION
A counter is a “sequential circuit that goes through a
prescribed sequence of state upon the application of input
pulses” [1].
The circuits inside the counters consist in a series of
synchronized flip-flops, interconnected with logic gates that
enables the flip-flops to follow a certain sequence of states.
“In a counter, the sequence of states may follow a binary
count or any other sequence of states”[1].
Counters are found in many equipments that contain
digital logic for counting the number of occurrences of an
event. They are also useful for control operations because they
generate timing sequences in a digital system.
A binary counter follows the binary sequence.
II. DESIGN OF THE CIRCUIT
In order to implement the binary counter, we must design
two counters that work together: the first one will generate a
1 second signal, that divides the main clock from 50 MHz to
1 Hz. The second counter will serve to count 10 counts from
the first clock, thats is, 10 seconds. After this process is
finished, the clock must reset to 0.
The following schematic diagram shows the binary
counter architecture implemented on this laboratory practice:
Fig 2.1. Schematic diagram of the binary counter.
The physical circuit must work according to these
restrictions:
● The circuit must start from 0 and add 1 each second
until it reaches the number 9.
● The binary number must be shown in 4 different leds
and the circuit has to obtain the decimal
representation of each number and show it in one 7-
segment display.
● When the count reaches the number 9, it has to be
restarted from 0.
III. IMPLEMENTATION OF THE CIRCUIT
The logical circuit shown in fig. 2.1 was implemented in a
hierarchical structured VHDL code using the software ISEE
Design Suite in order to program the binary counter.
The VHDL code was written based in the figure 2.1 and
those three important points. First, the top module of the
binary counter was implemented declaring three entry signals
and two out signals:
clkr : in std_logic;
clr : in std_logic;
led : out std_logic_vector(3 downto 0);
seg : out std_logic_vector(6 downto 0);
ann : out std_logic_vector(3 downto 0);
The circuit has two important inputs and three outputs.
The 50 MHz input signal was declared as “clkr” and the reset
signal was named “clr”. The outputs “led”, “seg” and “ann”
controlled the leds and the 7-segment display to show the
binary and decimal representation of the numbers.
The first step of the binary counter implementation
consisted in design one frequency converter to transform the
frequency of the FPGA clock signal from 50 MHz to 1 Hz,
this means that the counter should behave like a basic
chronometer adjusted to count in seconds. This entity
consisted in two signals: one input and output.
clk50mhz: in std_logic;
clk: out std_logic;
This counter generates a 1 Hz pulse for each 50 × 106
pulses of the input signal using two if processes. With this
entity, it was possible to convert the frequency of the FPGA
main clock from 50 MHz to 1 Hz.
The output signal of the frequency converter was
introduced in a second entity that consisted in another binary
counter that counts from 0 to 9 adding 1 to the previous
number each second. The inputs and output were:
clk, st : in std_logic;
cnt_out : out std_logic_vector(3 downto 0);
The 1 Hz input signal was declared as “clk” and the reset
signal was named “st”. The counter adds 1 to one binary
number for each pulse of the input signal and generates a
binary number from 0000 to 1001. Finally, the output was
connected to three different leds of the FPGA to show the
binary representation of each number.
Finally, the 4-bit binary number was introduced to one
decoder to show its decimal representation on a 7-segment
display.
A testbench file based in the architecture was created and,
with this, the logical circuit was simulated in the ISim tool to
analyze the waveforms of each output.
Fig. 2.2. Waveforms of the clock input and the states of leds and 7-segment
display leds..
, 2008, p.243.
The binary counter designed worked correctly. Finally, the
UCF file was created to program the FPGA with it and the
physical circuit worked exactly as its behavior was defined.
1- What is the amount of LUT’s used in the synthesis?
17 out of 1920..
2- What is the amount of FlipFlops used in the synthesis?
4 out of 1920.
3- What is the amount of IOB’s used in the synthesis?
17 out of 83.
4- What is the total percentage of logic gates used in the
design?
122 out of 100000 were used, 0.00122%.
CONCLUSIONS
Its important to now how it works the clock of the FPGA to
made good works and to easier some works that needs to wait
and a counter, another option for this work is made a
chronometer or a clock with the specific hour and use this for
another projects that need it, principally in the Finite state
Machine.
REFERENCES
[1] M. Mano, Digital logic and computer design, 1st ed. New Delhi:
Prentice-Hall of India