Errata 80161d

PIC18FXX8
PIC18FXX8 Rev. C0 Silicon/Data Sheet Errata

The PIC18FXX8 Rev. C0 parts you have received con- 2. Module: Data EEPROM
form functionally to the Device Data Sheet
(DS41159C), except for the anomalies described When reading the data EEPROM, the contents of
below. the EEDATA register may be corrupted if the RD
bit (EECON1<0>) is set immediately following a
All the problems listed here will be addressed in future write to the address byte (EEADR). The actual
revisions of the PIC18FXX8 silicon. contents of the data EEPROM remain unaffected.
The following silicon errata apply only to
Work around
PIC18FXX8 devices with these Device/Revision
IDs: Do not set EEADR immediately before the
execution of a read. Write to EEADR at least one
Part Number Device ID Revision ID instruction cycle before setting the RD bit. The
PIC18F248 00 1000 000 00101 instruction between the write to EEADR and the
read can be any valid instruction, including a NOP.
PIC18F258 00 1000 010 00101
PIC18F448 00 1000 001 00101 Date Codes that pertain to this issue:
PIC18F458 00 1000 011 00101 All engineering and production devices.
The Device IDs (DEVID1 and DEVID2) are located at
addresses 3FFFFEh:3FFFFFh in the device’s 3. Module: A/D (External Voltage Reference)
configuration space. They are shown in hexadecimal and Comparator Voltage
in the format “DEVID2 DEVID1”. Reference
When the external voltage reference, VREF-, is
1. Module: Core (Program Memory Space) selected for use with either the A/D or comparator
voltage reference, AVSS is connected to VREF- in
Performing table read operations above the user
the comparator module. If VREF- is a voltage other
program memory space (addresses over 1FFFFFh)
than AVSS (which must be tied externally to VSS),
may yield erroneous results at the extreme low end
excessive current will flow into the VREF- pin.
of the device’s rated temperature range (-40°C).
This applies specifically to addresses above Work around
1FFFFFh, including the user ID locations If external VREF- is used with a voltage other than
(200000h-200007h), the configuration bytes 0V, enable the comparator voltage reference by
(300000h-30000Dh) and the device ID locations setting the CVREN bit in the CVRCON register.
(3FFFFEh and 3FFFFFh). User program memory This disconnects VREF- and AVSS within the
is unaffected. comparator module.
Work around
Two possible work arounds are presented. Other
solutions may exist.
1. Do not perform table read operations on areas
above the user memory space at -40°C.
2. Insert NOP instructions (specifically, literal
FFFFh) around any table read instructions. The
suggested optimal number is 4 instructions
before and 8 instructions after each table read.
This may vary depending upon the particular
application, and should be optimized by the user.
Date Codes that pertain to this issue:
All engineering and production devices.
 2004 Microchip Technology Inc. DS80161D-page 1

PIC18FXX8
4. Module: Core (Instruction Set) 6. Module: MSSP (All I2C™ and
SPI™ Modes)
The Decimal Adjust W register instruction, DAW,
may improperly clear the CARRY bit (Status<0>) The Buffer Full (BF) flag bit of the SSPSTAT register
when executed. (SSPSTAT<0>) may be inadvertently cleared even
when the SSPBUF register has not been read. This
Work around
will occur only when the following two conditions
Test the CARRY bit state before executing the DAW occur simultaneously:
instruction. If the CARRY bit is set, increment the
• The four Least Significant bits of the BSR
next higher byte to be added using an instruction
register are equal to 0Fh (BSR<3:0> = 1111);
such as INCFSZ (this instruction does not affect
and
any Status flags and will not overflow a BCD nib-
ble). After the DAW instruction has been executed, • Any instruction that contains C9h in its 8 Least
process the CARRY bit normally (see Example 1). Significant bits (i.e., register file addresses,
literal data, address offsets, etc.) is executed.
EXAMPLE 1: PROCESSING THE CARRY Work around
BIT DURING BCD ADDITIONS All work arounds will involve setting the contents of
MOVLW 0x80 ; .80 (BCD) BSR<3:0> to some value other than 0Fh.
ADDLW 0x80 ; .80 (BCD)
In addition to those proposed below, other
BTFSC STATUS,C ; test C solutions may exist.
INCFSZ byte2 ; inc next higher LSB
1. When developing or modifying code, keep
DAW
BTFSC STATUS,C ; test C
these guidelines in mind:
INCFSZ byte2 ; inc next higher LSB • Assign 12-bit addresses to all variables.
This allows the assembler to know when
This is repeated for each DAW instruction. Access Banking can be used.
• Do not set the BSR to point to Bank 15
(BSR = 0Fh).
5. Module: CAN
• Allow the assembler to manipulate the
CAN Disable mode change request is not access bit present in most instructions.
confirmed. A CAN Disable mode request by writing Accessing the SFRs in Bank 15 will be done
‘001’ to the REQOP bits (CANCON<5:7>) immedi- through the Access Bank. Continue to use
ately changes the OPMODE bits (CANSTAT<5:7>), the BSR to select all GPR Banks.
implying that Disable mode is accepted. This occurs 2. If accessing a part of Bank 15 is required and
even though the CAN module itself may not have the use of Access Banking is not possible,
switched its state. consider using indirect addressing.
Work around 3. If pointing the BSR to Bank 15 is unavoidable,
review the absolute file listing. Verify that no
Switch to Configuration mode instead. Wake-up instructions contain C9h in the 8 Least
from CAN bus activity will continue to work even in Significant bits while the BSR points to Bank 15
Configuration mode. (BSR = 0Fh).
DS80161D-page 2  2004 Microchip Technology Inc.

PIC18FXX8
7. Module: MSSP (SPI, Slave Mode)
In its current implementation, the SS (Slave
Select) control signal generated by an external
master processor may not be successfully
recognized by the PIC® microcontroller operating
in Slave Select mode (SSPM3:SSPM0 = 0100). In
particular, it has been observed that faster
transitions (those with shorter fall-times) are more
likely to be missed than than slower transitions.
Work around
Insert a series resistor between the source of the
SS signal and the corresponding SS input line of
the microcontroller. The value of the resistor is
dependent on both the application system’s
characteristics and process variations between
microcontrollers. Experimentation and thorough
testing is encouraged.
This is a recommended solution. Others may exist.

PIC18FXX8
Clarifications/Corrections to the Data 2. Module: DC Characteristics Table
Sheet: In Section 27.1 “DC Characteristics”, the table’s
In the Device Data Sheet (DS41159C), the following Typ and Max values (on the following pages) have
clarifications and corrections should be noted. been updated. The changes are shown in bold
text.
1. Module: A/D (VREF+ and VREF-
References)
The operation of the module is clarified by the
addition of the following note to the end of
Section 20.1 “A/D Acquisition Requirements”:
Note: When using external voltage references
with the A/D converter, the source
impedance of the external voltage refer-
ences must be less than 20Ω to obtain the
specified A/D resolution. Higher reference
source impedances will increase both
offset and gain errors. Resistive voltage
dividers will not provide a sufficiently low
source impedance.
To maintain the best possible performance
in A/D conversions, external VREF inputs
should be buffered with an operational
amplifier or other low output impedance
circuit.

PIC18FXX8
27.1 DC Characteristics
PIC18LFXX8 Standard Operating Conditions (unless otherwise stated)
(Industrial) Operating temperature -40°C ≤ TA ≤ +85°C for industrial
Standard Operating Conditions (unless otherwise stated)
PIC18FXX8
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
(Industrial, Extended)
-40°C ≤ TA ≤ +125°C for extended
Param Characteristic/
Symbol Min Typ Max Units Conditions
No. Device
VBOR Brown-out Reset Voltage
PIC18LFXX8
D005 BORV1:BORV0 = 11 1.96 — 2.16 V
BORV1:BORV0 = 10 2.64 — 2.92 V
BORV1:BORV0 = 01 4.07 — 4.59 V
BORV1:BORV0 = 00 4.36 — 4.92 V
PIC18FXX8
D005 BORV1:BORV0 = 1x N.A. — N.A. V Not in operating voltage range of device
BORV1:BORV0 = 01 4.07 — 4.59 V
BORV1:BORV0 = 00 4.36 — 4.92 V
Legend: Rows are shaded for improved readability.
Note 1: This is the limit to which VDD can be lowered in Sleep mode, or during a device Reset, without losing RAM
data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O
pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have
an impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is
measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD and VSS
and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, ...).
4: For RC osc configuration, current through REXT is not included. The current through the resistor can be
estimated by the formula Ir = VDD/2 REXT (mA) with REXT in kΩ.
5: The LVD and BOR modules share a large portion of circuitry. The ∆IBOR and ∆ILVD currents are not
additive. Once one of these modules is enabled, the other may also be enabled without further penalty.

PIC18FXX8
27.1 DC Characteristics (Continued)
PIC18FXX8
No. Device
IDD Supply Current(2,3,4)
D010 PIC18LFXX8 XT osc configuration
— .7 2 mA VDD = 2.0V, +25°C, FOSC = 4 MHz
— .7 2 mA VDD = 2.0V, -40°C to +85°C, FOSC = 4 MHz
— 1.7 4 mA VDD = 4.2V, -40°C to +85°C, FOSC = 4 MHz
RC osc configuration
— 1 2.5 mA VDD = 2.0V, +25°C, FOSC = 4 MHz
— 1 2.5 mA VDD = 2.0V, -40°C to +85°C, FOSC = 4 MHz
RCIO osc configuration
— .7 2.5 mA VDD = 2.0V, +25°C, FOSC = 4 MHz
— .7 2.5 mA VDD = 2.0V, -40°C to +85°C, FOSC = 4 MHz
D010 PIC18FXX8 XT osc configuration
— 1.7 4 mA VDD = 4.2V, +25°C, FOSC = 4 MHz
RC osc configuration
— 2.5 5 mA VDD = 4.2V, +25°C, FOSC = 4 MHz
RCIO osc configuration
— 1.8 4 mA VDD = 4.2V, +25°C, FOSC = 4 MHz
D010A PIC18LFXX8 LP osc, FOSC = 32 kHz, WDT disabled
— 18 40 µA VDD = 2.0V, -40°C to +85°C
D010A PIC18FXX8 LP osc, FOSC = 32 kHz, WDT disabled
— 60 150 µA VDD = 4.2V, -40°C to +85°C
— 60 180 µA VDD = 4.2V, -40°C to +125°C
data.

PIC18FXX8
PIC18FXX8
No. Device
IDD Supply Current(2,3,4)
D010C PIC18LFXX8 EC, ECIO osc configurations
— 21 28 mA VDD = 4.2V, -40°C to +85°C
D010C PIC18FXX8 EC, ECIO osc configurations
— 21 30 mA VDD = 4.2V, -40°C to +125°C,
FOSC = 25 MHz
D013 PIC18LFXX8 HS osc configuration
— 1.3 3 mA FOSC = 6 MHz, VDD = 2.0V
— 18 28 mA FOSC = 25 MHz, VDD = 5.5V
HS + PLL osc configuration
— 28 40 mA FOSC = 10 MHz, VDD = 5.5V
D013 PIC18FXX8 HS osc configuration
— 18 28 mA FOSC = 25 MHz, VDD = 5.5V
HS + PLL osc configuration
— 28 40 mA FOSC = 10 MHz, VDD = 5.5V
D014 PIC18LFXX8 Timer1 osc configuration
— 32 65 µA FOSC = 32 kHz, VDD = 2.0V
D014 PIC18FXX8 Timer1 osc configuration
— 62 250 µA FOSC = 32 kHz, VDD = 4.2V, -40°C to +85°C
— 62 310 µA FOSC = 32 kHz, VDD = 4.2V, -40°C to +125°C
IPD Power-down Current(3)
D020 PIC18LFXX8
— 0.3 4 µA VDD = 2.0V, -40°C to +85°C
— 2 10 µA VDD = 4.2V, -40°C to +85°C
D020 PIC18FXX8 — 2 10 µA VDD = 4.2V, -40°C to +85°C
D021B — 6 40 µA VDD = 4.2V, -40°C to +125°C
data.

PIC18FXX8
PIC18FXX8
No. Device
∆IWDT Module Differential Current
D022 Watchdog Timer — 0.75 1.5 µA VDD = 2.5V, +25°C
PIC18LFXX8 — 0.8 8 µA VDD = 2.0V, -40°C to +85°C
— 7 25 µA VDD = 4.2V, -40°C to +85°C
D022 Watchdog Timer — 7 25 µA VDD = 4.2V, +25°C
PIC18FXX8 — 7 25 µA VDD = 4.2V, -40°C to +85°C
— 7 45 µA VDD = 4.2V, -40°C to +125°C
D022A ∆IBOR Brown-out Reset(5) — 38 50 µA VDD = 2.0V, +25°C
PIC18LFXX8 — 42 55 µA VDD = 2.0V, -40°C to +85°C
— 49 65 µA VDD = 4.2V, -40°C to +85°C
D022A Brown-out Reset(5) — 46 65 µA VDD = 4.2V, +25°C
— 50 75 µA VDD = 4.2V, -40°C to +125°C
D022B ∆ILVD Low Voltage Detect(5) — 36 50 µA VDD = 2.0V, +25°C
PIC18LFXX8 — 40 55 µA VDD = 2.0V, -40°C to +85°C
— 47 65 µA VDD = 4.2V, -40°C to +85°C
D022B Low Voltage Detect(5) — 44 65 µA VDD = 4.2V, +25°C
— 47 75 µA VDD = 4.2V, -40°C to +125°C
D025 ∆ITMR1 Timer1 Oscillator — 6.2 40 µA VDD = 2.0V, +25°C
PIC18LFXX8 — 6.2 45 µA VDD = 2.0V, -40°C to +85°C
— 7.5 55 µA VDD = 4.2V, -40°C to +85°C
D025 Timer1 Oscillator — 7.5 55 µA VDD = 4.2V, +25°C
PIC18FXX8 — 7.5 55 µA VDD = 4.2V, -40°C to +85°C
— 7.5 65 µA VDD = 4.2V, -40°C to +125°C
data.

PIC18FXX8
3. Module: External Clock Timing
Requirements (Table 27-6)
In Table 27-6, External Clock Timing Require-
ments, parameters 1A and 1, “External CLKI
Frequency, Oscillator Frequency”, the HS
oscillator conditions are corrected. The changes
are shown in bold text:
TABLE 27-6: EXTERNAL CLOCK TIMING REQUIREMENTS

Param No. Symbol Characteristic Min Max Units Conditions
1A FOSC (1)
External CLKI Frequency DC 40 MHz EC, ECIO, -40°C to +85°C
Oscillator Frequency(1) DC 25 MHz EC, ECIO, +85°C to +125°C
DC 4 MHz RC osc
0.1 4 MHz XT osc
4 25 MHz HS osc, -40°C to +85°C
4 25 MHz HS osc, +85°C to +125°C
4 10 MHz HS + PLL osc, -40°C to +85°C
4 6.25 MHz HS + PLL osc, +85°C to +125°C
DC 200 kHz LP osc
1 TOSC External CLKI Period(1) 25 — ns EC, ECIO, -40°C to +85°C
Oscillator Period(1) 40 — ns EC, ECIO, +85°C to +125°C
250 — ns RC osc
250 10,000 ns XT osc
40 — ns HS osc, -40°C to +85°C
40 — ns HS osc, +85°C to +125°C
100 250 ns HS + PLL osc, -40°C to +85°C
160 250 ns HS + PLL osc, +85°C to +125°C
5 200 µs LP osc
2 TCY Instruction Cycle Time(1) 100 — ns TCY = 4/FOSC, -40°C to +85°C
160 — ns TCY = 4/FOSC, +85°C to +125°C
3 TosL, External Clock in (OSC1) 30 — ns XT osc
TosH High or Low Time 2.5 — ns LP osc
10 — µs HS osc
4 TosR, External Clock in (OSC1) — 20 ns XT osc
TosF Rise or Fall Time — 50 ns LP osc
— 7.5 ns HS osc
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are
based on characterization data for that particular oscillator type under standard operating conditions with the
device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or
higher than expected current consumption. All devices are tested to operate at “Min.” values with an external
clock applied to the OSC1/CLKI pin. When an external clock input is used, the “Max.” cycle time limit is “DC”
(no clock) for all devices.

PIC18FXX8
4. Module: A/D Converter Characteristics
(Table 27-23)
In Table 27-23, A/D Converter Characteristics,
parameter A50 is corrected. The changes are
shown in bold text:
TABLE 27-23: A/D CONVERTER CHARACTERISTICS: PIC18FXX8 (INDUSTRIAL, EXTENDED)

PIC18LFXX8 (INDUSTRIAL)
Param
Symbol Characteristic Min Typ Max Units Conditions
No.
A01 NR Resolution — — 10 bit VREF = VDD ≥ 3.0V
A03 EIL Integral linearity error — — <±1 LSb VREF = VDD ≥ 3.0V
A04 EDL Differential linearity error — — <±1 LSb VREF = VDD ≥ 3.0V
A05 EFS Full scale error — — <±1 LSb VREF = VDD ≥ 3.0V
A06 EOFF Offset error — — <±1.5 LSb VREF = VDD ≥ 3.0V
(3)
A10 — Monotonicity guaranteed — VSS ≤ VAIN ≤ VREF
A20 VREF Reference voltage 0V — — V
A20A (VREFH – VREFL) 3V — — V For 10-bit resolution
A21 VREFH Reference voltage High VSS — VDD + 0.3V V
A22 VREFL Reference voltage Low VSS – 0.3V — VDD V
A25 VAIN Analog input voltage VSS – 0.3V — VREF + 0.3V V
A30 ZAIN Recommended impedance of — — 10.0 kΩ
analog voltage source
A40 IAD A/D conversion PIC18FXX8 — 180 — µA Average current
current (VDD) PIC18LFXX8 — 90 — µA consumption when
A/D is on (Note 1)
A50 IREF VREF input current (Note 2) — — 5 µA During VAIN acquisition.
Based on differential of
VHOLD to VAIN. To charge
CHOLD.
— — 150 µA During A/D conversion
cycle.
Note 1: When A/D is off, it will not consume any current other than minor leakage current. The power-down current
spec includes any such leakage from the A/D module.
VREF current is from RA2/AN2/VREF- and RA3/AN3/VREF+ pins or VDD and VSS pins, whichever is selected
as reference input.
2: VSS ≤ VAIN ≤ VREF
3: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.

PIC18FXX8
5. Module: Comparator Voltage Reference
Module
Bit 4, CVRSS, “Comparator VREF Source
Selection bit in Register 22-1: CVRCON Register
is corrected. The changes are shown in bold text:
REGISTER 22-1: CVRCON REGISTER

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0
bit 7 bit 0
bit 7 CVREN: Comparator Voltage Reference Enable bit

1 = CVREF circuit powered on
0 = CVREF circuit powered down
bit 6 CVROE: Comparator VREF Output Enable bit
1 = CVREF voltage level is also output on the RA0/AN0/CVREF pin
0 = CVREF voltage is disconnected from the RA0/AN0/CVREF pin
bit 5 CVRR: Comparator VREF Range Selection bit
1 = 0.00 CVRSRC to 0.625 CVRSRC, with CVRSRC/24 step size
0 = 0.25 CVRSRC to 0.719 CVRSRC, with CVRSRC/32 step size
bit 4 CVRSS: Comparator VREF Source Selection bit
1 = Comparator reference source CVRSRC = (VREF+) – (VREF-)
0 = Comparator reference source CVRSRC = VDD – VSS
bit 3-0 CVR<3:0>: Comparator VREF Value Selection 0 ≤ CVR3:CVR0 ≤ 15 bits
When CVRR = 1:
CVREF = (CVR3:CVR0/24) • (CVRSRC)
When CVRR = 0:
CVREF = 1/4 • (CVRSRC) + (CVR3:CVR0/32) • (CVRSRC)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

PIC18FXX8
6. Module: Low-Voltage Detect (LVD)
Characteristics
The Low-Voltage Detect (LVD) minimum and
maximum threshold voltages listed in Table 27-1 in
the device data sheet have been changed. The
changes are shown in bold text.
TABLE 27-1: LOW-VOLTAGE DETECT CHARACTERISTICS

Param
Symbol Characteristic Min Typ Max Units Conditions
No.
D420 VLVD LVD Voltage LVV = 0001 1.96 2.06 2.16 V T ≥ 25°C
LVV = 0010 2.16 2.27 2.38 V T ≥ 25°C
LVV = 0011 2.35 2.47 2.59 V T ≥ 25°C
LVV = 0100 2.43 2.58 2.69 V
LVV = 0101 2.64 2.78 2.92 V
LVV = 0110 2.75 2.89 3.03 V
LVV = 0111 2.95 3.1 3.26 V
LVV = 1000 3.24 3.41 3.58 V
LVV = 1001 3.43 3.61 3.79 V
LVV = 1010 3.53 3.72 3.91 V
LVV = 1011 3.72 3.92 4.12 V
LVV = 1100 3.92 4.13 4.34 V
LVV = 1101 4.07 4.33 4.59 V
LVV = 1110 4.36 4.64 4.92 V

PIC18FXX8
7. Module: Parallel Slave Port (PSP)
Waveforms
In Figure 10-2 and Figure 10-3 of the Device Data
Sheet, the signals PORTD, IBF, OBF, and PSPIF
are incorrectly shown as active-low. The correct
signal names are shown in the figures below.
FIGURE 10-2: PARALLEL SLAVE PORT WRITE WAVEFORMS
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
CS
WR
RD
PORTD
IBF
OBF
PSPIF
FIGURE 10-3: PARALLEL SLAVE PORT READ WAVEFORMS
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
CS
WR
RD
PORTD
IBF
OBF
PSPIF

PIC18FXX8
REVISION HISTORY
Rev A Document (07/2003)
First revision of this document, silicon issues 1 (Core –
Program Memory Space), 2 (Data EEPROM), 3 (A/D
(External Voltage Reference) and Comparator Voltage
Reference) and 4 (Core – Instruction Set) and data
sheet clarification issues 1 (A/D – VREF+ and VREF-
References) and 2 (DC Characteristics Table).
Rev B Document (03/2004)
Removed “Extended Temperature” from the title of the
Errata. Added silicon issues 5 (CAN), 6 (MSSP – All I2C
and SPI Modes) and 7 (MSSP – SPI, Slave Mode).
Added data sheet clarification issues 3 (External Clock
Timing Requirements – Table 27-6), 4 (A/D Converter
Characteristics – Table 27-23) and 5 (Comparator
Voltage Reference Module).
Rev C Document (06/2004)
Data Sheet Clarification issue 2 (DC Characteristics
Table) was updated to include parameter D005 (Brown-
out Reset Voltage) and added Data Sheet Clarification
issue 6 (Low-Voltage Detect (LVD) Characteristics).
Rev D Document (07/2004)
Clarifications/Corrections to the Data Sheet; Added
Data Sheet Clarification issue 7 (PSP Waveforms).
Module 2: DC Characteristics Table, Section 27.1
Param. No. D005, corrected trip-point values for
PIC18LFXX8.

Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
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Printed on recycled paper.
Microchip received ISO/TS-16949:2002 quality system certification for

its worldwide headquarters, design and wafer fabrication facilities in
Chandler and Tempe, Arizona and Mountain View, California in
October 2003. The Company’s quality system processes and
procedures are for its PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.

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05/28/04

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PIC18FXX8

PIC18FXX8 Rev. C0 Silicon/Data Sheet Errata

 2004 Microchip Technology Inc. DS80161D-page 1

DS80161D-page 2  2004 Microchip Technology Inc.

 2004 Microchip Technology Inc. DS80161D-page 3

DS80161D-page 4  2004 Microchip Technology Inc.

 2004 Microchip Technology Inc. DS80161D-page 5

DS80161D-page 6  2004 Microchip Technology Inc.

 2004 Microchip Technology Inc. DS80161D-page 7

DS80161D-page 8  2004 Microchip Technology Inc.

TABLE 27-6: EXTERNAL CLOCK TIMING REQUIREMENTS

 2004 Microchip Technology Inc. DS80161D-page 9

TABLE 27-23: A/D CONVERTER CHARACTERISTICS: PIC18FXX8 (INDUSTRIAL, EXTENDED)

DS80161D-page 10  2004 Microchip Technology Inc.

REGISTER 22-1: CVRCON REGISTER

bit 7 CVREN: Comparator Voltage Reference Enable bit

 2004 Microchip Technology Inc. DS80161D-page 11

TABLE 27-1: LOW-VOLTAGE DETECT CHARACTERISTICS

DS80161D-page 12  2004 Microchip Technology Inc.

FIGURE 10-2: PARALLEL SLAVE PORT WRITE WAVEFORMS

FIGURE 10-3: PARALLEL SLAVE PORT READ WAVEFORMS

 2004 Microchip Technology Inc. DS80161D-page 13

DS80161D-page 14  2004 Microchip Technology Inc.

Information contained in this publication regarding device Trademarks

Microchip received ISO/TS-16949:2002 quality system certification for

 2004 Microchip Technology Inc. DS80161D-page 15

DS80161D-page 16  2004 Microchip Technology Inc.

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