LAB 14 – GREY COUNTER TESTBENCH

NAME : SHEHRYAR ALI HAMDANI

ROLL NO : 0120-0025

TASK : Writing Testbench

For this lab, please follow the instructions available in the tutorial below to develop a self-
checking testbench for your grey counter design.
http://www.asic-world.com/verilog/art_testbench_writing1.html
These truth tables for the next state logic and output logic are given below.
What you need to submit:
• Your grey counter Verilog code.
• Your testbench Verilog code.
• Lab report.

Grey counter verilog code :

module graycounter(input wire clk,x,q2,q1,q0, output reg d2,d1,d0);

integer i ;

initial begin
d2 = 0; d1 = 0; d0 = 0 ;
end

always @(posedge clk)

begin
for (i=0;i<=8;i=i+1) begin
d2 <= x&~q1&~q0 | q2&q0 | ~x&q1&~q0 ;
d1 <= q1&~q0 | ~x&~q2&q0 | x&q2&q0 ;
d0 <= ~x&~q2&~q1 | ~x&q2&q1 | x&~q2&q1 | x&q2&~q1 ;
end
end
endmodule
Grey counter testbench :

module tb_graycounter;

reg tclk,tq2,tq1,tq0,tx ;
wire td2,td1,td0 ;
reg dut_error;
reg td2_compare, td1_compare , td0_compare;

graycounter tb_graycounter(tclk,tx,tq2,tq1,tq0,td2,td1,td0);

event reset_tx;
event terminate_sim;

initial
begin
$display ("########");
tclk = 0 ;
tq2 = 0 ;
tq1 = 0 ;
tq0 = 0 ;
tx = 0 ;
dut_error = 0;
end

always
#5 tclk = ~tclk;

initial
begin
$dumpfile ("tb_graycounter.vcd");
$dumpvars;
end

initial
@ (terminate_sim) begin
$display ("Terminating simulation");
if (dut_error == 0) begin
$display ("Simulation Result : PASSED");
end
else begin
$display ("Simulation Result : FAILED");
end
$display ("#########");
#1 $finish;
end
event reset_done;

initial
forever begin
@ (reset_tx);
@ (posedge tclk)
$display ("Applying tx");
tx = 1;
@ (posedge tclk)
tx = 0;
$display ("Came out of tx");
-> reset_done;
end

initial begin
#10 -> reset_tx;
@ (reset_done);
@ (posedge tclk);
tx = 1;
repeat (5)
begin
@ (negedge tclk);
end
tx = 0;
#5 -> terminate_sim;
end

initial begin
td2_compare = 1'b0 ; td1_compare = 1'b0 ; td0_compare = 1'b0 ;
#5
td2_compare = 1'b0 ; td1_compare = 1'b0 ; td0_compare = 1'b1 ;
#20
td2_compare = 1'b1 ; td1_compare = 1'b0 ; td0_compare = 1'b0 ;
#10
td2_compare = 1'b0 ; td1_compare = 1'b0 ; td0_compare = 1'b1 ;
#10
td2_compare = 1'b1 ; td1_compare = 1'b0 ; td0_compare = 1'b0 ;
end

always @ (negedge tclk)

if (td2_compare != td2 && td1_compare != td1 && td0_compare != td0) begin
$display ("DUT ERROR AT TIME%d",$time);
$display ("Expected value %d, Got Value %d", td2_compare,td2);
$display ("Expected value %d, Got Value %d", td1_compare,td1);
$display ("Expected value %d, Got Value %d", td0_compare,td0);
dut_error = 1;
#5 -> terminate_sim;
end

endmodule
simulation of grey counter

Explanation :

The verilog code implements a 3 bit gray counter . The grey counter changes only one bit of its
output sequence given the input sequence.

The present state is represented by q2,q1, and q0 whereas the next state is represented by d2,d1,d0 .
The input to d filp flop is X.

The test bench creates three events : reset , terminate_simulation and reset_done.
td2_compare,td1_compare and td0_compare represent the expected output while td2,td1, and td0
represent the actual output.