5 4 3 2 1

Topstar Digital technologies Co.,LTD

D D
Board name: MotherBoard Schematic 02. System block & Index
Project name: C49 03. PWR Block & Description
Version: VerA 04. Notes & Annotations
Initial Date: 2010-04-01 05. Schematic Modify and History
06. CLOCK Distribution

Topstar Confidential

C C

Hardware drawing by: Hardware check by: EMI Check by:

Power drawing by: Power check by:

Manager Sign by:

B B

A A

TOPSTAR TECHNOLOGY
Joseph
Page Name Title
Size Project Name Rev
C C49
A
Date: Friday, May 07, 2010 Sheet 1 of 59
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5 4 3 2 1
 5 4 3 2 1

Topstar Confidential
ShenZhen Topstar Industry Co.,LTD
D D
C49 SYSTEM BLOCK Ver:A

Backlight
Connector
+VDC

CK505M
Clocking
Only for PM SLG8SP585
TFT
+V3.3S
LVDS switch +V3.3S

64M*16Bit*4 DDRIII
+V1.5GDDR

Memory DDR3 SODIMM0

interface DDR3 800/1066 800/1066
Arrandule/clarsfield +V0.75S,+V1.5,+V3.3S
VGA LVDS Nvidia 989rPGA
NB11M DDR3 SODIMM1
+V5S R/G/B +VGA_CORE,
PEGX16 /eDP
+V1.05GPU +VCC_CORE,+VccGFX DDR3 800/1066 800/1066
+V1.8GDDR, +V1.5S, +V1.8S,
TMDS +V3.3GPU +V0.75S,+V1.5,+V3.3S
+V1.5GPU +V1.1S_VTT
C C
HDMI
CONN
FDI DMI*4 100MHz

PCIE 1X RTL8102E/8111D RJ45

BIOS SPI +V3.3S,+V3.3AL
8Mbit
+V3.3AL Ibex_peak
LVDS
1071 BGA SATA ODD
HDMI
+V5S
R/G/B +V3.3A,+V3.3S,+V1.5S,
+V1.05S,+V1.8S,
PCIE mini Card PCIE mini Card +V5A,+V5S
S-ATA
SIM Card 2.5" HDD SD/MMC/MS CARD
+V5S
Card Reader
USB1.1/2.0 ITE 1337
PCIE 1X +V3.3AL
LPC
AZALIA
USB1.1/2.0

Blue Tooth Camera

KB Controller/EC
USB PORT(3)
B 1.3M ODULE +V5AL
ENE 3926 B
+V3.3AL +V3.3S +V3.3AL,+V3.3S,+V5AL L

TCM R
(Reserve)

AZALIA MiC In
ALC662
+V5S,+V3.3S .. Line Out

LED/TouchPAD/Button/ LID Switch

Switch Board
DAUGHTER BOARD DAUGHTER BOARD

KB Matrix

A A

TOPSTAR TECHNOLOGY
Joseph
Page Name Sys block
Size Project Name Rev
C C49
A
Date: Friday, May 07, 2010 Sheet 2 of 59
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5 4 3 2 1
 5 4 3 2 1

C46 POWER BLOCK Ver:A

Platform
Logic
VCC_SENCE
VSS_SENCE

VR_ON
D D

IMON
VR_TT#
VIN
Vcc_core
注意: V_5 IMVP-6.5 VID[6...0]
PSI#
虚线表示电源电压信号。 V_3
DPRSLPVR

CLK_ENABLE#

IMVP6_PWRGD
Charge Battery
ISL6251 51A
+VCC_CORE
PSI# PROCHOT#

PCH CPU_PWRGD CPU-M

VCC_CORE
Adapter Power +VDC ISL62882
65/90W Switch 5A
C C
+V1.8S MOSFET
+V1.8GPU
CLK
KIA1117
CHIP

Always_On
DDR Power
Power
TPS51218
TPS51125
ISL62872 ISL62881 TPS51218 TPS51218 +APL5331 +V5S
+V3.3S

+V3.3AL +V1.5
+V1.05S +V1.1S_VTT +V0.75S
8A 18A +V5AL
5A/5A 12A/2.5A MOSFET
MOSFET MOSFET MOSFET
+VGA_CORE +VGFX +V1.5S
10A 14A +V1.5GPU 3A
+V1.05GPU +V3.3GPU
3A
2.5A <0.5A
B
System Power B
+V_S

A A

TOPSTAR TECHNOLOG
Joseph
Page Name PWR Block
Size Project Name Rev
C C49 A
Date: Friday, May 07, 2010 Sheet 3 of 59
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR

5 4 3 2 1
 5 4 3 2 1

Voltage Rails
+VDC Primary DC system power supply(9V-19V)
I2C SMB Address
+VCC_CORE Core voltage for processor
D Device Address Hex Bus Master D

+V1.1S_VTT 1.1V for CPU

Clock Generator 1101 001x D2 SMB_PCH PCH
SO-DIMM0 1010 000x A0 SMB_PCH PCH
+V1.05S 1.05V for PCH core
SO-DIMM1 1010 010x A4 SMB_PCH PCH
+V0.75S 0.75V DDR3 Termination voltage
NEW CARD Variable Variable SMB_PCH PCH
+V1.5 1.5V power rail for DDR3
PCIE Mini CARD Variable Variable SMB_PCH PCH
+V3.3AL 3.3V always on power rail
PCH Variable Variable SMB1_PCH ENE3926
+V3.3S 3.3V main power rail
+V5AL 5V for USB Device Smart Battery 0001 011x 16 I2C ENE3926
+V5S 5V main power rail
Touch sensor IC 1000 110x 8C SMB1_PCH ENE3926
+VGA_CORE 0.8--1.03V for GPU NB8M core voltage

+V1.5S 1.5S for PCIE Device

+V1.8S 1.8V for display votage

+V3.3GPU 3.3V for external GPU

+V1.05GPU 1.05V for external GPU

+V1.8GPU 1.8V for external GPU

C C

+V1.5GPU 1.5V for external GPU

Power States/AC mode

Board stack up description Signal SLP_S3# SLP_S4# SLP_S5# +V*AL +V* +V*S Clock

S0(Full On) HIGH HIGH HIGH ON ON ON ON

PCB Layers
S3(STM) LOW HIGH HIGH ON ON OFF OFF
TOP
S4(STD) LOW LOW HIGH ON OFF OFF OFF
GND
S5(SoftOff) LOW LOW LOW ON OFF OFF OFF
IN1

IN2 Trace Impedence:50ohm +/-15%(Default)

VCC

IN3

B GND B

Bottom

Wake up Events
USB Table
USB Port# Function Description LID switch from EC
Power switch from EC
0 Express Card

1 minicard1

2 reserved

3 camera

4 USB port1

5 Bluetooth

6 Reserved
A A

7 Reserved

8 CARD Reader TOPSTAR TECHNOLOG

Joseph
9 minicard2 Page Name Notes
Size Project Name Rev
10 USB port2 C C49 A
Date: Friday, May 07, 2010 Sheet 4 of 59
11 USB port3 PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5 4 3 2 1
 5 4 3 2 1

C48 VerB to VerC change

1:GPURST#使用与门控制（I GU1 ,NI GR1），由PLTRST#与EC_GPURST#共同控制，正常的开关机的时候EC_GPURST#始终为高电平，
即GPURST#与PLATRST#同步，由PLTRST#控制，做显卡切换的时候由EC_GPURST#控制GPURST#，
这样做的原因就是如果始终由EC_GPURST#通过侦测PLTRST#来控制GPURST#，
因为在热启动的过程中PLTRST#被拉下来的时间基本上就在5ms左右，而EC的扫描周期就是5ms,
有可能会抓不到PLTRST#一个变化的过程而保持一直为高，会造成显卡驱动的丢失等异常现象。
D D

2：死锁电话设计变更，电路改变描述如下：
NI Q31,PZ8,change PR187 from 100 ohm to 2K ohm,change PR24 from 51k to 15K
变更原因如下：Q31是显卡GPU_OVT#控制死锁电路的通道，因为系统下要做显卡切换，当从独显切到集显的时候，
所有GPU电都会掉下来，所以GPU_OVT#也会掉下来，会导致异常死锁，所以不能这样控制，现在GPU温度侦测是
通过BIOS读取然后发送给EC，由EC控制。PR187换成2K,PR24换成15K的原因是因为之前的组合不能死锁，
就算有死锁信号发出来，因为51K和100ohm分压，分出来的电压不能维持死锁电路，同时去掉PZ8是因为之前
发现稳压管随着温度变化漏电流会增大，可能会导致异常死锁，同时因为3.3AL芯片内部有过压保护功能，
故去掉PZ8不会对线路有影响。

3：TP_CON2由之前的6Pin换成7pin,变更的原因是主板要兼容C49，而C49上需要两个EC的GPIO控制两个开关，
之前的线路上只有一个EC GPIO，故需要增加1pin。

C 4：PWRLED#信号同时控制POWER1与PWRLED1，之前线路设计PWRLED#只控制POWER1,而PWRLED1是使用其他EC的GPIO控制， C

导致这两个PWR灯不能同步，不满足设计要求。

5：Audio Jack 物料变更，由之前的SMD料切换到DIP料，相印的元件Symbol也有变更。同时Audio小板上的

SPK CONN物料因为成本因素，也有变更为普通使用的CONN，与RTC CONN一致，不涉及线路图变更。

6：USB conn物料变更，因为之前的USB conn是反的，会给用户使用造成困扰，线路图变更参考线路图

7：网卡CO-lay 千兆Option for C49,具体线路图变更请参考线路图。

C48 VerC to C49 VerA change

1：PROCHOT#由单相变双相，EC作为控制信号输出
B
2：PCH GPIO33连接到EC pin 104(EC输出)，作为EC_ME_LOCK#控制信号 B
3：MCH_HDMI_HPD直接
4：连接显卡的SMBUS与EC的SMBUS，使EC直接读取显卡温度
5：删除蓝牙主板上的CONN，将蓝牙信号连接到LCD CONN
6：GPU_OVT#连接到EC的Pin88(EC 输入信号)
7：ESATA USB CONN变更为单个的USB CONN
8：删除E-CARD Function
9：调整RSMRST#与+V3.3AL掉电时序，ALW_PWROK 从Pin110变更到Pin95(EC输入&中断pin)
10：调整C49_switch2到110pin(EC输入)
11：PWR_LAN与主板连接线由30pin电子线变更为1个8pin的电子线（For 电源）与一个20pin FFC conn(For 网卡)
12：去掉+V1.05S线路，共用+V1.1S_VTT，中间使用Open 点与电阻连接
13：更改死锁电路设计
TOPSTAR TECHNOLOG
A Joseph A

Page Name history

Size Project Name Rev
Custom C49 A
Date: Friday, May 07, 2010 Sheet 5 of 59
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5 4 3 2 1
 5 4 3 2 1

+V3.3S {8,14,15,16,22,23,24,25,26,27,28,29,30,32,33,34,35,36,37,38,40,41,42,43,47,48,49,50,51,53,54,55,56}

+V3.3AL {22,23,24,25,27,28,30,32,34,35,36,37,41,42,43,44,45,46,47,48,49,50,51,54,56}

+V3.3S FB1 2 1 100ohm@100MHz,3A +V3.3S_CK_VDD

FB0805
D D
C1 C2 C3 C4 C5

10UF/6.3V,X5R 0.1UF/25V,Y5V 0.1UF/25V,Y5V

0.1UF/25V,Y5V 0.1UF/25V,Y5V
C0805 C0402 C0402 C0402 C0402
Layout Note:
Cap Close to CK505 PWR pin

+V3.3S

R573
10K U1
R0402 SMBUS ADD:1101 001X
1 31 R955 0 R0402
VDD_DOT SMB_DATA SMB_DATA_S {14,15,24,37}
CPU_STOP# 5 32 R956 0 R0402
VDD_27 SMB_CLK SMB_CLK_S {14,15,24,37}
17 VDD_SRC
+V3.3S_CK_VDD 29 16 CPU_STOP#
VDD_REF CPU_STOP#
24 23 BCLK R1 0 R0402
VDD_CPU CPU0 CLK_BUF_BCLK_P {24}
18 22 BCLK# R2 0 R0402
VDD_CPU_IO CPU0# CLK_BUF_BCLK_N {24}
+VDDIO_CLK 15 VDD_SRC_IO Integrated resistors on differentail clk
G1 GND1 CPU1 20
G2 GND2 CPU1# 19
G3 GND3
No more than 500 mil G4 3 DOT96 R3 0 R0402
GND4 DOT96 CLK_BUF_DOT96_P {24}
C11 27pF/50V,NPO XTAL_IN 28 4 DOT96# R4 0 R0402
XTAL_IN DOT96# CLK_BUF_DOT96_N {24}
C0402

1
Y1 XTAL_OUT 27 10 R5 0 R0402
XTAL_OUT SRC0/SATA CLK_BUF_SATA_P {24}
C +V3.3S FB2 1 2 100ohm@100MHz,3A +VDDIO_CLK 14.31818MHz G5 11 R6 0 R0402 C
GND5 SRC0#/SATA CLK_BUF_SATA_N {24}
XS2_3D3
FB0805 C6 C7 C8 C9 C10 13 R7 0 R0402
SRC1 CLK_BUF_EXP_P {24}
14 R8 0 R0402
SRC1# CLK_BUF_EXP_N {24}

2
2 VSS_DOT
10UF/6.3V,X5R 0.1UF/25V,Y5V 0.1UF/25V,Y5V C12 27pF/50V,NPO 8 6
VSS_27 27M_NSS 27M_nonSSC {20}
10UF/6.3V,X5R 0.1UF/25V,Y5V C0402 9 7
C0805 C0805 C0402 C0402 C0402 VSS_SATA 27M_SS 27M_SSC {20}
12 VSS_SRC
21 30 BCLK_FS R9 33 R0402
VSS_CPU REF/FS CLK_BUF_REF14 {24}
26 25 CLK_PWRGD
VSS_REF CK_PWRGD/PWRDWN#
CK505QFN32

+V3.3S

Frequence Select
High:100Mhz
Low:133Mhz(Default) R10
10K
CLK_BUF_REF14 C13 10PF/50V,NPO
ns
C0402

R0402
B B
ns

BCLK_FS

R895 0 ns
+V3.3S
+V3.3AL

R896 C534
10K 0.1UF/10V,X7R
5

R897 R0402
10K 1 VCC
R0402 4 CLK_PWRGD
ns 2
GND
3

SOT23_5
PQ85 SN74AHC1G08DBV
3

2N7002 U30
R898 1K 1 SOT23
{53} CK505_CLK_EN#
R0402
A C536 A
2

C535
C0402
C0402 0.1UF/25V,Y5V
0.1UF/25V,Y5V
ns TOPSTAR TECHNOLOG
Joseph
Page Name CK505M
Size Project Name Rev
C C49 A
Date: Friday, May 07, 2010 Sheet 6 of 59
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5 4 3 2 1
 5 4 3 2 1

PEG_IRCOMP_R R11 49.9,1%

U2A R0402
PEG_ICOMPI B26
A26 R12 750 OHM
D DMI_TXN0 PEG_ICOMPO R0402 D
{25} DMI_TXN0 A24 DMI_RX#[0] PEG_RCOMPO B27
DMI_TXN1 C23 A25 EXP_RBIAS
{25} DMI_TXN1 DMI_RX#[1] PEG_RBIAS PEG_TXN[15..0] {17}
DMI_TXN2 B22
{25} DMI_TXN2 DMI_RX#[2]
DMI_TXN3 A21 K35 PEG_TXN0
{25} DMI_TXN3 DMI_RX#[3] PEG_RX#[0]
J34 PEG_TXN1
DMI_TXP0 PEG_RX#[1] PEG_TXN2
{25} DMI_TXP0 B24 DMI_RX[0] PEG_RX#[2] J33
DMI_TXP1 D23 G35 PEG_TXN3
{25} DMI_TXP1 DMI_RX[1] PEG_RX#[3]
DMI_TXP2 PEG_TXN4

DMI
{25} DMI_TXP2 B23 DMI_RX[2] PEG_RX#[4] G32
DMI_TXP3 A22 F34 PEG_TXN5
{25} DMI_TXP3 DMI_RX[3] PEG_RX#[5]
F31 PEG_TXN6
DMI_RXN0 PEG_RX#[6] PEG_TXN7
{25} DMI_RXN0 D24 DMI_TX#[0] PEG_RX#[7] D35
DMI_RXN1 G24 E33 PEG_TXN8
{25} DMI_RXN1 DMI_TX#[1] PEG_RX#[8]
DMI_RXN2 F23 C33 PEG_TXN9
{25} DMI_RXN2 DMI_TX#[2] PEG_RX#[9]
DMI_RXN3 H23 D32 PEG_TXN10
{25} DMI_RXN3 DMI_TX#[3] PEG_RX#[10]
B32 PEG_TXN11
DMI_RXP0 PEG_RX#[11] PEG_TXN12
{25} DMI_RXP0 D25 DMI_TX[0] PEG_RX#[12] C31
DMI_RXP1 F24 B28 PEG_TXN13
{25} DMI_RXP1 DMI_TX[1] PEG_RX#[13]
DMI_RXP2 E23 B30 PEG_TXN14
{25} DMI_RXP2 DMI_TX[2] PEG_RX#[14]
DMI_RXP3 G23 A31 PEG_TXN15
{25} DMI_RXP3 DMI_TX[3] PEG_RX#[15] PEG_TXP[15..0] {17}
J35 PEG_TXP0
PEG_RX[0] PEG_TXP1
PEG_RX[1] H34
H33 PEG_TXP2
{25} FDI_TXN[7:0] PEG_RX[2]
FDI_TXN0 E22 F35 PEG_TXP3
C
FDI_TXN1 FDI_TX#[0] PEG_RX[3] PEG_TXP4
C
D21 FDI_TX#[1] PEG_RX[4] G33
FDI_TXN2 D19 E34 PEG_TXP5
FDI_TXN3 FDI_TX#[2] PEG_RX[5] PEG_TXP6
D18 FDI_TX#[3] PEG_RX[6] F32
FDI_TXN4 G21 D34 PEG_TXP7
FDI_TXN5 FDI_TX#[4] PEG_RX[7] PEG_TXP8
E19 F33

PCI EXPRESS -- GRAPHICS

FDI_TXN6 FDI_TX#[5] PEG_RX[8] PEG_TXP9
F21 FDI_TX#[6] PEG_RX[9] B33
FDI_TXN7

Intel(R) FDI
G18 D31 PEG_TXP10
FDI_TX#[7] PEG_RX[10] PEG_TXP11
PEG_RX[11] A32
C30 PEG_TXP12
{25} FDI_TXP[7:0] PEG_RX[12]
FDI_TXP0 D22 A28 PEG_TXP13
FDI_TXP1 FDI_TX[0] PEG_RX[13] PEG_TXP14
C21 FDI_TX[1] PEG_RX[14] B29
FDI_TXP2 D20 A30 PEG_TXP15
FDI_TX[2] PEG_RX[15] PEG_RXN[15..0] {17}
FDI_TXP3 C18
FDI_TXP4 FDI_TX[3]
G22 FDI_TX[4] PEG_TX#[0] L33 0.1UF/10V,X7R GC217 PEG_RXN0
FDI_TXP5 E20 M35 0.1UF/10V,X7R GC218 PEG_RXN1
FDI_TXP6 FDI_TX[5] PEG_TX#[1]
F20 FDI_TX[6] PEG_TX#[2] M330.1UF/10V,X7R GC219 PEG_RXN2
FDI_TXP7 G19 FDI_TX[7] PEG_TX#[3] M30 0.1UF/10V,X7R GC220 PM PEG_RXN3
PEG_TX#[4] L310.1UF/10V,X7R GC221 PM
PEG_RXN4
{25} FDI_FSYNC0 F17 FDI_FSYNC[0] PEG_TX#[5] K32 0.1UF/10V,X7RGC223 PM PEG_RXN5
{25} FDI_FSYNC1 E17 FDI_FSYNC[1] PEG_TX#[6] M29 0.1UF/10V,X7RGC222 PM
PEG_RXN6
PEG_TX#[7] J31 0.1UF/10V,X7RGC224 PM PEG_RXN7
{25} FDI_INT C17 FDI_INT PEG_TX#[8] K290.1UF/10V,X7R GC225 PM
PEG_RXN8
H30 0.1UF/10V,X7R GC227 PEG_RXN9
PEG_TX#[9] PM
B {25} FDI_LSYNC0 F18 FDI_LSYNC[0] PEG_TX#[10] H290.1UF/10V,X7R GC226 PM
PEG_RXN10 B
{25} FDI_LSYNC1 D17 FDI_LSYNC[1] PEG_TX#[11] F290.1UF/10V,X7RGC228 PM
PEG_RXN11
E280.1UF/10V,X7R GC229 PEG_RXN12
PEG_TX#[12] PM
PEG_TX#[13] D29 0.1UF/10V,X7RGC231 PM PEG_RXN13
PEG_TX#[14] D27 0.1UF/10V,X7R GC230 PM
PEG_RXN14
PEG_TX#[15] C26 0.1UF/10V,X7R GC232 PM PEG_RXN15
PEG_RXP[15..0] {17}
PM
PEG_TX[0] L34 GC237 0.1UF/10V,X7R PM PEG_RXP0
M34 GC240 0.1UF/10V,X7R PEG_RXP1
PEG_TX[1] PM
PEG_TX[2] M32 GC242 0.1UF/10V,X7R PEG_RXP2
L30 GC241 0.1UF/10V,X7R PEG_RXP3
PEG_TX[3] PM
PEG_TX[4] M31 GC238 0.1UF/10V,X7R PEG_RXP4
K31 GC243 0.1UF/10V,X7R PM PEG_RXP5
PEG_TX[5] PM
M28 GC239 0.1UF/10V,X7R PEG_RXP6
PEG_TX[6]
H31 GC244 0.1UF/10V,X7R PM PEG_RXP7
PEG_TX[7] PM
PEG_TX[8] K28 GC2450.1UF/10V,X7R PEG_RXP8
G30 GC247 0.1UF/10V,X7R PM PEG_RXP9
PEG_TX[9] PM
PEG_TX[10] G29 GC2460.1UF/10V,X7R PEG_RXP10
F28 GC2480.1UF/10V,X7R PM PEG_RXP11
PEG_TX[11] PM
E27 GC235 0.1UF/10V,X7R PEG_RXP12
PEG_TX[12]
D28 GC233 0.1UF/10V,X7R PM PEG_RXP13
PEG_TX[13] GC236 0.1UF/10V,X7R PM PEG_RXP14
PEG_TX[14] C27
C25 GC2340.1UF/10V,X7R PM PEG_RXP15 TOPSTAR TECHNOLOGY
PEG_TX[15] PM
A
PM Joseph A
PM
PM Page Name N11M PCIE&PWR&GND
IC,AUB_CFD_rPGA,R1P0
Size Project Name Rev
B C49
A
Date: Friday, May 07, 2010 Sheet 7 of 59
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5 4 3 2 1
 5 4 3 2 1

+V1.1S_VTT {10,11,48,49,53}

+V3.3S {6,14,15,16,22,23,24,25,26,27,28,29,30,32,33,34,35,36,37,38,40,41,42,43,47,48,49,50,51,53,54,55,56}

+V1.5 {11,14,15,47,54,55,56}

+V1.1S_VTT

Voltage Level?
R59
D D
+V1.1S_VTT 1K +V3.3S
R0402
Layout Note: ns
Place close to CPU S_Top
R51
U2B R15 10K
H_COMP3 AT23 10K R0402
COMP3

1
A16 BCLK_CPU_P_R R13 0 R0402 R0402 ns
BCLK BCLK_CPU_P {28} S_Top S_Top
H_COMP2 BCLK_CPU_N_R

MISC
AT24 B16 R14 0 R0402 Q27
COMP2 BCLK# S_Bot BCLK_CPU_N {28}
PM_EXT_TS#0 3 2 ns
S_Bot DIM_EXTTS#0 {14}
H_COMP1 BCLK_ITP_P SOT23 MMBT3904-F

CLOCKS
G16 COMP1 BCLK_ITP AR30 T24 ns
AT30 BCLK_ITP_N T36 ns
H_COMP0 BCLK_ITP#
AT26 COMP0 CLK_EXP_P_R R17 0 R0402 S_Top
PEG_CLK E16 CLK_EXP_P {24}
+V1.1S_VTT D16 CLK_EXP_N_R R18 0 R0402 S_Bot +V1.1S_VTT
PEG_CLK# S_Bot CLK_EXP_N {24}
AH24 SKTOCC# CLK_DP_P_R R19 S_BotR0402
0
S_Bot
ns +V3.3S
Voltage Level?
DPLL_REF_SSCLK A18
A17 CLK_DP_N_R R20 0 R0402 ns
R21 49.9,1% R0402 H_CATERR# AK14 DPLL_REF_SSCLK# R154
CATERR# S_Bot

THERMAL
+V1.1S_VTT 1K
S_Top S_Bot R0402
F6 ns
SM_DRAMRST# DDR3_DRAMRST# {14,15} S_Top
R23 0 R0402 H_PECI_R AT15 R24
{28} H_PECI PECI
+V1.1S_VTT AL1 SM_RCOMP_0 R22 10K
S_Top SM_RCOMP[0] SM_RCOMP_1 10K R0402
SM_RCOMP[1] AM1

1
AN1 SM_RCOMP_2 R0402 ns
R25 68 R0402 ns VR_PROCHOT# SM_RCOMP[2] S_Top Q28 S_Top
AN26 PROCHOT#
AN15 PM_EXT_TS#0 PM_EXT_TS#1 3 2 ns
PM_EXT_TS#[0] DIM_EXTTS#1 {15}

DDR3
MISC
AP15 PM_EXT_TS#1 SOT23 MMBT3904-F
S_Top PM_EXT_TS#[1]

{28,34} THERMTRIP# AK15 THERMTRIP# S_Top

+V1.1S_VTT PRDY# AT28

XDP_REQ
+V1.1S_VTT 目前我们用的内存端没有做过温的功能。
PREQ# AP27

AN28 TCK
R26 68 R0402 ns H_CPURST#_R TCK TMS TDO R566 49.9,1% R0402
C AP26 RESET_OBS# TMS AP28 C
TRST#

PWR MANAGEMENT
AT27 ns
TRST#

JTAG & BPM

S_Top
R27 0 R0402 H_PM_SYNC_R TDI S_Bot
{25} H_PM_SYNC AL15 PM_SYNC TDI AT29
AR27 TDO TMS R253 49.9,1% R0402
+V1.1S_VTT S_Top TDO TDI_M R562 ns
TDI_M AR29
R487 0 R0402 VCCPWRGOOD_1_R AN14 AP29 TDO_M 49.9,1%
VCCPWRGOOD_1 TDO_M R0402 TCK R267 S_Bot
49.9,1% R0402
S_Top AN25 S_Bot ns
DBR# T48 ns
R488 0 R0402 VCCPWRGD_0_R AN27
{28} VCCPWRGD_0 VCCPWRGOOD_0 S_Bot +V3.3S
R413 S_Top AJ22 TDI R296 49.9,1% R0402
BPM#[0] T20 ns
1K,1% PM_DRAM_PWRGD AK13 AK22 T42 ns S_Top ns
{25} PM_DRAM_PWRGD SM_DRAMPWROK BPM#[1]
R0402 BPM#[2] AK24 T43 ns
ns XDP_REQ R325 S_Bot
49.9,1% R0402 R28
BPM#[3] AJ24 T44 ns
S_Top CPU_VTT_PWG AM15 AJ25 ns S_Top ns 10K
VTTPWRGOOD BPM#[4] T46
AH22 T45 ns S_Top R0402
BPM#[5] S_Top S_Bot S_Top
BPM#[6] AK23 T47 ns
H_PWRGD_XDP_R AM26 AH23 T37 ns S_Top
TAPPWRGOOD BPM#[7] EC_PROCHOT# {42}
S_Top
TDI_M S_Top +V1.1S_VTT
R29 1.5K,1% R0402 PLT_RST#_R AL14 S_Top R30 Q2 R32
{17,27,34,35,37,41,42} BUF_PLT_RST# RSTIN# R265
S_Top 1K MMBT3904-F 1K

2
S_Top 0 ns R0402 Q1 SOT23 R0402
1 MMBT3904-F R31 S_Top
1 S_Top
R0402 +V1.1S_VTT S_Top +V1.1S_VTT
IC,AUB_CFD_rPGA,R1P0 TDO_M ns SOT23 1K
R33 S_Bot S_Top ns R0402

3
750 OHM S_Top S_Top
R0402 VR_PROCHOT#
S_Top VR_PROCHOT# {53}

Processor Compensation DDR3 Compensation Signals

Signals SM_RCOMP_2

H_COMP1 H_COMP3 SM_RCOMP_1

H_COMP0 H_COMP2 SM_RCOMP_0

B B

R34 R35 R36 R37 R38 R39 R40

49.9,1% 49.9,1% 20,1% 20,1% 100,1% 24.9,1% 130,1%
R0402 R0402 r0402 r0402 R0402 R0402 R0402
S_Top S_Top S_Bot S_Bot S_Bot S_Bot S_Bot

+V1.5

R215
1.21K,1%
S_Top

{42} CPU_VTT_PWG
PM_DRAM_PWRGD

A A
R899
R234 750 OHM
3.3K S_Bot
S_Top
TOPSTAR TECHNOLOGY
Joseph
Page Name N11M PCIE&PWR&GND
Size Project Name Rev
C C49
A
Date: Friday, May 07, 2010 Sheet 8 of 59
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5 4 3 2 1
 5 4 3 2 1

U2D

U2C

SB_CK[0] W8 M_CLK_DDR2 {15}

D {15} MB_DATA[63:0] SB_CK#[0] W9 M_CLK_DDR#2 {15} D
MB_DATA0 B5 M3
SB_DQ[0] SB_CKE[0] M_CKE2 {15}
AA6 MB_DATA1 A5
SA_CK[0] M_CLK_DDR0 {14} SB_DQ[1]
AA7 MB_DATA2 C3
SA_CK#[0] M_CLK_DDR#0 {14} MB_DATA3 SB_DQ[2]
SA_CKE[0] P7 M_CKE0 {14} B3 SB_DQ[3] SB_CK[1] V7 M_CLK_DDR3 {15}
{14} MA_DATA[63:0] MA_DATA0 A10 MB_DATA4 E4 V6
MA_DATA1 SA_DQ[0] MB_DATA5 SB_DQ[4] SB_CK#[1] M_CLK_DDR#3 {15}
C10 SA_DQ[1] A6 SB_DQ[5] SB_CKE[1] M2 M_CKE3 {15}
MA_DATA2 C7 MB_DATA6 A4
MA_DATA3 SA_DQ[2] MB_DATA7 SB_DQ[6]
A7 SA_DQ[3] SA_CK[1] Y6 M_CLK_DDR1 {14} C4 SB_DQ[7]
MA_DATA4 B10 Y5 MB_DATA8 D1
MA_DATA5 SA_DQ[4] SA_CK#[1] M_CLK_DDR#1 {14} MB_DATA9 SB_DQ[8]
D10 SA_DQ[5] SA_CKE[1] P6 M_CKE1 {14} D2 SB_DQ[9]
MA_DATA6 E10 MB_DATA10 F2 AB8
SA_DQ[6] SB_DQ[10] SB_CS#[0] M_CS#2 {15}
MA_DATA7 A8 MB_DATA11 F1 AD6
SA_DQ[7] SB_DQ[11] SB_CS#[1] M_CS#3 {15}
MA_DATA8 D8 MB_DATA12 C2
MA_DATA9 SA_DQ[8] MB_DATA13 SB_DQ[12]
F10 SA_DQ[9] SA_CS#[0] AE2 M_CS#0 {14} F5 SB_DQ[13]
MA_DATA10 E6 AE8 MB_DATA14 F3
SA_DQ[10] SA_CS#[1] M_CS#1 {14} SB_DQ[14]
MA_DATA11 F7 MB_DATA15 G4 AC7
SA_DQ[11] SB_DQ[15] SB_ODT[0] M_ODT2 {15}
MA_DATA12 E9 MB_DATA16 H6 AD1
SA_DQ[12] SB_DQ[16] SB_ODT[1] M_ODT3 {15}
MA_DATA13 B7 MB_DATA17 G2
MA_DATA14 SA_DQ[13] MB_DATA18 SB_DQ[17]
E7 SA_DQ[14] SA_ODT[0] AD8 M_ODT0 {14} J6 SB_DQ[18]
MA_DATA15 C6 AF9 MB_DATA19 J3
SA_DQ[15] SA_ODT[1] M_ODT1 {14} SB_DQ[19]
MA_DATA16 H10 MB_DATA20 G1
SA_DQ[16] SB_DQ[20] MB_DM[7:0] {15}
MA_DATA17 G8 MB_DATA21 G5 D4 MB_DM0
MA_DATA18 SA_DQ[17] MB_DATA22 SB_DQ[21] SB_DM[0] MB_DM1
K7 SA_DQ[18] J2 SB_DQ[22] SB_DM[1] E1
MA_DATA19 J8 MB_DATA23 J1 H3 MB_DM2
MA_DATA20 SA_DQ[19] MB_DATA24 SB_DQ[23] SB_DM[2] MB_DM3
G7 SA_DQ[20] J5 SB_DQ[24] SB_DM[3] K1
MA_DATA21 G10 MB_DATA25 K2 AH1 MB_DM4
SA_DQ[21] MA_DM[7:0] {14} SB_DQ[25] SB_DM[4]
MA_DATA22 J7 B9 MA_DM0 MB_DATA26 L3 AL2 MB_DM5
MA_DATA23 SA_DQ[22] SA_DM[0] MA_DM1 MB_DATA27 SB_DQ[26] SB_DM[5] MB_DM6
J10 SA_DQ[23] SA_DM[1] D7 M1 SB_DQ[27] SB_DM[6] AR4
MA_DATA24 L7 H7 MA_DM2 MB_DATA28 K5 AT8 MB_DM7
MA_DATA25 SA_DQ[24] SA_DM[2] MA_DM3 MB_DATA29 SB_DQ[28] SB_DM[7]
M6 SA_DQ[25] SA_DM[3] M7 K4 SB_DQ[29]
MA_DATA26 M8 AG6 MA_DM4 MB_DATA30 M4
MA_DATA27 SA_DQ[26] SA_DM[4] MA_DM5 MB_DATA31 SB_DQ[30]
L9 SA_DQ[27] SA_DM[5] AM7 N5 SB_DQ[31]
MA_DATA28 L6 AN10 MA_DM6 MB_DATA32 AF3
MA_DATA29 SA_DQ[28] SA_DM[6] MA_DM7 MB_DATA33 SB_DQ[32]
K8 SA_DQ[29] SA_DM[7] AN13 AG1 SB_DQ[33] MB_DQS#[7:0] {15}
MA_DATA30 N8 MB_DATA34 AJ3 D5 MB_DQS#0
MA_DATA31 SA_DQ[30] MB_DATA35 SB_DQ[34] SB_DQS#[0] MB_DQS#1
P9 SA_DQ[31] AK1 SB_DQ[35] SB_DQS#[1] F4
MA_DATA32 AH5 MB_DATA36 AG4 J4 MB_DQS#2
MA_DATA33 SA_DQ[32] MB_DATA37 SB_DQ[36] SB_DQS#[2] MB_DQS#3
C AF5 SA_DQ[33] MA_DQS#[7:0] {14} AG3 SB_DQ[37] SB_DQS#[3] L4 C
MA_DATA34 AK6 C9 MA_DQS#0 MB_DATA38 AJ4 AH2 MB_DQS#4
SA_DQ[34] SA_DQS#[0] SB_DQ[38] SB_DQS#[4]
DDR SYSTEM MEMORY A

DDR SYSTEM MEMORY - B

MA_DATA35 AK7 F8 MA_DQS#1 MB_DATA39 AH4 AL4 MB_DQS#5
MA_DATA36 SA_DQ[35] SA_DQS#[1] MA_DQS#2 MB_DATA40 SB_DQ[39] SB_DQS#[5] MB_DQS#6
AF6 SA_DQ[36] SA_DQS#[2] J9 AK3 SB_DQ[40] SB_DQS#[6] AR5
MA_DATA37 AG5 N9 MA_DQS#3 MB_DATA41 AK4 AR8 MB_DQS#7
MA_DATA38 SA_DQ[37] SA_DQS#[3] MA_DQS#4 MB_DATA42 SB_DQ[41] SB_DQS#[7]
AJ7 SA_DQ[38] SA_DQS#[4] AH7 AM6 SB_DQ[42]
MA_DATA39 AJ6 AK9 MA_DQS#5 MB_DATA43 AN2
MA_DATA40 SA_DQ[39] SA_DQS#[5] MA_DQS#6 MB_DATA44 SB_DQ[43]
AJ10 SA_DQ[40] SA_DQS#[6] AP11 AK5 SB_DQ[44]
MA_DATA41 AJ9 AT13 MA_DQS#7 MB_DATA45 AK2
MA_DATA42 SA_DQ[41] SA_DQS#[7] MB_DATA46 SB_DQ[45]
AL10 SA_DQ[42] AM4 SB_DQ[46]
MA_DATA43 AK12 MB_DATA47 AM3
SA_DQ[43] SB_DQ[47] MB_DQS[7:0] {15}
MA_DATA44 AK8 MB_DATA48 AP3 C5 MB_DQS0
MA_DATA45 SA_DQ[44] MB_DATA49 SB_DQ[48] SB_DQS[0] MB_DQS1
AL7 SA_DQ[45] MA_DQS[7:0] {14} AN5 SB_DQ[49] SB_DQS[1] E3
MA_DATA46 AK11 C8 MA_DQS0 MB_DATA50 AT4 H4 MB_DQS2
MA_DATA47 SA_DQ[46] SA_DQS[0] MA_DQS1 MB_DATA51 SB_DQ[50] SB_DQS[2] MB_DQS3
AL8 SA_DQ[47] SA_DQS[1] F9 AN6 SB_DQ[51] SB_DQS[3] M5
MA_DATA48 AN8 H9 MA_DQS2 MB_DATA52 AN4 AG2 MB_DQS4
MA_DATA49 SA_DQ[48] SA_DQS[2] MA_DQS3 MB_DATA53 SB_DQ[52] SB_DQS[4] MB_DQS5
AM10 SA_DQ[49] SA_DQS[3] M9 AN3 SB_DQ[53] SB_DQS[5] AL5
MA_DATA50 AR11 AH8 MA_DQS4 MB_DATA54 AT5 AP5 MB_DQS6
MA_DATA51 SA_DQ[50] SA_DQS[4] MA_DQS5 MB_DATA55 SB_DQ[54] SB_DQS[6] MB_DQS7
AL11 SA_DQ[51] SA_DQS[5] AK10 AT6 SB_DQ[55] SB_DQS[7] AR7
MA_DATA52 AM9 AN11 MA_DQS6 MB_DATA56 AN7
MA_DATA53 SA_DQ[52] SA_DQS[6] MA_DQS7 MB_DATA57 SB_DQ[56]
AN9 SA_DQ[53] SA_DQS[7] AR13 AP6 SB_DQ[57]
MA_DATA54 AT11 MB_DATA58 AP8
MA_DATA55 SA_DQ[54] MB_DATA59 SB_DQ[58]
AP12 SA_DQ[55] AT9 SB_DQ[59]
MA_DATA56 AM12 MB_DATA60 AT7
MA_DATA57 SA_DQ[56] MB_DATA61 SB_DQ[60]
AN12 SA_DQ[57] MA_A_A[15:0] {14} AP9 SB_DQ[61]
MA_DATA58 AM13 Y3 MA_A_A0 MB_DATA62 AR10
SA_DQ[58] SA_MA[0] SB_DQ[62] MB_B_A[15:0] {15}
MA_DATA59 AT14 W1 MA_A_A1 MB_DATA63 AT10 U5 MB_B_A0
MA_DATA60 SA_DQ[59] SA_MA[1] MA_A_A2 SB_DQ[63] SB_MA[0] MB_B_A1
AT12 SA_DQ[60] SA_MA[2] AA8 SB_MA[1] V2
MA_DATA61 AL13 AA3 MA_A_A3 T5 MB_B_A2
MA_DATA62 SA_DQ[61] SA_MA[3] MA_A_A4 SB_MA[2] MB_B_A3
AR14 SA_DQ[62] SA_MA[4] V1 SB_MA[3] V3
MA_DATA63 AP14 AA9 MA_A_A5 R1 MB_B_A4
SA_DQ[63] SA_MA[5] MA_A_A6 SB_MA[4] MB_B_A5
SA_MA[6] V8 {15} MB_B_BS0 AB1 SB_BS[0] SB_MA[5] T8
T1 MA_A_A7 W5 R2 MB_B_A6
SA_MA[7] {15} MB_B_BS1 SB_BS[1] SB_MA[6]
Y9 MA_A_A8 R7 R6 MB_B_A7
SA_MA[8] {15} MB_B_BS2 SB_BS[2] SB_MA[7]
AC3 U6 MA_A_A9 R4 MB_B_A8
{14} MA_A_BS0 SA_BS[0] SA_MA[9] SB_MA[8]
AB2 AD4 MA_A_A10 R5 MB_B_A9
{14} MA_A_BS1 SA_BS[1] SA_MA[10] SB_MA[9]
U7 T2 MA_A_A11 AC5 AB5 MB_B_A10
{14} MA_A_BS2 SA_BS[2] SA_MA[11] {15} MB_B_CAS# SB_CAS# SB_MA[10]
U3 MA_A_A12 Y7 P3 MB_B_A11
B SA_MA[12] {15} MB_B_RAS# SB_RAS# SB_MA[11] B
AG8 MA_A_A13 AC6 R3 MB_B_A12
SA_MA[13] {15} MB_B_WE# SB_WE# SB_MA[12]
T3 MA_A_A14 AF7 MB_B_A13
SA_MA[14] MA_A_A15 SB_MA[13] MB_B_A14
{14} MA_A_CAS# AE1 SA_CAS# SA_MA[15] V9 SB_MA[14] P5
AB3 N1 MB_B_A15
{14} MA_A_RAS# SA_RAS# SB_MA[15]
{14} MA_A_WE# AE9 SA_WE#

IC,AUB_CFD_rPGA,R1P0
IC,AUB_CFD_rPGA,R1P0

A A

TOPSTAR TECHNOLOGY
Joseph
Page Name N11M PCIE&PWR&GND
Size Project Name Rev
C C49
A
Date: Friday, May 07, 2010 Sheet 9 of 59
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5 4 3 2 1
 5 4 3 2 1

+VCC_CORE {53}

+V1.1S_VTT {8,11,48,49,53}

U2F

+VCC_CORE +V1.1S_VTT Clarksfield 1.1v

Arrandale 1.05v
D
AG35 VCC1 VTT0_1 AH14 D
AG34 VCC2 VTT0_2 AH12
AG33 AH11 +V1.1S_VTT +V1.1S_VTT
VCC3 VTT0_3
AG32 VCC4 VTT0_4 AH10 C14 C15 C16 C17 C18 C19
AG31 VCC5 VTT0_5 J14
AG30 J13 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R
VCC6 VTT0_6
AG29 VCC7 VTT0_7 H14
AG28 VCC8 VTT0_8 H12
AG27 G14 R58 R156
VCC9 VTT0_9
AG26 VCC10 VTT0_10 G13 1K 1K
AF35 VCC11 VTT0_11 G12 R0402 R0402
AF34 G11 ns
VCC12 VTT0_12 PM_PSI# PM_DPRSLPVR
AF33 VCC13 VTT0_13 F14
AF32 VCC14 VTT0_14 F13
AF31 VCC15 VTT0_15 F12
AF30 VCC16 VTT0_16 F11
AF29 E14 R155 R157
VCC17 VTT0_17
AF28 VCC18 VTT0_18 E12 1K 1K
AF27 VCC19 VTT0_19 D14 R0402 R0402
AF26 D13 ns
VCC20 VTT0_20
AD35 D12
1.1V RAIL POWER
VCC21 VTT0_21
AD34 VCC22 VTT0_22 D11 C20 C21 C22 C23 C24 C25
AD33 VCC23 VTT0_23 C14
AD32 C13 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R 0.22uF/10V,X7R 0.01uF/25V,X7R
VCC24 VTT0_24
AD31 VCC25 VTT0_25 C12
AD30 VCC26 VTT0_26 C11
AD29 VCC27 VTT0_27 B14
AD28 VCC28 VTT0_28 B12
AD27 VCC29 VTT0_29 A14
AD26 VCC30 VTT0_30 A13
AC35 VCC31 VTT0_31 A12
AC34 VCC32 VTT0_32 A11
AC33 VCC33
AC32 VCC34
AC31 +V1.1S_VTT
VCC35
AC30 VCC36 VTT0_33 AF10
AC29 VCC37 VTT0_34 AE10
AC28 VCC38 VTT0_35 AC10
CPU CORE SUPPLY

C AC27 VCC39 VTT0_36 AB10 C

AC26 VCC40 VTT0_37 Y10 C26 C27
AA35 VCC41 VTT0_38 W10
AA34 U10 10uF/6.3V,X5R 10uF/6.3V,X5R
VCC42 VTT0_39
AA33 VCC43 VTT0_40 T10
AA32 VCC44 VTT0_41 J12
AA31 J11 +VCC_CORE
VCC45 VTT0_42
AA30 VCC46 VTT0_43 J16
AA29 VCC47 VTT0_44 J15
AA28 VCC48
AA27 VCC49
AA26 VCC50
Y35 VCC51
Y34 VCC52
Y33 VCC53
Y32 VCC54
Y31 VCC55
Y30 VCC56
Y29 VCC57 C28 C29 C30 C31 C32 C33 C34 C35 C36 C37 C38
Y28 VCC58
Y27 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R
VCC59 ns ns ns ns ns
Y26 VCC60
V35 VCC61 PSI# AN33 PM_PSI# {53}
V34 VCC62
POWER

V33 VCC63
V32 VCC64 VID[0] AK35 H_VID0 {53}
V31 VCC65 VID[1] AK33 H_VID1 {53}
V30 VCC66 VID[2] AK34 H_VID2 {53}
V29 VCC67 VID[3] AL35 H_VID3 {53}
CPU VIDS

V28 VCC68 VID[4] AL33 H_VID4 {53}

V27 VCC69 VID[5] AM33 H_VID5 {53}
V26 VCC70 VID[6] AM35 H_VID6 {53}
U35 VCC71 PROC_DPRSLPVR AM34 PM_DPRSLPVR {53}
U34 VCC72
U33 VCC73
U32 VCC74
U31 G15 VTT_SELECT_R R41 R0402 0
VCC75 VTT_SELECT VTT_SELECT {48}
B
U30 VCC76 B
U29 VCC77
U28 +VCC_CORE
VCC78
U27 VCC79 C39 C40 C41 C42 C43 C44 C45 C46 C47 C48 C49 C50
U26 VCC80
R35 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R
VCC81 ns ns ns ns
R34 VCC82
R33 R43
VCC83
R32 VCC84 ISENSE AN35 Vcore_IMON_R R42 0
Vcore_IMON {53}
100,1%
R31 R0402 R0402
VCC85
R30 VCC86
R29 VCC87
R28 AJ34 VCCSENSE_R R44 R0402 0
SENSE LINES

VCC88 VCC_SENSE VCCSENSE {53}

R27 VCC89 VSS_SENSE AJ35 VSSSENSE_R R45 R0402 0
VSSSENSE {53}
R26 VCC90
P35 VCC91
P34 B15 R46
VCC92 VTT_SENSE T3 ICTP ns
P33 A15 100,1%
VCC93 VSS_SENSE_VTT T1 ICTP ns
P32 R0402
VCC94
P31 VCC95
P30 VCC96 C51 C52 C53 C54 C55 C56 C57 C58 C59 C60 C61 C62
P29 VCC97
P28 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R 1uF/10V,X7R 1uF/10V,X7R 0.22uF/10V,X7R 0.22uF/10V,X7R 0.01uF/25V,X7R 0.01uF/25V,X7R 10uF/6.3V,X5R
VCC98 ns
P27 VCC99
P26 VCC100

IC,AUB_CFD_rPGA,R1P0

A A

TOPSTAR TECHNOLOGY
Joseph
Page Name N11M PCIE&PWR&GND
Size Project Name Rev
C C49
A
Date: Friday, May 07, 2010 Sheet 10 of 59
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5 4 3 2 1
 5 4 3 2 1

+VGFX {49}

+V1.1S_VTT {8,10,48,49,53}

+V1.5 {8,14,15,47,54,55,56}

+V1.8S {16,27,29,30,47,54,55}

D D

+VGFX

U2G

AT21 VAXG1
AT19 VAXG2 VAXG_SENSE AR22 VGFXVCCSEN {49}
AT18 AT22

SENSE
LINES
VAXG3 VSSAXG_SENSE VGFXVSSSEN {49}
AT16 VAXG4
C64 C65 C66 C63 AR21 VAXG5
AR19 VAXG6
10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R AR18 VAXG7
AR16 VAXG8 GFX_VID[0] AM22 GFXVR_VID_0 {49}
AP21 VAXG9 GFX_VID[1] AP22 GFXVR_VID_1 {49} GFXVR_EN {49}

GRAPHICS VIDs
AP19 VAXG10 GFX_VID[2] AN22 GFXVR_VID_2 {49}
AP18 VAXG11 GFX_VID[3] AP23 GFXVR_VID_3 {49}
AP16 VAXG12 GFX_VID[4] AM23 GFXVR_VID_4 {49}
AN21 VAXG13 GFX_VID[5] AP24 GFXVR_VID_5 {49}

GRAPHICS
AN19 VAXG14 GFX_VID[6] AN24 GFXVR_VID_6 {49}
AN18 VAXG15
AN16 R705
VAXG16
AM21 VAXG17 GFX_VR_EN AR25 470
AM19 VAXG18 GFX_DPRSLPVR AT25 GFXVR_DPRSLPVR {49} R0402
AM18 VAXG19 GFX_IMON AM24 VGFX_IMON {49}
AM16 VAXG20
AL21 VAXG21
C AL19 VAXG22
C
AL18 +V1.5
VAXG23
AL16 VAXG24
AK21 VAXG25 VDDQ1 AJ1
AK19 VAXG26 VDDQ2 AF1
AK18 AE7

- 1.5V RAILS
VAXG27 VDDQ3
C67 C68 C69 C70 AK16 VAXG28 VDDQ4 AE4
AJ21 VAXG29 VDDQ5 AC1 C71 C72 C73 C74 C75 C76
0.22uF/10V,X7R 0.01uF/25V,X7R 10uF/6.3V,X5R 10uF/6.3V,X5R AJ19 AB7
VAXG30 VDDQ6 10uF/6.3V,X5R 10uF/6.3V,X5R 1uF/10V,X7R 1uF/10V,X7R 1uF/10V,X7R 1uF/10V,X7R
AJ18 VAXG31 VDDQ7 AB4
AJ16 VAXG32 VDDQ8 Y1
AH21 VAXG33 VDDQ9 W7

POWER
AH19 VAXG34 VDDQ10 W4
AH18 VAXG35 VDDQ11 U1
AH16 VAXG36 VDDQ12 T7
VDDQ13 T4
VDDQ14 P1
+V1.1S_VTT N7
VDDQ15
VDDQ16 N4

DDR3
VDDQ17 L1
J24 VTT1_45 VDDQ18 H1
FDI

J23 VTT1_46
H25 +V1.1S_VTT
VTT1_47
C77 C78
10uF/6.3V,X5R 10uF/6.3V,X5R P10
VTT0_59
VTT0_60 N10
VTT0_61 L10
VTT0_62 K10
+V1.1S_VTT C79 C80
10uF/6.3V,X5R 10uF/6.3V,X5R
1.1V

VTT1_63 J22
K26 VTT1_48 VTT1_64 J20
J27 J18 +V1.1S_VTT
VTT1_49 VTT1_65
PEG & DMI

J26 VTT1_50 VTT1_66 H21

B
J25 VTT1_51 VTT1_67 H20 B
H27 VTT1_52 VTT1_68 H19
C81 C82 C83 C84 G28 VTT1_53
G27 VTT1_54
10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R G26 VTT1_55 C85 C86
F26 VTT1_56
E26 L26 10uF/6.3V,X5R 10uF/6.3V,X5R
VTT1_57 VCCPLL1
1.8V

E25 VTT1_58 VCCPLL2 L27

M26 VCCPLL
VCCPLL3

IC,AUB_CFD_rPGA,R1P0

+V1.8S

VCCPLL FB3 1 2 FB0805

300ohm@100MHz,1.5A
C87 C88 C89 C90
1uF/10V,X7R 1uF/10V,X7R 1uF/10V,X7R 10uF/6.3V,X5R

A A

TOPSTAR TECHNOLOGY
Joseph
Page Name N11M PCIE&PWR&GND
Size Project Name Rev
C C49
A
Date: Friday, May 07, 2010 Sheet 11 of 59
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5 4 3 2 1
 5 4 3 2 1

U2I
U2H

AT20 VSS1 VSS81 AE34

AT17 VSS2 VSS82 AE33 K27 VSS161
AR31 VSS3 VSS83 AE32 K9 VSS162
AR28 VSS4 VSS84 AE31 K6 VSS163
AR26 VSS5 VSS85 AE30 K3 VSS164
AR24 VSS6 VSS86 AE29 J32 VSS165
AR23 VSS7 VSS87 AE28 J30 VSS166
AR20 VSS8 VSS88 AE27 J21 VSS167
D D
AR17 VSS9 VSS89 AE26 J19 VSS168
AR15 VSS10 VSS90 AE6 H35 VSS169
AR12 VSS11 VSS91 AD10 H32 VSS170
AR9 VSS12 VSS92 AC8 H28 VSS171
AR6 VSS13 VSS93 AC4 H26 VSS172
AR3 VSS14 VSS94 AC2 H24 VSS173
AP20 VSS15 VSS95 AB35 H22 VSS174
AP17 VSS16 VSS96 AB34 H18 VSS175
AP13 VSS17 VSS97 AB33 H15 VSS176
AP10 VSS18 VSS98 AB32 H13 VSS177
AP7 VSS19 VSS99 AB31 H11 VSS178
AP4 VSS20 VSS100 AB30 H8 VSS179
AP2 VSS21 VSS101 AB29 H5 VSS180
AN34 VSS22 VSS102 AB28 H2 VSS181
AN31 VSS23 VSS103 AB27 G34 VSS182
AN23 VSS24 VSS104 AB26 G31 VSS183
AN20 VSS25 VSS105 AB6 G20 VSS184
AN17 VSS26 VSS106 AA10 G9 VSS185
AM29 VSS27 VSS107 Y8 G6 VSS186
AM27 VSS28 VSS108 Y4 G3 VSS187
AM25 VSS29 VSS109 Y2 F30 VSS188
AM20 VSS30 VSS110 W35 F27 VSS189
AM17 VSS31 VSS111 W34 F25 VSS190
C AM14 VSS32 VSS112 W33 F22 VSS191 C
AM11 VSS33 VSS113 W32 F19 VSS192
AM8 VSS34 VSS114 W31 F16 VSS193
AM5 VSS35 VSS115 W30 E35 VSS194
AM2 W29 E32
AL34
AL31
VSS36
VSS37
VSS38 VSS
VSS116
VSS117
VSS118
W28
W27
E29
E24
VSS195
VSS196
VSS197
VSS
AL23 VSS39 VSS119 W26 E21 VSS198
AL20 VSS40 VSS120 W6 E18 VSS199
AL17 VSS41 VSS121 V10 E13 VSS200
AL12 VSS42 VSS122 U8 E11 VSS201
AL9 VSS43 VSS123 U4 E8 VSS202
AL6 VSS44 VSS124 U2 E5 VSS203
AL3 VSS45 VSS125 T35 E2 VSS204 VSS_NCTF1 AT35
AK29 VSS46 VSS126 T34 D33 VSS205 VSS_NCTF2 AT1
AK27 VSS47 VSS127 T33 D30 VSS206 VSS_NCTF3 AR34
AK25 VSS48 VSS128 T32 D26 VSS207 VSS_NCTF4 B34
AK20 VSS49 VSS129 T31 D9 VSS208 VSS_NCTF5 B2

NCTF
AK17 VSS50 VSS130 T30 D6 VSS209 VSS_NCTF6 B1
AJ31 VSS51 VSS131 T29 D3 VSS210 VSS_NCTF7 A35
AJ23 VSS52 VSS132 T28 C34 VSS211
AJ20 VSS53 VSS133 T27 C32 VSS212
AJ17 VSS54 VSS134 T26 C29 VSS213
AJ14 VSS55 VSS135 T6 C28 VSS214
B AJ11 VSS56 VSS136 R10 C24 VSS215 B
AJ8 VSS57 VSS137 P8 C22 VSS216
AJ5 VSS58 VSS138 P4 C20 VSS217
AJ2 VSS59 VSS139 P2 C19 VSS218
AH35 VSS60 VSS140 N35 C16 VSS219
AH34 VSS61 VSS141 N34 B31 VSS220
AH33 VSS62 VSS142 N33 B25 VSS221
AH32 VSS63 VSS143 N32 B21 VSS222
AH31 VSS64 VSS144 N31 B18 VSS223
AH30 VSS65 VSS145 N30 B17 VSS224
AH29 VSS66 VSS146 N29 B13 VSS225
AH28 VSS67 VSS147 N28 B11 VSS226
AH27 VSS68 VSS148 N27 B8 VSS227
AH26 VSS69 VSS149 N26 B6 VSS228
AH20 VSS70 VSS150 N6 B4 VSS229
AH17 VSS71 VSS151 M10 A29 VSS230
AH13 VSS72 VSS152 L35 A27 VSS231
AH9 VSS73 VSS153 L32 A23 VSS232
AH6 VSS74 VSS154 L29 A9 VSS233
AH3 VSS75 VSS155 L8
AG10 VSS76 VSS156 L5
AF8 VSS77 VSS157 L2
AF4 VSS78 VSS158 K34 TOPSTAR TECHNOLOGY
AF2 VSS79 VSS159 K33
A AE35 K30 Joseph A
VSS80 VSS160
Page Name N11M PCIE&PWR&GND
Size Project Name Rev
IC,AUB_CFD_rPGA,R1P0 B C49
IC,AUB_CFD_rPGA,R1P0 A
Date: Friday, May 07, 2010 Sheet 12 of 59
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5 4 3 2 1
 5 4 3 2 1

U2E

RSVD32 AJ13
RSVD33 AJ12

AP25 RSVD1
AL25 RSVD2 RSVD34 AH25
AL24 AK26 H11 H12 H13 H14
RSVD3 RSVD35
AL22 RSVD4
AJ33 RSVD5 RSVD36 AL26
D D
AG9 RSVD6 RSVD_NCTF_37 AR2
M27 RSVD7
L28 RSVD8 RSVD38 AJ26
R496 0 R0402 ns J17 AJ27
{14} VREFA_DDR3 R497 0 R0402 ns SA_DIMM_VREF RSVD39 CPU_HOLE CPU_HOLE CPU_HOLE CPU_HOLE
{15} VREFB_DDR3 H17 SB_DIMM_VREF
G25 ns ns ns ns
RSVD11

1
2
3
4
5
6
7
8
9

1
2
3
4
5
6
7
8
9

1
2
3
4
5
6
7
8
9

1
2
3
4
5
6
7
8
9
G17 RSVD12
E31 RSVD13 RSVD_NCTF_40 AP1

1
2
3
4
5
6
7
8
9

1
2
3
4
5
6
7
8
9

1
2
3
4
5
6
7
8
9

1
2
3
4
5
6
7
8
9
E30 RSVD14 RSVD_NCTF_41 AT2

RSVD_NCTF_42 AT3
RSVD_NCTF_43 AR1

RSVD45 AL28
R47 3.01K,1% R0402 ns CFG0 AM30 AL29
CFG[0] RSVD46
AM28 CFG[1] RSVD47 AP30
AP31 CFG[2] RSVD48 AP32
R49 3.01K,1% R0402 CFG3 AL32 AL27
R48 3.01K,1% R0402 ns CFG4 AL30 CFG[3] RSVD49
CFG[4] RSVD50 AT31
AM31 CFG[5] RSVD51 AT32
AN29 CFG[6] RSVD52 AP33
C AM32 CFG[7] RSVD53 AR33 C
AK32 CFG[8] RSVD_NCTF_54 AT33
AK31 AT34

RESERVED
CFG[9] RSVD_NCTF_55
AK28 CFG[10] RSVD_NCTF_56 AP35
AJ28 CFG[11] RSVD_NCTF_57 AR35
AN30 AR32 BRACKET BRACKET1_Mylar
CFG[12] RSVD58
AN32 CFG[13]
AJ32 CFG[14]
AJ29 CFG[15] RSVD_TP_59 E15
AJ30 CFG[16] RSVD_TP_60 F15
AK30 CFG[17] KEY A2
H16 RSVD_TP_86 RSVD62 D15
RSVD63 C15
RSVD64 AJ15
RSVD65 AH15

B19 RSVD15
A19 RSVD16
A20 RSVD17
B20 RSVD18
RSVD_TP_66 AA5
U9 RSVD19 RSVD_TP_67 AA4
T9 RSVD20 RSVD_TP_68 R8
B
RSVD_TP_69 AD3 B
AC9 RSVD21 RSVD_TP_70 AD2
AB9 RSVD22 RSVD_TP_71 AA2
RSVD_TP_72 AA1
RSVD_TP_73 R9
RSVD_TP_74 AG7
CPU_BRACKET Mylar
C1 RSVD_NCTF_23 RSVD_TP_75 AE3
A3 RSVD_NCTF_24

RSVD_TP_76 V4
RSVD_TP_77 V5
RSVD_TP_78 N2
J29 RSVD26 RSVD_TP_79 AD5
J28 RSVD27 RSVD_TP_80 AD7
RSVD_TP_81 W3
A34 RSVD_NCTF_28 RSVD_TP_82 W2
A33 RSVD_NCTF_29 RSVD_TP_83 N3
RSVD_TP_84 AE5
C35 RSVD_NCTF_30 RSVD_TP_85 AD9
B35 RSVD_NCTF_31
AP34 R50 0 R0402
VSS
TOPSTAR TECHNOLOGY
A Joseph A
Page Name N11M PCIE&PWR&GND
IC,AUB_CFD_rPGA,R1P0
Size Project Name Rev
B C49
A
Date: Friday, May 07, 2010 Sheet 13 of 59
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5 4 3 2 1
 5 4 3 2 1

+V3.3S {6,8,15,16,22,23,24,25,26,27,28,29,30,32,33,34,35,36,37,38,40,41,42,43,47,48,49,50,51,53,54,55,56}
+V1.5 {8,11,15,47,54,55,56}
+V0.75S {15,47,54}

+V0.75S +V1.5

+V1.5

204
203

100
105
106
111
112
117
118
123
124

145
150
151
155
156
161
162
167
168
172
173
178
179
184
185
189
190
195
196

1
C91

75
76
81
82
87
88
93
94
99
D D
DIMM1 + ns C92 C93 C94 C95 C96 C97 C98

1
{9} MA_A_A[15:0]
ns ns ns

VTT2
VTT1

VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18

VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
MA_DATA[63:0] {9} CT7343_19 C0402 C0805 C0805 C0402 C0805 C0402 C0805

2
MA_A_A0 98 5 MA_DATA0 0.1UF/25V,Y5V 2.2UF/10V,X7R 2.2UF/10V,X7R 2.2UF/10V,X7R
MA_A_A1 A0 D0 MA_DATA1 220UF/2.5V,POSCAP 2.2UF/10V,X7R 0.1UF/25V,Y5V 0.1UF/25V,Y5V
97 A1 D1 7
MA_A_A2 96 15 MA_DATA2
MA_A_A3 A2 D2 MA_DATA3
95 A3 D3 17
MA_A_A4 92 4 MA_DATA4 1, A minimum of 9 high frequency
MA_A_A5 A4 D4 MA_DATA5 capacitors are recommended to be
91 A5 D5 6
MA_A_A6 90 16 MA_DATA6 placed near each SO-DIMM of DDR2.
MA_A_A7 A6 D6 MA_DATA7 +V1.5 2, 2.2μF*5 per DIMM,0.1μF*4 per
86 A7 D7 18
MA_A_A8 89 21 MA_DATA8 DIMM,330μF*1 per DIMM
MA_A_A9 A8 D8 MA_DATA9
85 A9 D9 23
MA_A_A10 107 33 MA_DATA10
MA_A_A11 A10/AP D10 MA_DATA11
84 A11 D11 35
MA_A_A12 83 22 MA_DATA12
MA_A_A13 A12/BC# D12 MA_DATA13 C100 C101 C103 C104
119 A13 D13 24 C105 C106
MA_A_A14 80 34 MA_DATA14
MA_A_A15 A14 D14 MA_DATA15 10uF/6.3V,X5R
C0402 C0805 10uF/6.3V,X5R
C0805 C0402
78 A15 D15 36
39 MA_DATA16 2.2UF/10V,X7R 2.2UF/10V,X7R
D16 MA_DATA17 0.1UF/25V,Y5V 0.1UF/25V,Y5V
{9} MA_A_BS0 109 BA0 D17 41
108 51 MA_DATA18
{9} MA_A_BS1 BA1 D18
79 53 MA_DATA19
{9} MA_A_BS2 BA2 D19
40 MA_DATA20
D20
{9}
{9}
M_CS#0
M_CS#1
114
121
CS0
CS1
D21
D22
42
50
MA_DATA21
MA_DATA22 Layout note:电容靠近DDR slot VDD PIN
52 MA_DATA23
MA_DM0 D23 MA_DATA24
11 DQM0 D24 57
MA_DM1 28 59 MA_DATA25
MA_DM2 DQM1 D25 MA_DATA26 +V0.75S
46 DQM2 D26 67
MA_DM3 63 69 MA_DATA27
MA_DM4 DQM3 D27 MA_DATA28
136 DQM4 D28 56
MA_DM5 153 58 MA_DATA29
MA_DM6 DQM5 D29 MA_DATA30
{9} MA_DM[7:0] 170 DQM6 D30 68
MA_DM7 187 70 MA_DATA31 C99 C102 C107 C108
DQM7 D31 MA_DATA32
D32 129
113 131 MA_DATA33 1uF/10V,X7R 1uF/10V,X7R 1uF/10V,X7R 1uF/10V,X7R
{9} MA_A_WE# WE D33
C 115 141 MA_DATA34 C
{9} MA_A_CAS# CAS D34
110 143 MA_DATA35
{9} MA_A_RAS# RAS D35
130 MA_DATA36
D36 MA_DATA37
{9} M_CKE0 73 CKE0 D37 132
74 140 MA_DATA38
{9} M_CKE1 CKE1 D38 MA_DATA39
D39 142
101 147 MA_DATA40
{9} M_CLK_DDR0 CK0 D40 MA_DATA41
{9} M_CLK_DDR#0 103 CK0 D41 149
102 157 MA_DATA42
{9} M_CLK_DDR1 CK1 D42 MA_DATA43
{9} M_CLK_DDR#1 104 CK1 D43 159
146 MA_DATA44
D44 MA_DATA45
{9} M_ODT0 116 ODT0 D45 148
120 158 MA_DATA46
{9} M_ODT1 ODT1 D46
160 MA_DATA47
MA_DQS0 D47 MA_DATA48
12 DQS0 D48 163
MA_DQS1 29 165 MA_DATA49
MA_DQS2 DQS1 D49 MA_DATA50
47 DQS2 D50 175
MA_DQS3 64 177 MA_DATA51
MA_DQS4 DQS3 D51 MA_DATA52
137 DQS4 D52 164
MA_DQS5 154 166 MA_DATA53
MA_DQS6 DQS5 D53 MA_DATA54
{9} MA_DQS[7:0] 171 DQS6 D54 174
MA_DQS7 188 176 MA_DATA55
DQS7 D55 MA_DATA56
D56 181
200 183 MA_DATA57
{6,15,24,37} SMB_DATA_S SDA D57 MA_DATA58
{6,15,24,37} SMB_CLK_S 202 SCL D58 191
193 MA_DATA59
R415 10K R0402 D59 MA_DATA60
197 SA0 D60 180
+V3.3S R414 10K R0402 201 182 MA_DATA61
SA1 D61 MA_DATA62
D62 192
199 194 MA_DATA63
VDDSPD D63
close to DDR pin
VREFA_DDR3 R416 0 1 10 MA_DQS#0
0.1UF/25V,Y5V C380 VREFB_CA VREF_DQ DQS#0 MA_DQS#1
126 VREF_CA DQS#1 27
C379 45 MA_DQS#2
C382 DQS#2 MA_DQS#3
198 EVENT# DQS#3 62
C0402 2.2UF/10V,X7R C381 2.2UF/10V,X7R 30 135 MA_DQS#4
C0805 0.1UF/25V,Y5V RESET# DQS#4 MA_DQS#5
DQS#5 152
C0402 C0805 77 169 MA_DQS#6
B NC1 DQS#6 B
close to DDR pin 122 NC2 DQS#7 186 MA_DQS#7
125 NCTEST MA_DQS#[7:0] {9}
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33

GND1
GND2
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9

DDR3_SODIMM204_0
2
3
8
9
13
14
19
20
25
26
31
32
37
38
43
44
48
49
54
55
60
61
65
66
71
72
127
128
133
134
138
139
144

205
206

{8} DIM_EXTTS#0

{8,15} DDR3_DRAMRST#

+V1.5 +V1.5

R492 R900
1K,1% 1K,1%
R0402 R0402
VREFA_DDR3 VREFB_CA
VREFA_DDR3 {13}

R493 R901 C538

1K,1% 1K,1% C537
R0402 R04020.1UF/25V,Y5V
C0402 2.2UF/10V,X7R
C0805
A close to DDR pin A

TOPSTAR TECHNOLOGY
Joseph
Page Name DDR3 SODIMM0
Size Project Name Rev
C C49
A
Date: Friday, May 07, 2010 Sheet 14 of 59
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5 4 3 2 1
 5 4 3 2 1

+V3.3S {6,8,14,16,22,23,24,25,26,27,28,29,30,32,33,34,35,36,37,38,40,41,42,43,47,48,49,50,51,53,54,55,56}
+V1.5 {8,11,14,47,54,55,56}
+V0.75S {14,47,54}

+V0.75S +V1.5
D D

204
203

100
105
106
111
112
117
118
123
124

145
150
151
155
156
161
162
167
168
172
173
178
179
184
185
189
190
195
196
75
76
81
82
87
88
93
94
99
DIMM2
{9} MB_B_A[15:0]
MB_DATA[63:0] {9}

VTT2
VTT1

VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18

VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
MB_B_A0 98 5 MB_DATA0
MB_B_A1 A0 D0 MB_DATA1
97 A1 D1 7
MB_B_A2 96 15 MB_DATA2
MB_B_A3 A2 D2 MB_DATA3
95 A3 D3 17
+V1.5 MB_B_A4 92 4 MB_DATA4
MB_B_A5 A4 D4 MB_DATA5
91 A5 D5 6
MB_B_A6 90 16 MB_DATA6
MB_B_A7 A6 D6 MB_DATA7
86 A7 D7 18
C109 C110 C111 C112 C113 C114 C115 C116 C117 MB_B_A8 89 21 MB_DATA8
ns ns MB_B_A9 A8 D8 MB_DATA9
85 A9 D9 23
C0805 C0805 C0402 C0805 C0805 C0402 C0805 C0805 C0402 MB_B_A10 107 33 MB_DATA10
2.2UF/10V,X7R 2.2UF/10V,X7R 0.1UF/25V,Y5V 2.2UF/10V,X7R MB_B_A11 A10/AP D10 MB_DATA11
84 A11 D11 35
10UF/6.3V,X5R 0.1UF/25V,Y5V 2.2UF/10V,X7R 2.2UF/10V,X7R 0.1UF/25V,Y5V MB_B_A12 83 22 MB_DATA12
MB_B_A13 A12/BC# D12 MB_DATA13
119 A13 D13 24
+V1.5 MB_B_A14 80 34 MB_DATA14
MB_B_A15 A14 D14 MB_DATA15
78 A15 D15 36
39 MB_DATA16
C118 C119 D16 MB_DATA17
{9} MB_B_BS0 109 BA0 D17 41
10uF/6.3V,X5R 10uF/6.3V,X5R 108 51 MB_DATA18
{9} MB_B_BS1 BA1 D18
C0805 C0805 79 53 MB_DATA19
{9} MB_B_BS2 BA2 D19
+V1.5 40 MB_DATA20
D20 MB_DATA21
{9} M_CS#2 114 CS0 D21 42
121 50 MB_DATA22
{9} M_CS#3 CS1 D22 MB_DATA23
D23 52
C120 C121 C122 C123 C124 C125 C126 C127 MB_DM0 11 57 MB_DATA24
ns ns ns ns MB_DM1 DQM0 D24 MB_DATA25
28 DQM1 D25 59
C0402 C0805 C0402 C0805 C0805 C0402 C0805 C0805 MB_DM2 46 67 MB_DATA26
0.1UF/25V,Y5V2.2UF/10V,X7R 2.2UF/10V,X7R 0.1UF/25V,Y5V 2.2UF/10V,X7R MB_DM3 DQM2 D26 MB_DATA27
63 DQM3 D27 69
0.1UF/25V,Y5V 2.2UF/10V,X7R 2.2UF/10V,X7R MB_DM4 136 56 MB_DATA28
MB_DM5 DQM4 D28 MB_DATA29
153 DQM5 D29 58
C Layout note:电容靠近DDR SLOT VDD PIN {9} MB_DM[7:0]
MB_DM6 170 DQM6 D30 68 MB_DATA30 C
MB_DM7 187 70 MB_DATA31
DQM7 D31 MB_DATA32
D32 129
113 131 MB_DATA33
{9} MB_B_WE# WE D33
115 141 MB_DATA34
{9} MB_B_CAS# CAS D34
110 143 MB_DATA35
{9} MB_B_RAS# RAS D35
130 MB_DATA36
D36 MB_DATA37
{9} M_CKE2 73 CKE0 D37 132
74 140 MB_DATA38
+V0.75S {9} M_CKE3 CKE1 D38 MB_DATA39
D39 142
101 147 MB_DATA40
{9} M_CLK_DDR2 CK0 D40 MB_DATA41
{9} M_CLK_DDR#2 103 CK0 D41 149
102 157 MB_DATA42
{9} M_CLK_DDR3 CK1 D42 MB_DATA43
{9} M_CLK_DDR#3 104 CK1 D43 159
C383 C384 C385 C386 146 MB_DATA44
D44 MB_DATA45
{9} M_ODT2 116 ODT0 D45 148
1uF/10V,X7R 1uF/10V,X7R 1uF/10V,X7R 1uF/10V,X7R 120 158 MB_DATA46
{9} M_ODT3 ODT1 D46
ns ns ns ns 160 MB_DATA47
MB_DQS0 D47 MB_DATA48
12 DQS0 D48 163
MB_DQS1 29 165 MB_DATA49
MB_DQS2 DQS1 D49 MB_DATA50
47 DQS2 D50 175
MB_DQS3 64 177 MB_DATA51
DQS3 D51
C46这几个电容拿掉了 MB_DQS4 137 DQS4 D52 164 MB_DATA52
MB_DQS5 154 166 MB_DATA53
MB_DQS6 DQS5 D53 MB_DATA54
{9} MB_DQS[7:0] 171 DQS6 D54 174
MB_DQS7 188 176 MB_DATA55
DQS7 D55 MB_DATA56
D56 181
200 183 MB_DATA57
{6,14,24,37} SMB_DATA_S SDA D57 MB_DATA58
{6,14,24,37} SMB_CLK_S 202 SCL D58 191
Note: D59 193 MB_DATA59
SO-DIMM1 SPD Address is 0xA4 R54 10K R0402 197 180 MB_DATA60
+V3.3S R55 10K R0402 SA0 D60 MB_DATA61
SO-DIMM1 TS Address is 0x34 201 SA1 D61 182
192 MB_DATA62
D62 MB_DATA63
199 VDDSPD D63 194

VREFB_DDR3 1 10 MB_DQS#0
VREF_DQ DQS#0
close to DDR pin VREFA_CA 126 VREF_CA DQS#1 27 MB_DQS#1
45 MB_DQS#2
B
C130 C131 DQS#2 MB_DQS#3 B
198 EVENT# DQS#3 62
C129 C128 30 135 MB_DQS#4
0.1UF/25V,Y5V 0.1UF/25V,Y5V RESET# DQS#4 MB_DQS#5
DQS#5 152
C0402 2.2UF/10V,X7R C0402 2.2UF/10V,X7R 77 169 MB_DQS#6
C0805 C0805 NC1 DQS#6 MB_DQS#7
122 NC2 DQS#7 186
close to DDR pin 125 NCTEST MB_DQS#[7:0] {9}

VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33

GND1
GND2
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
DDR3_SODIMM204_0
2
3
8
9
13
14
19
20
25
26
31
32
37
38
43
44
48
49
54
55
60
61
65
66
71
72
127
128
133
134
138
139
144

205
206
{8} DIM_EXTTS#1

{8,14} DDR3_DRAMRST#

+V1.5

+V1.5

R494
1K,1%
R0402 R902
1K,1%
VREFB_DDR3 R0402
VREFB_DDR3 {13}
VREFA_CA
R495
1K,1%
R0402 R903 C540
1K,1% C539 2.2UF/10V,X7R
A R04020.1UF/25V,Y5V A
C0402 C0805

close to DDR pin

TOPSTAR TECHNOLOGY
Joseph
Page Name DDR3 SODIMM1
Size Project Name Rev
C C49
A
Date: Friday, May 07, 2010 Sheet 15 of 59
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5 4 3 2 1
 5 4 3 2 1

+V3.3S {6,8,14,15,22,23,24,25,26,27,28,29,30,32,33,34,35,36,37,38,40,41,42,43,47,48,49,50,51,53,54,55,56}
+V1.8S {11,27,29,30,47,54,55}

+V1.8S +V1.8S

U26

D GND 43 D
1 VSS VDD7 42
2 VDD VSS8 41
{22} LVDS_CLKAP 3 TMDS2+ VDD6 40
{22} LVDS_CLKAM 4 TMDS2- VSS7 39
5 VSS1 ATMDS2+ 38 PCH_LVDS_CLKAP {26}
{22} LVDS_YAP2 6 TMDS1+ ATMDS2- 37 PCH_LVDS_CLKAM {26}
{22} LVDS_YAM2 7 TMDS1- ATMDS1+ 36 PCH_LVDS_YAP2 {26}
8 VDD1 ATMDS1- 35 PCH_LVDS_YAM2 {26}
{27} LVDS_SEL 9 SEL ATMDS0+ 34 PCH_LVDS_YAP1 {26}
10 VSS2 ATMDS0- 33 PCH_LVDS_YAM1 {26}
{22} LVDS_YAP1 11 TMDS0+ ATMDSCLK+ 32 PCH_LVDS_YAP0 {26}
{22} LVDS_YAM1 12 TMDS0- ATMDSCLK- 31 PCH_LVDS_YAM0 {26}
13 VSS3 VDD5 30
{22} LVDS_YAP0 14 TMDSCLK+ BTMDS2+ 29 GPU_LVDS_CLKAP {20}
{22} LVDS_YAM0 15 TMDSCLK- BTMDS2- 28 GPU_LVDS_CLKAM {20}
16 VDD2 BTMDS1+ 27 GPU_LVDS_YAP2 {20}
17 VSS4 BTMDS1- 26 GPU_LVDS_YAM2 {20}
18 VDD3 BTMDS0+ 25 GPU_LVDS_YAP1 {20}
19 VSS5 BTMDS0- 24 GPU_LVDS_YAM1 {20}
20 VDD4 BTMDSCLK+ 23 GPU_LVDS_YAP0 {20}
21 VSS6 BTMDSCLK- 22 GPU_LVDS_YAM0 {20}

TS3DV421

PM

+V3.3S
+V3.3S
C C

U27

{27} LVDS_DDC_SEL 1 IN1 COM1 10 EDID_CLK {22} U28

{21} G_SMB_CLK 2 NO1 NC1 9 PCH_DDC_CLK {26} {21} GPU_LVDS_BKLTEN_R 1 NO IN 6 LVDS_BLT_SEL {27}
3 GND V+ 8 2 GND V+ 5

{21} G_SMB_DATA 4 NO2 NC2 7 PCH_DDC_DATA {26} {26} PCH_LVDS_BKLTEN 3 NC COM 4 LVDS_BKLTEN {22}
5 6 ts5a3157
IN2 COM2 EDID_DATA {22}
TS5A23157 PM

PM

+V3.3S

U29

{21} GPU_LVDS_VDDEN 1 NO IN 6 LVDS_SEL_PCH {27}

2 GND V+ 5

{26} PCH_LVDS_VDDEN 3 NC COM 4 LVDS_VDDEN {22}

ts5a3157

PM

B B

RN4 1 2 0
{26} PCH_LVDS_CLKAP LVDS_CLKAP {22}
RA0402_4 3 4 GM
{26} PCH_LVDS_CLKAM LVDS_CLKAM {22}
RN5 1 2 0
{26} PCH_LVDS_YAP2 LVDS_YAP2 {22}
RA0402_4 3 4 GM
{26} PCH_LVDS_YAM2 LVDS_YAM2 {22}
RN6 1 2 0
{26} PCH_LVDS_YAP1 LVDS_YAP1 {22}
RA0402_4 3 4 GM
{26} PCH_LVDS_YAM1 LVDS_YAM1 {22}
RN7 1 2 0
{26} PCH_LVDS_YAP0 LVDS_YAP0 {22}
{26} PCH_LVDS_YAM0 RA0402_4 3 4 GM
LVDS_YAM0 {22}

R893 GM 0 R0402
{26} PCH_LVDS_BKLTEN LVDS_BKLTEN {22}

R894 GM 0 R0402
{26} PCH_LVDS_VDDEN LVDS_VDDEN {22}

{26} PCH_DDC_CLK R891 GM 0 R0402

EDID_CLK {22}

{26} PCH_DDC_DATA R892 GM 0 R0402

EDID_DATA {22}
A A

TOPSTAR TECHNOLOGY
Joseph
Page Name DDR3 Decoupling
Size Project Name Rev
C C49
A
Date: Friday, May 07, 2010 Sheet 16 of 59
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5 4 3 2 1
 5 4 3 2 1

+V3.3GPU {20,21,36,38,55}
+VGA_CORE {50}
+V1.05GPU {18,19,20,55}

D D

GR1 0 ns
+V3.3GPU

GC1
0.1uF/10V,X7R +V1.05GPU
ns

5
EC_GPU_RST# VCC
GU1 GR2 is used for test only, so it Under GPU Near GPU
{42} EC_GPU_RST# 1 can be unstuff for cost saving.
4 GPU_RST#
2 GC3 GC4 GC5 GC6 GC8
{8,27,34,35,37,41,42} BUF_PLT_RST# GND U3A C0805
C0805
SN74AHC1G08DBV GR2 0.1uF/10V,X7R C0402 C0402 4.7uF/10V,X5R 10uF/6.3V,X5R

3
SOT23_5 100K AM16 PCI_EXPRESS AK16 1uF/10V,X5R 1uF/10V,X5R
PM PM PCIE_CLKREQ PEX_RST# PEX_IOVDD_01
AR13 PEX_CLKREQ PEX_IOVDD_02 AK17
AK21 PM PM PM PM PM
GR3 200,1% R0402 AJ17 PEX_IOVDD_03 +VGA_CORE U3F +VGA_CORE U3G
PEX_TSTCLK_OUT PEX_IOVDD_04 AK24
ns AJ18 AK27 PEX_IOVDD+PEX_IOVDDQ:MAX:2200mA +V1.05GPU
PEX_TSTCLK_OUT# PEX_IOVDD_05 NVVDD
{24} PCIE_CLKREQ GND
GND_096 E15
{24} CLK_PCIE_N11M AR16 PEX_REFCLK Under GPU Near GPU AB11 VDD_001 GND_097 E18
{24} CLK_PCIE_N11M# AR17 PEX_REFCLK# PEX_IOVDDQ_1 AG11 AB13 VDD_002 VDD_057 P21 AA11 GND_1 GND_098 E24
PEX_IOVDDQ_2 AG12 AB15 VDD_003 VDD_058 P23 AA12 GND_2 GND_099 E27
AG13 GC15 GC16 GC18 GC13 GC9 GC19 GC20 AB17 P25 AA13 E30
PEG_TXP15 GC14 0.1UF/10V,X7R PEX_IOVDDQ_3 C0805 C0805 C0805 VDD_004 VDD_059 GND_3 GND_100
AL17 PEX_TX0 PEX_IOVDDQ_4 AG15 AB19 VDD_005 VDD_060 R11 AA14 GND_4 GND_101 E6
PEG_RXP[15..0] PEG_TXN15 GC17 0.1UF/10V,X7R AM17 AG16 0.1uF/10V,X7R 0.1uF/10V,X7R C0402 C0402 4.7uF/10V,X5R 4.7uF/10V,X5R10uF/6.3V,X5R AB21 R12 AA15 E9
{7} PEG_RXP[15..0] PEX_TX0# PEX_IOVDDQ_5 VDD_006 VDD_061 GND_5 GND_102
PM AG17 1uF/10V,X5R 1uF/10V,X5R AB23 R13 AA16 F2
PEG_RXN[15..0] PEG_RXP15 PEX_IOVDDQ_6 VDD_007 VDD_062 GND_6 GND_103
{7} PEG_RXN[15..0] PM AP17 PEX_RX0 PEX_IOVDDQ_7 AG18 AB25 VDD_008 VDD_063 R14 AA17 GND_7 GND_104 F31
PEG_RXN15 AN17 AG22 PM PM PM PM PM PM PM AC11 R15 AA18 F34
PEG_TXP[15..0] PEX_RX0# PEX_IOVDDQ_8 VDD_009 VDD_064 GND_8 GND_105
{7} PEG_TXP[15..0] PEX_IOVDDQ_9 AG23 AC12 VDD_010 VDD_065 R16 AA19 GND_9 GND_106 F5
PEG_TXP14 GC21 0.1UF/10V,X7R AM18 AG24 AC13 R17 AA2 J2
PEG_TXN[15..0] PEG_TXN14 GC10 0.1UF/10V,X7R PEX_TX1 PEX_IOVDDQ_10 VDD_011 VDD_066 GND_10 GND_107
{7} PEG_TXN[15..0] AM19 PEX_TX1# AC14 VDD_012 VDD_067 R18 AA20 GND_11 GND_108 J31
PM AC15 VDD_013 VDD_068 R19 AA21 GND_12 GND_109 J34
PEG_RXP14 PM AN19 AC16 R20 AA22 J5
PEG_RXN14 PEX_RX1 VDD_014 VDD_069 GND_13 GND_110
AP19 PEX_RX1# AC17 VDD_015 VDD_070 R21 AA23 GND_14 GND_111 L9
+V3.3GPU +V3.3GPU AG25 +VGA_CORE AC18 R22 AA24 M11
PEG_TXP13 GC22 0.1UF/10V,X7R PEX_IOVDDQ_11 VDD_016 VDD_071 GND_15 GND_112
AL19 PEX_TX2 PEX_IOVDDQ_12 AG26 AC19 VDD_017 VDD_072 R23 AA25 GND_16 GND_113 M13
PEG_TXN13 GC23 0.1UF/10V,X7R AK19 PEX_TX2# PEX_IOVDDQ_13 AJ14 MAX:19.6A Under GPU Near GPU AC20 VDD_018 VDD_073 R24 AA34 GND_17 GND_114 M15
PM PEX_IOVDDQ_14 AJ15 AC21 VDD_019 VDD_074 R25 AA5 GND_18 GND_115 M17
PEG_RXP13 PM AR19 AJ19 AC22 T12 AB12 M19
GR53 GR4 PEG_RXN13 PEX_RX2 PEX_IOVDDQ_15 VDD_020 VDD_075 GND_19 GND_116
AR20 PEX_RX2# PEX_IOVDDQ_16 AJ21 AC23 VDD_021 VDD_076 T14 AB14 GND_20 GND_117 M2
10K 10K AJ22 GC24 GC12 GC25 GC27 GC28 GC29 AC24 T16 AB16 M21
PM PM PEG_TXP12 GC11 0.1UF/10V,X7R PEX_IOVDDQ_17 C0402 C0805 VDD_022 VDD_077 GND_21 GND_118
AL20 PEX_TX3 PEX_IOVDDQ_18 AJ24 AC25 VDD_023 VDD_078 T18 AB18 GND_22 GND_119 M23
S_Bot PEG_TXN12 GC26 0.1UF/10V,X7R AM20 AJ25 0.047uF/16V,X7R 0.22uF/10V,X7R C0603 1uF/10V,X5R 4.7uF/10V,X5R AD12 T20 AB20 M25
PEX_TX3# PEX_IOVDDQ_19 0.047uF/16V,X7R 0.22uF/10V,X7R VDD_024 VDD_079 GND_23 GND_120
PM PEX_IOVDDQ_20 AJ27 AD14 VDD_025 VDD_080 T22 AB22 GND_24 GND_121 M31
EC_GPU_RST# PCIE_CLKREQ PEG_RXP12 PM AP20 AK18 AD16 T24 AB24 M34
PEG_RXN12 PEX_RX3 PEX_IOVDDQ_21 PM PM PM PM PM PM VDD_026 VDD_081 GND_25 GND_122
AN20 PEX_RX3# PEX_IOVDDQ_22 AK20 AD18 VDD_027 VDD_082 V11 AC9 GND_26 GND_123 M5
PEX_IOVDDQ_23 AK23 AD22 VDD_028 VDD_083 V13 AD11 GND_27 GND_124 N11
C PEG_TXP11 GC30 0.1UF/10V,X7R AM21 AK26 AD24 V15 AD13 N12 C
PEG_TXN11 GC31 0.1UF/10V,X7R PEX_TX4 PEX_IOVDDQ_24 VDD_029 VDD_084 GND_28 GND_125
AM22 PEX_TX4# PEX_IOVDDQ_25 AL16 L11 VDD_030 VDD_085 V17 AD15 GND_29 GND_126 N13
PM L12 VDD_031 VDD_086 V19 AD17 GND_30 GND_127 N14
PEG_RXP11 PM AN22 GC32 GC33 GC45 GC35 GC36 L13 V21 AD2 N15
PEG_RXN11 PEX_RX4 C0402 VDD_032 VDD_087 GND_31 GND_128
AP22 PEX_RX4# L14 VDD_033 VDD_088 V23 AD21 GND_32 GND_129 N16
0.047uF/16V,X7R C0402 C0402 0.022uF/16V,X7R L15 V25 AD23 N17
PEG_TXP10 GC37 0.1UF/10V,X7R 0.022uF/16V,X7R 0.022uF/16V,X7R
0.022uF/16V,X7R VDD_034 VDD_089 GND_33 GND_130
AL22 PEX_TX5 L16 VDD_035 VDD_090 W11 AD25 GND_34 GND_131 N18
PEG_TXN10 GC38 0.1UF/10V,X7R AK22 L17 W12 AD31 N19
PEX_TX5# PM PM PM PM PM VDD_036 VDD_091 GND_35 GND_132
PM L18 VDD_037 VDD_092 W13 AD34 GND_36 GND_133 N20
PEG_RXP10 PM AR22 L19 W14 AD5 N21
PEG_RXN10 PEX_RX5 VDD_038 VDD_093 GND_37 GND_134
AR23 PEX_RX5# L20 VDD_039 VDD_094 W15 AE11 GND_38 GND_135 N22
L21 VDD_040 VDD_095 W16 AE12 GND_39 GND_136 N23
PEG_TXP9 GC39 0.1UF/10V,X7R AL23 L22 W17 AE13 N24
PEG_TXN9 GC42 0.1UF/10V,X7R PEX_TX6 GC40 GC41 GC43 GC44 VDD_041 VDD_096 GND_40 GND_137
AM23 PEX_TX6# L23 VDD_042 VDD_097 W18 AE14 GND_41 GND_138 N25
PM
NC_1 A2 L24 VDD_043 VDD_098 W19 AE15 GND_42 GND_139 P12
PEG_RXP9 PM AP23 AA4 C0402 0.01uF/25V,X7R C0402 0.01uF/25V,X7R L25 W20 AE16 P14
PEG_RXN9 PEX_RX6 NC_2 0.01uF/25V,X7R 0.01uF/25V,X7R VDD_044 VDD_099 GND_43 GND_140
AN23 PEX_RX6# NC_3 AB4 M12 VDD_045 VDD_100 W21 AE17 GND_44 GND_141 P16
AB7 PM PM PM PM M14 W22 AE18 P18
PEG_TXP8 GC46 0.1UF/10V,X7R NC_4 VDD_046 VDD_101 GND_45 GND_142
AM24 PEX_TX7 NC_5 AC5 M16 VDD_047 VDD_102 W23 AE19 GND_46 GND_143 P20
PEG_TXN8 GC47 0.1UF/10V,X7R AM25 AD6 M18 W24 AE20 P22
PEX_TX7# NC_6 VDD_048 VDD_103 GND_47 GND_144
PM NC_7 AF6 M20 VDD_049 VDD_104 W25 AE21 GND_48 GND_145 P24
PEG_RXP8 PM AN25 AG6 GC48 GC49 GC50 M22 Y12 AE22 R2
PEG_RXN8 PEX_RX7 NC_8 VDD_050 VDD_105 GND_49 GND_146
AP25 PEX_RX7# NC_9 AJ5 M24 VDD_051 VDD_106 Y14 AE23 GND_50 GND_147 R31
AK15 C0402 4700pF/25V,X7R C0402 P11 Y16 AE24 R34
PEG_TXP7 GC51 0.1UF/10V,X7R NC_10 0.01uF/25V,X7R 4700pF/25V,X7R VDD_052 VDD_107 GND_51 GND_148
AL25 PEX_TX8 NC_11 AL7 P13 VDD_053 VDD_108 Y18 AE25 GND_52 GND_149 R5
PEG_TXN7 GC52 0.1UF/10V,X7R AK25 E7 P15 Y20 AG2 T11
PEX_TX8# NC_14 PM PM PM VDD_054 VDD_109 GND_53 GND_150
PM NC_16 H32 P17 VDD_055 VDD_110 Y22 AG31 GND_54 GND_151 T13
PEG_RXP7 PM AR25 M7 P19 Y24 AG34 T15
PEG_RXN7 PEX_RX8 NC_17 VDD_056 VDD_111 GND_55 GND_152
AR26 PEX_RX8# NC_18 P6 AG5 GND_56 GND_153 T17
NC_21 U7 AK2 GND_57 GND_154 T19
PEG_TXP6 GC53 0.1UF/10V,X7R AL26 V6 +V3.3GPU AK31 T21
PEX_TX9 NC_22 GND_58 GND_155
PEG_TXN6 GC54 0.1UF/10V,X7R AM26 PEX_TX9# NC_23 Y4 MAX:120mA Under GPU Near GPU NB10_G128
PM
AK34 GND_59 GND_156 T23
PM AK5 GND_60 GND_157 T25
PEG_RXP6 PM AP26 AL12 U11
PEG_RXN6 PEX_RX9 GC55 GC56 GC57 GND_61 GND_158
AN26 PEX_RX9# AL15 GND_62 GND_159 U12
C0603 C0805 AL18 U13
PEG_TXP5 GC58 0.1UF/10V,X7R 0.1uF/10V,X7R 1uF/10V,X7R 4.7uF/10V,X5R GND_63 GND_160
AM27 PEX_TX10 AL21 GND_64 GND_161 U14
PEG_TXN5 GC59 0.1UF/10V,X7R AM28 F7 AL24 U15
PEX_TX10# PEX_SVDD_3V3_1 PM PM PM GND_65 GND_162
PM
PEX_SVDD_3V3_2 AG19 AL27 GND_66 GND_163 U16
PEG_RXP5 PM AN28 AL30 U17
PEG_RXN5 PEX_RX10 GND_67 GND_164
AP28 PEX_RX10# MAX:180mA AL6 GND_68 GND_165 U18
VDD33_1 J10 AL9 GND_69 GND_166 U19
PEG_TXP4 GC60 0.1UF/10V,X7R AL28 J11 AN2 U20
PEG_TXN4 GC61 0.1UF/10V,X7R PEX_TX11 VDD33_2 GC63 GC64 GND_70 GND_167
AK28 PEX_TX11# VDD33_3 J12 AN34 GND_71 GND_168 U21
PM VDD33_4 J13 AP12 GND_72 GND_169 U22
PEG_RXP4 PM AR28 J9 0.1uF/10V,X7R AP15 U23
PEG_RXN4 PEX_RX11 VDD33_5 0.1uF/10V,X7R GND_73 GND_170
AR29 PEX_RX11# AP18 GND_74 GND_171 U24
PM PM S46 VerA:Delete some caps AP21 U25
PEG_TXP3 GC67 0.1UF/10V,X7R GND_75 GND_172
AK29 PEX_TX12 VDD_SENSE1 D35 followed N10M DG 090327 AP24 GND_76 GND_173 V12
PEG_TXN3 GC68 0.1UF/10V,X7R AL29 P7 AP27 V14
B PEX_TX12# VDD_SENSE2 GND_77 GND_174 B
PM VDD_SENSE3 AD20 NVVDD_SENSE {50} AP3 GND_78 GND_175 V16
PEG_RXP3 PM AP29 AD19 +V1.05GPU AP30 V18
PEG_RXN3 PEX_RX12 GND_SENSE1 R57 0 R0402 GND_79 GND_176
AN29 PEX_RX12# GND_SENSE2 R7 AP33 GND_80 GND_177 V2
GND_SENSE3 E35 PM AP6 GND_081 GND_178 V20
PEG_TXP2
PEG_TXN2
GC69 0.1UF/10V,X7R
GC70 0.1UF/10V,X7R
AM29 PEX_TX13 Near GPU GFB1 AP9 GND_082 GND_179 V22
AM30 PEX_TX13# 1 2 FB0603 B12 GND_083 GND_180 V24
PM MAX:120mA 120ohm@100MHz,500mA B15 V31
PEG_RXP2 GC71 GC72 GC73 GND_084 GND_181
PM AN31 PEX_RX13 PEX_PLLVDD AG14 B21 GND_085 GND_182 V5
PEG_RXN2 AP31 C0805 PM C0805 B24 V9
PEX_RX13# 1uF/10V,X7R 4.7uF/10V,X5R 4.7uF/10V,X5R GND_086 GND_183
B27 GND_087 GND_184 Y11
PEG_TXP1 GC74 0.1UF/10V,X7R AM31 C0603 B3 Y13
PEG_TXN1 GC75 0.1UF/10V,X7R PEX_TX14 PM PM PM GND_088 GND_185
AM32 PEX_TX14# B30 GND_089 GND_186 Y15
PM AG20 T2 ns B33 Y17
PEG_RXP1 PEX_CAL_PU_GND/NC GND_090 GND_187
PM AR31 PEX_RX14 B6 GND_091 GND_188 Y19
PEG_RXN1 AR32 AG21 GR5 2.49K,1% R0402 PM B9 Y21
PEX_RX14# PEX_TERMP GND_092 GND_189
C2 GND_093 GND_190 Y23
PEG_TXP0 GC76 0.1UF/10V,X7R AN32 AP35 GR6 10K R0402 +V3.3GPU C34 Y25
PEG_TXN0 GC77 0.1UF/10V,X7R PEX_TX15 TESTMODE ns GND_094 GND_191
AP32 E12
PM
PEX_TX15# Layout Notice GND_095
PEG_RXP0 PM AR34 GR7 10K R0402
PEG_RXN0 PEX_RX15 PM
AP34 PEX_RX15# Under GPU: NB10_G128
PM
The total trace length measured from GPU ball to cap is no more than 150 mil
NB10_G128 S46 VerA:Add reserved pull up resistor
Near GPU:
CLOSE on TESTMODE follewed nvidia suggest
The total trace length measured from GPU ball to cap is no more than 750 mil
PM
TO N11

VerA: all PCIE singala lane reversal llh0523

A A

TOPSTAR TECHNOLOGY
Joseph
Page Name N11M PCIE&PWR&GND
Size Project Name Rev
D C49
A
Date: Friday, May 07, 2010 Sheet 17 of 59
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5 4 3 2 1
 5 4 3 2 1

+V1.05GPU {17,19,20,55}

+V1.5GPU {19,55}

+V1.5GPU
U3B

FBAD_0
MAX:5700mA Under GPU Near GPU +V1.5GPU
L32 FBA_D0 FBVDDQ0 J23
FBAD_1 N33 FPA J24 +V1.5GPU
FBAD_2 FBA_D1 FBVDDQ1
L33 FBA_D2 FBVDDQ2 J29 U21
FBAD_3 N34 AA27 GC86 GC80 GC81
FBAD_4 FBA_D3 FBVDDQ3 GC82 FBA_A0 U22
N35 FBA_D4 FBVDDQ4 AA29 A1 VDDQ0 A0 N3
FBAD_5 P35 AA31 0.1uF/10V,X7R
0.047uF/16V,X7R 0.1uF/10V,X7R 4.7uF/10V,X5R C1 P7 FBA_A1 A1 N3 FBA_A0
FBAD_6 FBA_D5 FBVDDQ5 VDDQ1 A1 FBA_A2 VDDQ0 A0 FBA_A1
P33 FBA_D6 FBVDDQ6 AB27 F1 VDDQ2 A2 P3 C1 VDDQ1 A1 P7
FBAD_7 P34 AB29 D2 N2 FBA_A3 F1 P3 FBA_A2
FBAD_8 FBA_D7 FBVDDQ7 PM PM PM PM VDDQ3 A3 FBA_A4 VDDQ2 A2 FBA_A3
K35 FBA_D8 FBVDDQ8 AC27 H2 VDDQ4 A4 P8 D2 VDDQ3 A3 N2
FBAD_9 K33 AD27 A8 P2 FBA_A5 H2 P8 FBA_A4
FBAD_10 FBA_D9 FBVDDQ9 VDDQ5 A5 FBA_A6 VDDQ4 A4 FBA_A5
K34 FBA_D10 FBVDDQ10 AE27 C9 VDDQ6 A6 R8 A8 VDDQ5 A5 P2
FBAD_11 H33 AJ28 E9 R2 FBA_A7 C9 R8 FBA_A6
FBAD_12 FBA_D11 FBVDDQ11 VDDQ7 A7 FBA_A8 VDDQ6 A6 FBA_A7
G34 FBA_D12 FBVDDQ12 B18 H9 VDDQ8 A8 T8 E9 VDDQ7 A7 R2
FBAD_13 G33 E21 R3 FBA_A9 H9 T8 FBA_A8
D FBAD_14 FBA_D13 FBVDDQ13 A9 FBA_A10 VDDQ8 A8 FBA_A9 D
E34 FBA_D14 FBVDDQ14 G17 N1 VDD1 A10 L7 A9 R3
FBAD_15 E33 G18 R1 R7 FBA_A11 N1 L7 FBA_A10
FBAD_16 FBA_D15 FBVDDQ15 GC79 GC84 GC78 GC85 VDD2 A11 FBA_A12 VDD1 A10 FBA_A11
G31 FBA_D16 FBVDDQ16 G22 B2 VDD3 A12 N7 R1 VDD2 A11 R7
FBAD_17 F30 G8 0.1uF/10V,X7R
0.047uF/16V,X7R 0.1uF/10V,X7R 4.7uF/10V,X5R K2 T3 FBA_A13 B2 N7 FBA_A12
FBAD_18 FBA_D17 FBVDDQ17 VDD4 A13 VDD3 A12 FBA_A13
G30 FBA_D18 FBVDDQ18 G9 G7 VDD5 A14 T7 K2 VDD4 A13 T3
FBAD_19 G32 H29 K8 M7 G7 T7
FBAD_20 FBA_D19 FBVDDQ19 PM PM PM PM VDD6 A15/BA3 VDD5 A14
K30 FBA_D20 FBVDDQ20 J14 D9 VDD7 K8 VDD6 A15/BA3 M7
FBAD_21 K32 J15 N9 D9
FBAD_22 FBA_D21 FBVDDQ21 VDD8 FBA_ODT0 VDD7
H30 FBA_D22 FBVDDQ22 J16 R9 VDD9 ODT0 K1 N9 VDD8
FBAD_23 K31 J17 J1 R9 K1 FBA_ODT0
FBAD_24 FBA_D23 FBVDDQ23 ODT1 +V1.5GPU VDD9 ODT0
L31 FBA_D24 FBVDDQ24 J20 ODT1 J1
FBAD_25 L30 J21 B1 L2 FBA_CS0#
FBAD_26 FBA_D25 FBVDDQ25 VSSQ0 CS0# FBA_CS0#
M32 FBA_D26 FBVDDQ26 J22 D1 VSSQ1 CS1# L1 B1 VSSQ0 CS0# L2
FBAD_27 N30 G1 D1 L1
FBAD_28 FBA_D27 VSSQ2 FBA_BA0 FBB_CKE VSSQ1 CS1#
M30 FBA_D28 E2 VSSQ3 BA0 M2 G1 VSSQ2
FBAD_29 P31 D8 N8 FBA_BA1 E2 M2 FBA_BA0
FBAD_30 FBA_D29 VSSQ4 BA1 FBA_BA2 FBA_CKE GR16 VSSQ3 BA0 FBA_BA1
R32 FBA_D30 E8 VSSQ5 BA2 M3 D8 VSSQ4 BA1 N8
FBAD_31 R30 B9 FBA_RST 1K,1% E8 M3 FBA_BA2
FBAD_32 FBA_D31 FBA_A4 VSSQ6 FBA_RST PM VSSQ5 BA2
AG30 FBA_D32 FBA_CMD0 V32 F9 VSSQ7 RESET# T2 B9 VSSQ6
FBAD_33 AG32 W31 FBA_RAS# G9 F9 T2 FBA_RST
FBAD_34 FBA_D33 FBA_CMD1 FBA_A5 VSSQ8 FBA_RAS# GR17 GR18 GR19 VSSQ7 RESET#
AH31 FBA_D34 FBA_CMD2 U31 RAS# J3 G9 VSSQ8
FBAD_35 AF31 Y32 FBA_BA1 E1 K3 FBA_CAS# 10K 10K 10K FBB_VREF2 J3 FBA_RAS#
FBAD_36 FBA_D35 FBA_CMD3 FBB_A2 VSS0 CAS# FBA_WE# PM PM PM RAS# FBA_CAS#
AF30 FBA_D36 FBA_CMD4 AB35 M1 VSS1 WE# L3 E1 VSS0 CAS# K3
FBAD_37 AE30 AB34 FBB_A4 P1 GC91 M1 L3 FBA_WE#
FBAD_38 FBA_D37 FBA_CMD5 FBB_A3 VSS2 FBADQM_0 GR20 0.01uF/16V,X7R VSS1 WE#
AC32 FBA_D38 FBA_CMD6 W35 T1 VSS3 DMU D3 P1 VSS2
FBAD_39 AD30 W33 FBB_CKE J2 E7 FBADQM_3 1K,1% PM T1 D3 FBADQM_1
FBAD_40 FBA_D39 FBA_CMD7 FBB_CS# VSS4 DML PM VSS3 DMU FBADQM_2
AN33 FBA_D40 FBA_CMD8 W30 B3 VSS5 J2 VSS4 DML E7
FBAD_41 AL31 T34 FBA_A11 G8 J7 FBA_CLK0 B3
FBAD_42 FBA_D41 FBA_CMD9 FBA_CAS# VSS6 CK FBA_CLK0# VSS5 FBA_CLK0
AM33 FBA_D42 FBA_CMD10 T35 J8 VSS7 CK# K7 G8 VSS6 CK J7
FBAD_43 AL33 AB31 FBA_WE# A9 J8 K7 FBA_CLK0#
FBAD_44 FBA_D43 FBA_CMD11 FBA_BA0 VSS8 FBA_CKE +V1.5GPU VSS7 CK#
AK30 FBA_D44 FBA_CMD12 Y30 M9 VSS9 CKE0 K9 A9 VSS8
FBAD_45 AK32 Y34 FBB_A5 P9 J9 M9 K9 FBA_CKE
FBAD_46 FBA_D45 FBA_CMD13 FBA_A12 VSS10 CKE1 VSS9 CKE0
AJ30 FBA_D46 FBA_CMD14 W32 T9 VSS11 P9 VSS10 CKE1 J9
FBAD_47 AH30 AA30 FBA_RST T9
FBAD_48 FBA_D47 FBA_CMD15 FBA_A7 FBB_VREF1 VSS11
AH33 FBA_D48 FBA_CMD16 AA32 H1 VREFDQ ZQ0 L8
FBAD_49 AH35 Y33 FBA_A10 M8 L9 GR12 FBB_VREF2 H1 L8
FBAD_50 FBA_D49 FBA_CMD17 FBA_CKE VREFCA ZQ1 1K,1% VREFDQ ZQ0
AH34 FBA_D50 FBA_CMD18 U32 M8 VREFCA ZQ1 L9
FBAD_51 AH32 Y31 FBA_A0 PM
FBAD_52 FBA_D51 FBA_CMD19 FBA_A9 FBAD_6 FBAD_25 GR61
AJ33 FBA_D52 FBA_CMD20 U34 D7 DQU0 DQL0 E3
FBAD_53 AL35 Y35 FBA_A6 FBAD_1 C3 F7 FBAD_27 243,1% FBAD_13 D7 E3 FBAD_23 GR62
FBAD_54 FBA_D53 FBA_CMD21 FBA_A2 FBAD_7 DQU1 DQL1 FBAD_28 PM FBB_VREF1 FBAD_11 DQU0 DQL0 FBAD_19 243,1%
AM34 FBA_D54 FBA_CMD22 W34 C8 DQU2 DQL2 F2 C3 DQU1 DQL1 F7
FBAD_55 AM35 V30 FBA_A8 FBAD_4 C2 F8 FBAD_29 FBAD_14 C8 F2 FBAD_20 PM
FBAD_56 FBA_D55 FBA_CMD23 FBA_A3 FBAD_3 DQU3 DQL3 FBAD_26 GC88 FBAD_8 DQU2 DQL2 FBAD_16
AF33 FBA_D56 FBA_CMD24 U35 A7 DQU4 DQL4 H3 C2 DQU3 DQL3 F8
FBAD_57 AE32 U30 FBA_A1 FBAD_0 A2 H8 FBAD_30 GR13 0.01uF/16V,X7R FBAD_12 A7 H3 FBAD_22
FBAD_58 FBA_D57 FBA_CMD25 FBA_A13 FBAD_5 DQU5 DQL5 FBAD_24 1K,1% PM FBAD_10 DQU4 DQL4 FBAD_17
AF34 FBA_D58 FBA_CMD26 U33 B8 DQU6 DQL6 G2 A2 DQU5 DQL5 H8
FBAD_59 AE35 AB30 FBA_BA2 FBAD_2 A3 H7 FBAD_31 待确定 PM FBAD_15 B8 G2 FBAD_21
FBAD_60 FBA_D59 FBA_CMD27 FBB_ODT0 FBADQS_0# DQU7 DQL7 FBADQS_3# FBAD_9 DQU6 DQL6 FBAD_18 待确定
AE34 FBA_D60 FBA_CMD28 AB33 B7 DQSU# DQSL# G3 A3 DQU7 DQL7 H7
FBAD_61 AE33 T33 FBA_CS0# FBADQS_0 C7 F3 FBADQS_3 FBADQS_1# B7 G3 FBADQS_2#
FBAD_62 FBA_D61 FBA_CMD29/NC FBA_ODT0 DQSU DQSL FBADQS_1 DQSU# DQSL# FBADQS_2
AB32 FBA_D62 FBA_CMD30/NC W29 C7 DQSU DQSL F3
FBAD_63 AC35
C FBA_D63 DDR3 C
PM DDR3
FBADQM_0 P32 PM
FBADQM_1 FBA_DQM0 FBA_CLK0
H34 FBA_DQM1 FBA_CLK0 T32
FBADQM_2 J30 T31 FBA_CLK0#
FBADQM_3 FBA_DQM2 FBA_CLK0# +V1.5GPU
P30 FBA_DQM3 FBA_CLK1 AC31 FBA_CLK1
FBADQM_4 AF32 AC30 FBA_CLK1#
FBADQM_5 FBA_DQM4 FBA_CLK1# +V1.5GPU
AL32 FBA_DQM5 U23
FBADQM_6 AL34
FBADQM_7 FBA_DQM6 FBA_A0
AF35 FBA_DQM7 A1 VDDQ0 A0 N3 U24
C1 P7 FBA_A1
VDDQ1 A1 FBB_A2 FBA_A0
F1 VDDQ2 A2 P3 A1 VDDQ0 A0 N3
FBADQS_0 L34 D2 N2 FBB_A3 C1 P7 FBA_A1
FBADQS_1 FBA_DQS_WP0 VDDQ3 A3 FBB_A4 VDDQ1 A1 FBB_A2
H35 FBA_DQS_WP1 H2 VDDQ4 A4 P8 F1 VDDQ2 A2 P3
FBADQS_2 J32 T30 T132 ns A8 P2 FBB_A5 D2 N2 FBB_A3
FBADQS_3 FBA_DQS_WP2 FBA_DEBUG VDDQ5 A5 FBA_A6 VDDQ3 A3 FBB_A4
N31 FBA_DQS_WP3 C9 VDDQ6 A6 R8 H2 VDDQ4 A4 P8
FBADQS_4 AE31 E9 R2 FBA_A7 A8 P2 FBB_A5
FBADQS_5 FBA_DQS_WP4 +V1.05GPU VDDQ7 A7 FBA_A8 VDDQ5 A5 FBA_A6
AJ32 FBA_DQS_WP5 H9 VDDQ8 A8 T8 C9 VDDQ6 A6 R8
FBADQS_6 AJ34 GFB2 R3 FBA_A9 E9 R2 FBA_A7
FBA_DQS_WP6 A9 VDDQ7 A7
FBADQS_7 AC33 FBA_DQS_WP7 MAX:100mA Near GPU 120ohm@100MHz,500mA N1 VDD1 A10 L7 FBA_A10
FBA_A11 +V1.5GPU +V1.5GPU
H9 VDDQ8 A8 T8 FBA_A8
FBA_A9
1 2 R1 VDD2 A11 R7 A9 R3
PM FB0603 B2 N7 FBA_A12 N1 L7 FBA_A10
FBADQS_0# GC89 GC90 VDD3 A12 FBA_A13 VDD1 A10 FBA_A11
L35 FBA_DQS_RN0 K2 VDD4 A13 T3 R1 VDD2 A11 R7
FBADQS_1# G35 G7 T7 B2 N7 FBA_A12
FBADQS_2# H31 FBA_DQS_RN1 1uF/10V,X5R 4.7uF/10V,X5R VDD5 A14 VDD3 A12 FBA_A13
FBA_DQS_RN2 K8 VDD6 A15/BA3 M7 K2 VDD4 A13 T3
FBADQS_3# N32 AG27 C0805 D9 G7 T7
FBADQS_4# AD32 FBA_DQS_RN3 FB_DLLAVDD0 PM PM VDD7 GR64 GR66 VDD5 A14
FBA_DQS_RN4 N9 VDD8 K8 VDD6 A15/BA3 M7
FBADQS_5# AJ31 AF27 R9 K1 FBB_ODT0 1K,1% 1K,1% D9
FBADQS_6# AJ35 FBA_DQS_RN5 FB_PLLAVDD0 VDD9 ODT0 PM PM VDD7
FBA_DQS_RN6 ODT1 J1 N9 VDD8
FBADQS_7# AC34 R9 K1 FBB_ODT0
FBA_DQS_RN7 FBB_CS# VDD9 ODT0
B1 VSSQ0 CS0# L2 ODT1 J1
P29 D1 L1 FBB_VREF3 FBB_VREF4
+V1.5GPU FBA_WDS0/NC VSSQ1 CS1# FBB_CS#
R29 FBA_WDS0#/NC G1 VSSQ2 B1 VSSQ0 CS0# L2
L29 E2 M2 FBA_BA0 GC176 GC177 D1 L1
FBA_WDS1/NC VSSQ3 BA0 FBA_BA1 GR69 0.01uF/16V,X7R GR70 0.01uF/16V,X7R VSSQ1 CS1#
M29 FBA_WDS1#/NC D8 VSSQ4 BA1 N8 G1 VSSQ2
AG29 E8 M3 FBA_BA2 1K,1% PM 1K,1% PM E2 M2 FBA_BA0
FBA_WDS2/NC VSSQ5 BA2 PM PM VSSQ3 BA0 FBA_BA1
AH29 FBA_WDS2#/NC B9 VSSQ6 D8 VSSQ4 BA1 N8
GR21 AD29 F9 T2 FBA_RST E8 M3 FBA_BA2
1K,1% FBA_WDS3/NC VSSQ7 RESET# VSSQ5 BA2
AE29 FBA_WDS3#/NC G9 VSSQ8 B9 VSSQ6
ns J3 FBA_RAS# F9 T2 FBA_RST
RAS# FBA_CAS# VSSQ7 RESET#
E1 VSS0 CAS# K3 G9 VSSQ8
J27 M1 L3 FBA_WE# J3 FBA_RAS#
FB_VREF VSS1 WE# RAS# FBA_CAS#
P1 VSS2 E1 VSS0 CAS# K3
NB10_G128 T1 D3 FBADQM_7 M1 L3 FBA_WE#
PM VSS3 DMU FBADQM_4 VSS1 WE#
J2 VSS4 DML E7 P1 VSS2
GR22 GC92 B3 T1 D3 FBADQM_6
2.49K,1% 0.01uF/16V,X7R VSS5 FBA_CLK1 VSS3 DMU FBADQM_5
G8 VSS6 CK J7 J2 VSS4 DML E7
ns ns J8 K7 FBA_CLK1# B3
VSS7 CK# VSS5 FBA_CLK1
A9 VSS8 G8 VSS6 CK J7
+V1.5GPU M9 K9 FBB_CKE J8 K7 FBA_CLK1#
B VSS9 CKE0 VSS7 CK# B
P9 VSS10 CKE1 J9 A9 VSS8
T9 M9 K9 FBB_CKE
VSS11 VSS9 CKE0
P9 VSS10 CKE1 J9
H1 VREFDQ ZQ0 L8 T9 VSS11
FBB_VREF3 M8 L9
GC101 GC102 GC103 GC104 GC105 GC106 GC107 VREFCA ZQ1
H1 VREFDQ ZQ0 L8
C0603 C0603 C0805 FBB_VREF4 M8 L9
1000pF/25V,X7R 1000pF/25V,X7R 0.01uF/16V,X7R 0.1uF/10V,X7R 1uF/10V,X7R 1uF/10V,X7R 4.7uF/10V,X5R FBAD_60 FBAD_32 GR67 VREFCA ZQ1
D7 DQU0 DQL0 E3
FBAD_59 C3 F7 FBAD_36 243,1%
PM PM PM PM PM PM PM FBAD_61 DQU1 DQL1 FBAD_33 PM FBAD_48 FBAD_47 GR68
C8 DQU2 DQL2 F2 D7 DQU0 DQL0 E3
FBAD_56 C2 F8 FBAD_37 FBAD_52 C3 F7 FBAD_43 243,1%
+V1.5GPU FBAD_63 DQU3 DQL3 FBAD_35 FBAD_50 DQU1 DQL1 FBAD_46 PM
A7 DQU4 DQL4 H3 C8 DQU2 DQL2 F2
FBAD_58 A2 H8 FBAD_39 FBAD_54 C2 F8 FBAD_41
FBAD_62 DQU5 DQL5 FBAD_34 FBAD_51 DQU3 DQL3 FBAD_45
B8 DQU6 DQL6 G2 A7 DQU4 DQL4 H3
FBAD_57 A3 H7 FBAD_38 待确定 FBAD_55 A2 H8 FBAD_42
GC108 GC109 GC110 GC111 GC112 GC113 GC114 FBADQS_7# DQU7 DQL7 FBADQS_4# FBAD_49 DQU5 DQL5 FBAD_44
B7 DQSU# DQSL# G3 B8 DQU6 DQL6 G2
C0603 C0603 C0805 FBADQS_7 C7 F3 FBADQS_4 FBAD_53 A3 H7 FBAD_40 待确定
1000pF/25V,X7R 1000pF/25V,X7R 0.01uF/16V,X7R 0.1uF/10V,X7R 1uF/10V,X7R 1uF/10V,X7R 4.7uF/10V,X5R DQSU DQSL FBADQS_6# DQU7 DQL7 FBADQS_5#
B7 DQSU# DQSL# G3
FBADQS_6 C7 F3 FBADQS_5
DDR3 DQSU DQSL
PM PM PM PM PM PM PM PM
DDR3
PM
+V1.5GPU

GC115 GC116 GC117 GC118 GC119 GC120 GC121

1000pF/25V,X7R 1000pF/25V,X7R 0.01uF/16V,X7R 0.1uF/10V,X7R 1uF/10V,X7R 1uF/10V,X7R 4.7uF/10V,X5R
C0603 C0603 C0805

PM PM PM PM PM PM PM
FBA_ODT0 FBB_ODT0

GR14 GR15
10K 10K +V1.5GPU
PM PM

GC93 GC94 GC95 GC96 GC97 GC98 GC99

A FBA_CLK0 FBA_CLK1 + 150UF/2.5V GC100 A
CT7343_28 1000pF/25V,X7R 1000pF/25V,X7R 0.01uF/16V,X7R 0.1uF/10V,X7R 1uF/10V,X7R 1uF/10V,X7R 4.7uF/10V,X5R
C0603 C0603 C0805

ns PM PM PM PM PM PM PM
GR234 GR235
243,1% 243,1%
PM PM

FBA_CLK0# FBA_CLK1#
TOPSTAR TECHNOLOGY
Joseph
Page Name N11M memory1
Size Project Name Rev
D C49
A
Date: Friday, May 07, 2010 Sheet 18 of 59
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5 4 3 2 1
 5 4 3 2 1

+V1.5GPU
U3C
+V1.05GPU {17,18,20,55}
B13 FBC_D0 Under GPU Near GPU
D13 FBC_D1 FBVDDQ27 N27 +V1.5GPU {18,55}
A13 FBC_D2
FPC
FBVDDQ28 P27
A14 FBC_D3 FBVDDQ29 R27
C16 T27 GC123 GC124
FBC_D4 FBVDDQ30 GC122 GC125
B16 FBC_D5 FBVDDQ31 U27
A17 U29 0.01uF/25V,X7R 0.047uF/16V,X7R 0.1uF/10V,X7R 4.7uF/10V,X5R
FBC_D6 FBVDDQ32
D16 FBC_D7 FBVDDQ33 V27
C13 FBC_D8 FBVDDQ34 V29
B11 V34 PM PM PM PM
FBC_D9 FBVDDQ35
D C11 FBC_D10 FBVDDQ36 W27 D
A11 FBC_D11 FBVDDQ37 Y27
C10 FBC_D12
C8 FBC_D13
B8 FBC_D14
A8 FBC_D15
E8 FBC_D16
F8 GC126 GC127 GC128 GC129
FBC_D17 0.01uF/25V,X7R 0.047uF/16V,X7R 0.1uF/10V,X7R 4.7uF/10V,X5R
F10 FBC_D18
F9 FBC_D19
F12 FBC_D20
D8 PM PM PM PM
FBC_D21
D11 FBC_D22
E11 FBC_D23
D12 FBC_D24 FBC_CMD0 C17
E13 FBC_D25 FBC_CMD1 B19
F13 FBC_D26 FBC_CMD2 D18
F14 FBC_D27 FBC_CMD3 F21
F15 FBC_D28 FBC_CMD4 A23
E16 FBC_D29 FBC_CMD5 D21
F16 FBC_D30 FBC_CMD6 B23
F17 FBC_D31 FBC_CMD7 E20
D29 FBC_D32 FBC_CMD8 G21
F27 FBC_D33 FBC_CMD9 F20
F28 FBC_D34 FBC_CMD10 F19
E28 FBC_D35 FBC_CMD11 F23
D26 FBC_D36 FBC_CMD12 A22
F25 FBC_D37 FBC_CMD13 C22
D24 FBC_D38 FBC_CMD14 B17
C E25 F24 C
FBC_D39 FBC_CMD15
E32 FBC_D40 FBC_CMD16 C25
F32 FBC_D41 FBC_CMD17 E22
D33 FBC_D42 FBC_CMD18 C20
E31 FBC_D43 FBC_CMD19 B22
C33 FBC_D44 FBC_CMD20 A19
F29 FBC_D45 FBC_CMD21 D22
D30 FBC_D46 FBC_CMD22 D20
E29 FBC_D47 FBC_CMD23 E19
B29 FBC_D48 FBC_CMD24 D19
C31 FBC_D49 FBC_CMD25 F18
C29 FBC_D50 FBC_CMD26 C19
B31 FBC_D51 FBC_CMD27 F22
C32 FBC_D52 FBC_CMD28 C23
B32 FBC_D53 FBC_CMD29/NC B20
B35 FBC_D54 FBC_CMD30/NC A20
B34 FBC_D55
A29 FBC_D56
B28 FBC_D57
A28 FBC_D58
C28 FBC_D59
C26 FBC_D60
D25 FBC_D61
B25 FBC_D62
A25 FBC_D63

A16 FBC_DQM0 FBC_CLK0 E17

D10 FBC_DQM1 FBC_CLK0# D17
B B
F11 FBC_DQM2 FBC_CLK1 D23
D15 FBC_DQM3 FBC_CLK1# E23
D27 FBC_DQM4
D34 +V1.05GPU
FBC_DQM5 GFB3
A34 FBC_DQM6
D28 120ohm@100MHz,500mA
FBC_DQM7 +V1.5GPU MAX:35mA 1 2
FB0603
C14 GC130 GC131 GC132 ns
FBC_DQS_WP0
A10 FBC_DQS_WP1 FBC_DEBUG G19 GR23 60.4,1% 0.1uF/10V,X7R C0805
E10 R0402 0.1uF/10V,X7R ns 10UF/6.3V,X5R
FBC_DQS_WP2 ns ns ns
D14 FBC_DQS_WP3
E26 FBC_DQS_WP4
D32 FBC_DQS_WP5
A32 FBC_DQS_WP6 FB_DLLAVDD1 J19
B26 FBC_DQS_WP7 FB_PLLAVDD1 J18

B14 FBC_DQS_RN0
B10 +V1.5GPU
FBC_DQS_RN1
D9 FBC_DQS_RN2
E14 FBC_DQS_RN3
Place close to balls
F26 FBC_DQS_RN4 FBCAL_PD_VDDQ K27 GR34 40.2,1%
D31 PM R0402
FBC_DQS_RN5
A31 FBC_DQS_RN6
A26 FBC_DQS_RN7 FBCAL_PU_GND L27 GR35 40.2,1%
PM R0402

G14 M27 GR26 40.2,1% 40.2 in DG

A FBC_WDS0/NC FBCAL_TERM_GND A
G15 PM R0402 TOPSTAR TECHNOLOGY
FBC_WDS0#/NC
G11 FBC_WDS1/NC
G12 Joseph
FBC_WDS1#/NC
G27 Page Name N11M memory2
FBC_WDS2/NC
G28 FBC_WDS2#/NC
G24 Size Project Name Rev
FBC_WDS3/NC A3 C49
G25 FBC_WDS3#/NC A
Date: Friday, May 07, 2010 Sheet 19 of 59
NB10_G128 PROPERTY NOTE: this document contains information confidential and property to
PM TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5 4 3 2 1
 5 4 3 2 1

+V3.3GPU {17,21,36,38,55}
+V1.05GPU {17,18,19,55}
+V1.8GPU {55}
+V3.3GPU

R60 R61 R62

4.99K,1% 15K,1% 2.2K
R0402 R0402 R0402 +V3.3GPU GU4
ns PM ns ROM_SI_GPU ROM_SO_GPU U3D
5 D Q 2
1K is not-stuffed in DG V02
D ROM_SI_GPU ROM_SCLK_GPU 6 AK9 IFPAB_PLLVDD D
C IFPAB_PLLVDD R63 1K,1% ns
IFPAB_RSET AJ11 MAX:220 mA
ROM_SCLK_GPU GR27 10K ROM_CS#_GPU 1 R0402 IFPAB_PLLVDD 1 2 +V1.05GPU
PM S ns T8 IFPAB_IOVDD GFB4
J26 NC_19 IFPA_IOVDD AG9
ROM_SO_GPU 7 +V3.3GPU ns T9 J25 AG10 PM FB0603
HOLD NC_20 IFPB_IOVDD GC133 GC134 120ohm@100MHz,500mA
GR29 10K 3 R70 10K R0402 AB5 AM12 1uF/10V,X5R C0805
PM W CEC IFPA_TXC# GPU_LVDS_CLKAM {16} C0402 4.7uF/10V,X5R
IFPA_TXC AM11 GPU_LVDS_CLKAP {16}
R64 R65 R66 8 4 PM
10K,1% 15K,1% 15K,1% VCC VSS
D7 RFU1 IFPA_TXD0# AL8 GPU_LVDS_YAM0 {16}
PM R0402 R0402 GR28 PM25LV010A R67 ns D6 AM8 PM PM +V1.8GPU
RFU2 IFPA_TXD0 GPU_LVDS_YAP0 {16}
ns PM 10K ns 10K R0402 C7
ns GC135 RFU3 MISC
B7 RFU4 IFPA_TXD1# AM9 GPU_LVDS_YAM1 {16} MAX:220 mA
0.1UF/10V,X7R A7 AM10 IFPAB_IOVDD 2 1 GFB5
RFU5 IFPA_TXD1 GPU_LVDS_YAP1 {16}
Rom_SI: -Hynix 32Mx32 (pull-down 15K) PM IFPAB FB0603
-Samsung 32MX32 (pull-down 20K) PM AL10 GC136 GC137 120ohm@100MHz,500mA GC140
IFPA_TXD2# GPU_LVDS_YAM2 {16}
AK10 GC138 GC139 PM C0805
IFPA_TXD2 GPU_LVDS_YAP2 {16} 0.1uF/10V,X7R 0.1uF/10V,X7R
R68 40.2K,1% N9 1uF/10V,X5R C0805 4.7uF/10V,X5R
MULTI_STRAP_REFO_GND
Change R61 from 15k to 35k to R0402
IFPA_TXD3# AL11 R71 100,1%ns C0402 C0402 C0402 4.7uF/10V,X5R
enable external VBIOS ROM R69
R0402
40.2K,1% M9 MULTI_STRAP_REF1_GND IFPA_TXD3 AK11 Under GPU Near GPU PM
PM PM PM PM
PM
IFPB_TXC# AN13
ROM_CS#_GPU C3 AP13
ROM_SI_GPU ROM_CS# IFPB_TXC +V3.3GPU
D3 ROM_SI
ROM_SO_GPU C4 AP8
ROM_SCLK_GPU ROM_SO IFPB_TXD4# GFB6
D4 ROM_SCLK IFPB_TXD4 AN8 MAX:220 mA
IFPCD_PLLVDD 1 2
AN10 120ohm@100MHz,500mA
ns T39 IFPB_TXD5# FB0603
F6 I2CH_SCL IFPB_TXD5 AP10
GC142 GC143 GC144 GC145 GC146 PM/HDMI
ns T40 G6 AR10 0.1uF/10V,X7R 0.1uF/10V,X7R 0.1uF/10V,X7R 1uF/10V,X5R C0805
+V1.05GPU I2CH_SDA IFPB_TXD6# C0402 C0402 C0402 C0402 4.7uF/10V,X5R
C IFPB_TXD6 AR11 C
PM/HDMI PM/HDMI PM/HDMI PM/HDMI PM/HDMI
FB4 120ohm@100MHz,500mA MAX:60+45 mA ns T10 A5 AP11 R73 100,1%ns +V1.05GPU
PLLVDD SPDIF IFPB_TXD7#
1 2 IFPB_TXD7 AN11 MAX:285 mA
PM FB0603 IFPCD_IOVDD 1 2 GFB7
ns T11 A4 FB0603
GC147 GC148 GC149 GC150 BUFRST# GC153 120ohm@100MHz,500mA
C0805 1uF/10V,X5R 0.1UF/10V,X7R 0.1UF/10V,X7R ns T12 C5 AJ9 IFPCD_PLLVDD GC151 GC152 GC154 C0805 PM/HDMI
4.7uF/10V,X5R C0402 RFU IFPC_PLLVDD R75 1K,1% 0.1uF/10V,X7R 0.1uF/10V,X7R 1uF/10V,X5R 4.7uF/10V,X5R
IFPC_RSET AK7
PM PM PM AJ8 PM/HDMI C0402 C0402 C0402 PM/HDMI
IFPC_IOVDD
Near GPU Under GPU PM AK14 GND_192 IFPD_IOVDD AK8 IFPCD_IOVDD PM/HDMI PM/HDMI PM/HDMI
R76 0 K9 GND_193 IFPD_PLLVDD AC6 IFPCD_PLLVDD Under GPU Near GPU
R0402 ns AB6 R77 1K,1%
IFPD_RSET PM/HDMI
+V1.05GPU
PLLVDD AE9 AN3 R78 33 R0402 PM/HDMI HDMI_DDC_DATA {36}
FB5 120ohm@100MHz,500mA MAX:45mA PLLVDD IFPC_AUX# R79 33 R0402 PM/HDMI
AD9 VID_PLLVDD IFPC_AUX AP2 HDMI_DDC_CLK {36}
1 2 SP_PLLVDD AF9 SP_PLLVDD

S
4
Pn
6
V
e
r
B
:
Dt
H
M
I
_
D
D
C
Cc
_
Kr
L
a
dt
n

Ai
D
Ak
T

s9
i
w
r
o
n
g
l
y
PM FB0603
GC155 GC156 AR2 IFPC_TXC#_R
PM/HDMI
C158 0.1uF/10V,X7R

l
i
k
,
s
w
a
p
h
e
m
t
o
o
r
e
c
l
n
0
0
6
2
6
IFPC_L3# IFPC_TXC# {36}
C0805 1uF/10V,X5R XTALOUTBUFF_T12 D2 AP1 IFPC_TXC_R
PM/HDMI C159 0.1uF/10V,X7R IFPC_TXC {36}
4.7uF/10V,X5R C0402 GC157 XTAL_SSIN XTAL_PLL IFPC_L3
33 XTALOUTBUFF_T12 +V3.3GPU 0.1UF/10V,X7R
27M_nonSSC_GPU B1 AM4 IFPC_TXD0N_R
PM/HDMI
C160 0.1uF/10V,X7R IFPC_TXD0N {36}
{6} 27M_SSC PMNear XTAL_IN IFPC_L2#
GR226 GPU PM PM
IFPC_L2 AM3 IFPC_TXD0P_R
PM/HDMI C161 0.1uF/10V,X7R IFPC_TXD0P {36}
1

IFPCD
PM
GR227 GFB8 ns T181 D1 AM5 IFPC_TXD1N_R
PM/HDMI
C162 0.1uF/10V,X7R IFPC_TXD1N {36}
10K XTAL_OUTBUFF IFPC_L1#
120ohm@100MHz,500mA IFPC_L1 AL5 IFPC_TXD1P_R
PM/HDMI C163 0.1uF/10V,X7R IFPC_TXD1P {36}
PM PM FB0603 MAX:120mA ns T182 B2 XTAL_OUT
2

IFPC_L0# AM6 IFPC_TXD2N_R

PM/HDMI
C164 0.1uF/10V,X7R IFPC_TXD2N {36}
IFPC_L0 AM7 IFPC_TXD2P_R
PM/HDMI C165 0.1uF/10V,X7R IFPC_TXD2P {36}
GC160 GC161 GC164
4.7UF/10V,X5R 1uF/10V,X5R GC162 GC163 470pF/25V,X7R
C0805 C0402 0.1UF/10V,X7R4700PF/25V,X7R AJ12 AN4
GC165 0.1UF/10V,X7R DACA_VDD IFPD_AUX#
B AK12 DACA_VREF IFPD_AUX AP4 B
PM PM PM PM PM R80 PM AK13 DACA_RSET
{6} 27M_nonSSC
GR228 33 27M_nonSSC_GPU Near GPU Under GPU R0402
PM 124,1%
IFPD_L3# AR4
PM R81 33 R0402 PM G1 AR5
{38} CRT_DDC_CLK I2CA_SCL IFPD_L3
R82 33 R0402 PM G4 IFPC_TXC#_R R83 499,1% PM/HDMI
{38} CRT_DDC_DATA I2CA_SDA
GR236 AP5 IFPC_TXC_R R84 499,1% PM/HDMI
IFPD_L2#

3
10K AN5 IFPC_TXD0N_R R85 499,1% PM/HDMI
DACA IFPD_L2 IFPC_TXD0P_R R86 499,1% PM/HDMI Q3 +V3.3GPU
PM {38} CRT_HSYNC AM13 DACA_HSYNC
AL13 AN7 IFPC_TXD1N_R R87 499,1% PM/HDMI BSS138
{38} CRT_VSYNC DACA_VSYNC IFPD_L1#
AP7 IFPC_TXD1P_R R88 499,1% PM/HDMI SOT23 1 R89
IFPD_L1 IFPC_TXD2N_R R90 499,1% PM/HDMI PM/HDMI PM/HDMI 10K
AM15 AR7 IFPC_TXD2P_R R91 499,1% PM/HDMI
{38} CRT_RED DACA_RED IFPD_L0#

2
{38} CRT_GREEN AM14 DACA_GREEN IFPD_L0 AR8
{38} CRT_BLUE AL14 DACA_BLUE

AG7 R92 10K R0402

DACB_VDD
DACB_VREF AK6
DACB_RSET AH7 PM
+V3.3GPU
TBD
G3 R93 2.2K R0402
150,1% GR38 CRT_RED DACC I2CB_SCL R94 2.2K R0402
I2CB_SDA G2
PM AM1 PM
150,1% GR41 CRT_GREEN DACB_HSYNC
DACB_VSYNC AM2 PM
PM AK4
150,1% GR43 CRT_BLUE DACB_RED
DACB_GREEN AL4
PM AJ4
DACB_BLUE

Place close to balls NB10_G128

PM
A A

TOPSTAR TECHNOLOGY
Joseph
Page Name N11M IO_1
Size Project Name Rev
Custom C49
A
Date: Friday, May 07, 2010 Sheet 20 of 59
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5 4 3 2 1
 5 4 3 2 1

+V3.3GPU {17,20,36,38,55}

ITEM FUNC Action

GPIO0 GPIO no using , PD 10K

GPIO1 HPD-C connect to HDMI conn with level shifter

U3E
GPIO2 Panel backlight brightness reserved associated with EC PWM , then connect to LVDS conn , reserved PD 10K

N1 GPIO3 Panel Power enable , active high connect LCDVDD_ON

R96 10K R0402 MIOA_D0
AJ6 IFPEF_PLLVDD MIOA_D1 P4
PM AL1 P1 GPIO4 Panel backlight On , active high connect LCDVDD backlight on
R95 10K R0402 IFPEF_RSET MIOA_D2
AE7 IFPE_IOVDD MIOA_D3 P2
PM AD7 P3 GPIO5 GPU vid0 Reserved routing to GPU power controller
IFPF_IOVDD MIOA_D4
MIOA_D5 T3
AD4 IFPEF MIOA T2 GPIO6 GPU vid1 Reserved routing to GPU power controller
D IFPE_AUX# MIOA_D6 D
AE4 IFPE_AUX MIOA_D7 T1
GPIO7 GPU vid2 no using , reserved 10K PU V3.3S
MIOA_D8 U4
AE5 IFPE_L3# MIOA_D9 U1
GPIO8 Thermal trip of GPU , active low Connect to Hardware shut down circuit , parallel with CPU thermaltrip , 10K PU V3.3S
AE6 IFPE_L3 MIOA_D10 U2
MIOA_D11 U3
GPIO9 Thermal alert input connect to thermal sensor IC alert with 10K PU V3.3S
AF5 IFPE_L2# MIOA_D12/NC R6
AF4 IFPE_L2 MIOA_D13/NC T6
GPIO10 Memory Vref switch no using , NC
MIOA_D14/NC N6
AG4 IFPE_L1# GPIO11 SLI_SYNC , host GPU output , slave input No using , PD 10K followed DEMO
AH4 IFPE_L1
MIOA_CTL3 P5 GPIO12 PWR_LEVEL no using , 10K PU V3.3S followed DEMO
AH5 IFPE_L0# MIOA_HSYNC N3
AH6 IFPE_L0 MIOA_VSYNC L3 GPIO13 Dynamic NVVDD control 0 no using , NC
MIOA_DE N2
AF2 IFPF_AUX# GPIO14 Dynamic NVVDD control 0 no using , NC
AF3 IFPF_AUX
MIOA_CLKOUT R4 GPIO15 HPD-E no using , PD 10K
AH3 IFPF_L3# MIOA_CLKOUT# T4
AH2 IFPF_L3 GPIO16 FAN_PWM no using , PD 10K
AH1 N4 R97 10K R0402
IFPF_L2# MIOA_CLKIN PM
GPIO17 Reserved no using , PD 10K
AJ1 IFPF_L2
GPIO18 Reserved no using , PD 10K
AJ2 IFPF_L1#
AJ3 IFPF_L1 GPIO19 HPD_D no using , PD 10K
AL3 IFPF_L0# GPIO20 Reserved no using , PD 10K
AL2 IFPF_L0
+V3.3GPU GPIO21 HPD-F no using , PD 10K

AA9 MIOB_VDDQ1 GPIO22 SWAPRDY 10K PU V3.3S

AB9 MIOB_VDDQ2
MIOB
C166
0.1uF/10V,X5R
W9
Y9
MIOB_VDDQ3 THERMDN B4 需要用DDR3的 GPIO23 GPIO no using , NC
C0402 MIOB_VDDQ4
THERMDP B5
PM ns T13 AA7 MIOB_CAL_PD_VDDQ
C ns T14 AA6 C
MIOB_CAL_PU_GND
AP14 ns R98 10K R0402
ns T15 JTAG_TCK ns R99 10K R0402
AF1 MIOB_VREF JTAG_TMS AR14 +V3.3GPU
AN14 ns R100 10K R0402
JTAG_TDI
JTAG_TDO AN16 T16 ns
N10M-GS:0xA74(strap2 pull-down 25K, rom_sclk pull-up 15K) Y1 MIOB_D0 JTAG_TRST# AP16 ns R101 1K R0402 +V3.3GPU
N10M-GE:0xA68(strap2 pull-up 5K, rom_sclk pull-down 15K) Y2 MIOB_D1
Y3 GPU_SM_CLK R102 2.2K R0402
MIOB_D2 GPU_SM_DATA R103 2.2K R0402
AB3 MIOB_D3
AB2 MISC1 ns
+V3.3GPU MIOB_D4
AB1 MIOB_D5 ns
AC4 MIOB_D6
AC1 MIOB_D7
AC2 E2 GPU_SM_CLK
MIOB_D8 I2CS_SCL GPU_SM_DATA
AC3 MIOB_D9 I2CS_SDA E1
R105 R106 R107 AE3 E3 R109 33 R0402
4.99K,1% 34.8K,1% MIOB_D10 I2CC_SCL R110 33 R0402 G_SMB_CLK {16}
45.3K,1% AE2 MIOB_D11 I2CC_SDA E4 G_SMB_DATA {16}
R0402 R0402 R0402 U6 MIOB_D12/NC RFU_1 F4 PMI2CD_SCL_GPU
ns PM PM W6 MIOB_D13/NC RFU_2 G5 PMI2CD_SDA_GPU
Y6 D5 +V3.3GPU
STRAP0_GPU MIOB_D14/NC RFU_3
W5 STRAP0 RFU_4 E5
STRAP1_GPU W7
STRAP2_GPU STRAP1 G_SMB_CLK R111 2.2K R0402 PM
V7 STRAP2 G_SMB_DATA R112 2.2K R0402 PM
W3 I2CD_SCL_GPU R113 2.2K R0402 ns
MIOB_CTL3 I2CD_SDA_GPU R116 2.2K R0402 ns
W1 MIOB_HSYNC
R114 R115 R117 W2 K1 GPIO0_GPU GPU_VID2 R118 10K R0402 ns
30.1K,1% 34.8K,1% 15K,1% MIOB_VSYNC GPIO0 GPU_OVT# R119 10K R0402 PM
Y5 MIOB_DE GPIO1 K2 GPU_HDMI_HPD {36,42}
R0402 R0402 R0402 K3 GPU_LVDS_BKLTCTL SLI_SWAPRDY R120 10K R0402 ns
GPIO2 GPU_LVDS_BKLTCTL {22}
PM ns ns V4 H3
MIOB_CLKOUT GPIO3 GPU_LVDS_VDDEN {16}
W4 H2 PWR_LEVEL R121 10K R0402 ns
MIOB_CLKOUT# GPIO4 GPU_LVDS_BKLTEN
GPIO5 H1 GPU_VID0 {50}
R122 10K R0402 AE1 H4
MIOB_CLKIN GPIO6 GPU_VID1 {50}
PM H5 GPU_VID2
+V3.3GPU GPIO7 GPU_OVT#
GPIO8 H6 GPU_OVT# {42}
S46P VerB:Ns R579,stuff GPIO9 J7 THER_ALERT#
B R562 and change R562 to 35k P9 MIOA_VDDQ1 GPIO10 K4 B
R9 K5 SLI_SYNC GPU_HDMI_HPD R123 10K R0402 ns
followed nvidia PUN 090619 C167 T9
MIOA_VDDQ2 GPIO11
H7 PWR_LEVEL ns R124 33 R0402 GPIO0_GPU R125 10K R0402 PM
MIOA_VDDQ3 GPIO12 AC_IN {42,44}
0.1uF/10V,X5R U9 J4 GPU_LVDS_BKLTCTL R126 10K R0402
C0402 MIOA_VDDQ4 GPIO13 SLI_SYNC R127 10K R0402 ns
GPIO14 J6
PM L1 HPD_E_GPU GPU_LVDS_VDDEN R128 10K R0402 PM
GPIO15 GPU_FAN_PWM HPD_E_GPU R129 10K R0402 ns
GPIO16 L2
L4 GPU_GPIO17 GPU_FAN_PWM R130 10K R0402 ns
ns T17 GPIO17 GPU_GPIO18 GPU_GPIO17 R131 10K R0402 ns
U5 MIOA_CAL_PD_VDDQ GPIO18 M4
ns T18 T5 L7 HPD_D_GPU GPU_GPIO18 R132 10K R0402 ns
MIOA_CAL_PU_GND GPIO19 GPU_GPIO20 HPD_D_GPU R133 10K R0402 ns
GPIO20 L5
K6 HPD_F_GPU GPU_GPIO20 R134 10K R0402 ns
ns T19 GPIO21 SLI_SWAPRDY HPD_F_GPU R135 10K R0402 ns
N5 MIOA_VREF GPIO22 L6
GPIO23 M6

Nvidia advise:
NB10_G128 For used GPIO1,2,3,4,5,6: please use 10K pull-down for initial value.
For used GPIO8,12: please use 10K pull-up for initial value. NOTE:
PM
For the unused GPIO, no need external HW pull-up/down. 1, XCLK_277 set 0 ，using 27MHz clock
2，FB_0_BAR_SIZE 0 system frame buffer 256M
3，PCI_DEVID[4:0] N10M-GS set 0x0A74 PCI_DEVID[4:0] set 10100
+V3.3GPU
4, USER[3:0] set 1111 , using EDID method to detect panel
5, 3GIO_PADCFG[3:0] set 0001 , using NOTEBOOK configuration
6, RAMCFG[3:0] need follow latest PUN
R707 0 R0402 PM R251 7, PEX_PLL_EN_TERM100 set 0 , using PEX PLL termination disable configuration
0 8, SLOT_CLK_CFG set 1 , GPU MCH using the same clk chip
Q33 R0402 9, SUB_VENDOR set 0 , no VIDEO BIOS ROM
PM
C215 10.SMBUS_ALT_ADDR Set 0
2N7002E-T1
PM 11.0 3D Device 1VGA Device(default)
{42} EC_GPU_SML1CLK 3 2 GPU_SM_CLK 0.1UF/25V,Y5V
C0402
ns
+V3.3GPU
U34
1

A 74AHCT1G08GV A
1 VCC SOT23_5
THER_ALERT# 4 GPU_LVDS_BKLTEN_R
R708 0 R0402 GPU_LVDS_BKLTEN GPU_LVDS_BKLTEN_R {16}
2
PM GND
TOPSTAR TECHNOLOGY
3

2N7002E-T1 PM
GR52 R240 Joseph
10K {42} EC_GPU_SML1DATA 3 2 GPU_SM_DATA 10K Page Name N11M IO_2
R0402 R0402
PM ns Size Project Name
PM Rev
Custom C49
Q34 +V3.3GPU A
1

Date: Friday, May 07, 2010 Sheet 21 of 59

PROPERTY NOTE: this document contains information confidential and property to
+V3.3GPU TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5 4 3 2 1
 5 4 3 2 1

+V3.3S {6,8,14,15,16,23,24,25,26,27,28,29,30,32,33,34,35,36,37,38,40,41,42,43,47,48,49,50,51,53,54,55,56}
+VDC {37,44,46,47,48,49,50,53,54,55}
+V3.3S
+V3.3AL {6,23,24,25,27,28,30,32,34,35,36,37,41,42,43,44,45,46,47,48,49,50,51,54,56}
+V5AL {30,40,41,46,47,48,51,54}
D24 2 1 1N4148WS
{41,42} LIDR# +V5S {24,26,30,33,34,36,38,40,41,42,49,50,53,54}
SOD323
R136
1K
D1
R0402
{16} LVDS_BKLTEN 1
LCDCON1
3 BKLT_ON LCDCON2X20
BKLT_ON {42}
CNS40_LCDB
2 LCDVDD
{42} HW_OFF_BKLT#
C168
BAT54A 41 41
1000pF/50V,X7R LCDVDD 1 2
C0402 1 2
D
3 3 4 4 D
{16} LVDS_YAM0 5 5 6 6 LVDS_YAM1 {16}
{16} LVDS_YAP0 7 7 8 8 LVDS_YAP1 {16}
9 9 10 10
{16} LVDS_YAM2 11 11 12 12 LVDS_CLKAP {16}
{16} LVDS_YAP2 13 13 14 14 LVDS_CLKAM {16}
15 15 16 16
LCDVDD BT_PWR 17 18 BT_USB_PP5_R
F1 ns 1.5A T-Fuse 17 18 BT_USB_PN5_R
19 19 20 20
AO6409 R0603 21 22
+V3.3S BT_PWRON_R 21 22
23 23 24 24
+V3.3AL 6 1 FB6 0 R0805 LCDVDD 25 26
D 25 26
5 2 {16} EDID_CLK 27 27 28 28
4 S 3 {16} EDID_DATA 29 29 30 30 EDID PWR
G C169 C170 C171 R139 +5VAL_Camera 31 32 LVDS_CAM_USB_PN3
2.2K F2 1.5A T-Fuse BKLT_PWM 31 32 LVDS_CAM_USB_PP3
Q4 33 33 34 34
R137 R138 C172 C173 C0402 10UF/6.3V,X5R C0805 R0402 +VDC R0603 ns 35 36 BKLT_ON
10K 100K C0402 0.1UF/25V,Y5V C0805 10UF/6.3V,X5R ns 35 36
37 37 38 38
3LCDVDD_EN#

R0402 ns C0402 ns 1 2 39 40
ns FB7 39 40
INVT_VDD 42 42
0.047uF/16V,X7R 0.01uF/16V,X7R 100ohm@100MHz,3A
R140 LVDS_VDDGON# C174 C175
100K FB0805 0.1uF/25V,X7R 0.1uF/25V,X7R
R0402 C0603 C0603
ns
Q5
2N7002 LCDVDD
1 SOT23 +VDC
{16} LVDS_VDDEN
2

R141 R142
100K 100 R143
R0402 R0603 100K

Q6 6

3
SC70_6

C LVDS_VDDEN 2 5 +V5AL C
2N7002DW
100pF/50V,NPO
1

VerB:Reverse Camera PWR control Circuit 071026

R144 0 R0402 C176 R145 +V5S
{42} EC_BKLT_PWM
100K

FB8 0 R0402 BKLT_PWM R146 R147

{21} GPU_LVDS_BKLTCTL
ns 0 0
R0805 R0805
FB26 0 R0402 R148 C177 ns
{26} LVDS_BKLTCTL
ns 10K
R0402 100pF/50V,NPO R149 0 R0805 E1
C0402

1
+5VAL_Camera EMI
ns
500mA

1
+V3.3S +V3.3AL 2 3
R150
10K Q7 C178 C179
R151 0 R0603 ns R0402 SOT23 0.1uF/10V,X5R 10UF/6.3V,X5R
ns AO3415 C0402 C0805

1
R152 0 R0603 EDID PWR ns
R153 10K
C180 R0402
ns
BT +V5S +V3.3S

3
0.1UF/10V,X7R
C0402 Add +5S to CAM POWER Q12
许沐锌 081111
AO3415
{42} Camera_ON 1
R285 BT 0 R0805 2 3 R286 0 BT_PWR
Q8 BT

2
R159 2N7002E-T1 R287 ns 0 R0805 BT BT C241
R158 R0603 0 100K SOT23 C240
R0402 ns 1000pF/50V,X7R 0.1UF/10V,X7R

1
R160 R0603 0 ns BT
R289
CHK1 100K
1 2 LVDS_CAM_USB_PN3 BT
{27} CAM_USB_PN3 LVDS_CAM_USB_PP3
{27} CAM_USB_PP3 4 3
B B
D2 D3
L4_0805 90ohm@100MHz,0.5A
1

ns BT_ON# R292 BT 1K
EGA10603V05A1-B EGA10603V05A1-B
ESDPAD_R0603 ESDPAD_R0603
ns ns
2

3
Q13 BT_PWRON 100K BT R957 BT_PWRON_R
2N7002E-T1-E3
R300 BT 1K 1 SOT23
{42} BT_PWRON
BT

2
R301 C242
100K
BT 0.47uF/25V,Y5V
BT

R0402 0 BT R288
R0402 0 BT R290

L4_0805 90ohm@100MHz,0.5A CHK6

1 2 BT_USB_PP5_R
{27} BT_USB_PP5
4 3 BT_USB_PN5_R
{27} BT_USB_PN5
ns

A A

TOPSTAR TECHNOLOGY
Joseph
Page Name
LVDS&Inverter CONN
Size Project Name Rev
C C49
A
Date: Friday, May 07, 2010 Sheet 22 of 59
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5 4 3 2 1
 5 4 3 2 1

+V1.05S {24,25,28,29,30,34,48,54,55,56}
+V3.3AL {6,22,24,25,27,28,30,32,34,35,36,37,41,42,43,44,45,46,47,48,49,50,51,54,56}
+V3.3S {6,8,14,15,16,22,24,25,26,27,28,29,30,32,33,34,35,36,37,38,40,41,42,43,47,48,49,50,51,53,54,55,56}
EC_RTC {44,46}
PCH_EC_RTC {30}

SPONGE_RTC1 Voltage Swing on RTCX1 pin

RTCBAT GLUE EC_RTC
assembly should not exceed 1.0V.
RTC_BAT1 D8
BAT54C PCH_EC_RTC
+ SOT23
- 1
RTCBAT with Cable
D D
assembly 3

根据机构 2 C186
1uF/10V,X7R
定Cable尺寸 C0603
CMOS Settings J1
Clear CMOS Short
R182
Keep CMOS Open
1K R183 20K R0402 +V3.3S
R0402

1
RTCBAT1 R184 20K R0402 J1
CONN2_R C187 C188 JOPEN U4A +V3.3S
3

CNS2_R R185 1uF/10V,X7R RESISTOR_1

1M C0603 1uF/10V,X7R ns 32XCLK0 R189 R186
1 1 B13 D33
3

RTCX1 FWH0 / LAD0 LPC_AD0 {34,37,42}

2
R0402 C0603 32XCLK1 10K 10K
2 2 D13 RTCX2 FWH1 / LAD1 B33 LPC_AD1 {34,37,42}
4

C32 R0402 R0402

FWH2 / LAD2 LPC_AD2 {34,37,42}
A32 ns ns
FWH3 / LAD3 LPC_AD3 {34,37,42}
4

RTC_RST# C14 R971

RTCRST# 10K
FWH4 / LFRAME# C34 LPC_FRAME# {34,37,42}
SRTC_RST# D17 R0402
SRTCRST#
LDRQ0# A34

RTC

LPC
SM_INTRUDER# A16 F34
INTRUDER# LDRQ1# / GPIO23
ICH_INTVRMEN A14 AB9 INT_SERIRQ
INTVRMEN SERIRQ INT_SERIRQ {34,42}

R187 33 R0402 A30

{33} AZALIA_CODEC_BITCLK HDA_BCLK
SATA0RXN AK7 SATA_RXN0 {40}
R188 33 R0402 D29 AK6 0.01uF/25V,X7R
{33} AZALIA_CODEC_SYNC HDA_SYNC SATA0RXP SATA_RXP0 {40}
AK11 0.01uF/25V,X7R
C387 C0402
SATA0TXN SATA_TXN0 {40}
P1 AK9 C388 C0402
{33} SPKR SPKR SATA0TXP SATA_TXP0 {40}
R190 33 R0402 C30
{33} AZALIA_CODEC_RST# HDA_RST#
SATA1RXN AH6 SATA_RXN1 {40}
AH5 0.01uF/25V,X7R
SATA1RXP SATA_RXP1 {40}
C G30 AH9 0.01uF/25V,X7R
C390 C0402 C
{33} AZALIA_SDATAIN0 HDA_SDIN0 SATA1TXN SATA_TXN1 {40}
AH8 C389 C0402
SATA1TXP SATA_TXP1 {40}
F30 HDA_SDIN1
AF11 R498 1K R0402 ns
SATA2RXN R499 1K R0402 ns
E32 HDA_SDIN2 SATA2RXP AF9

IHDA
SATA2TXN AF7
F32 HDA_SDIN3 SATA2TXP AF6

AH3 R500 1K R0402 ns

R191 33 R0402 SATA3RXN R501 1K R0402 ns
{33} AZALIA_CODEC_SDOUT B29 HDA_SDO SATA3RXP AH1
SATA3TXN AF3
SATA3TXP AF1
{42} EC_ME_LOCK# H32 HDA_DOCK_EN# / GPIO33

SATA
SATA4RXN AD9
J30 HDA_DOCK_RST# / GPIO13 SATA4RXP AD8
AD6 delete esata for costdown
R984 SATA4TXN
SATA4TXP AD5
4.7K
ns ns ICTP M3 AD3 R504 1K R0402 ns
T50 JTAG_TCK SATA5RXN
AD1 R505 1K R0402 ns
ns ICTP SATA5RXP
T51 K3 JTAG_TMS SATA5TXN AB3
SATA5TXP AB1
ns ICTP K1 +V1.05S
T52 JTAG_TDI

JTAG
ns ICTP J2 AF16
T53 JTAG_TDO SATAICOMPO
ns ICTP J4 AF15 R192 37.4,1% +V3.3S
T54 TRST# SATAICOMPI R0402

OD output
SPI_CLK R193 0 BA2 need pullup
SPI_CLK R195
SPI_CS0# R194 0 AV3 10K
+V3.3AL +V3.3S SPI_CS0# R0402
AY3 SPI_CS1# SATALED# T3 SATA_LED# {43}

R198 SPI_MOSI R197 0 AY1 Y9 R199 10K R0402 +V3.3S

B
R196 SPI_MOSI SATA0GP / GPIO21 B

SPI
0 0 SPI_MISO R200 0 AV1 V1 R201 10K R0402
ns SPI_MISO SATA1GP / GPIO19

R202
ns IbexPeak-M_Rev1_0

10K R0402
U5
8 5 SPI_MOSI
VDD SI SPI_MISO
SO 2
R203 3.3K 3 1 SPI_CS0#
WP# CE# SPI_CLK
SCK 6
R204 3.3K 7 HOLD#
VSS 4

8M
C184
SOIC8_50_208 PCH_EC_RTC
332K 1% PULL 32XCLK0 R178 0 C0402
HIGH TO
VBAT_RTC FOR R0402
Y2 15pF/50V,NPO
ICH8M INTRNAL

1
R179 VR ENABLE(PULL R180 32.768KHz
LOW DISABLE) 10M xd3_2X6
3
332K,1% R0402
R0402 ASSY

2
C185
ICH_INTVRMEN
32XCLK1 C0402

15pF/50V,NPO
R181
0
ns
R0402

A A

TOPSTAR TECHNOLOGY
Joseph
Page Name N10M PCIE&PWR&GND
Size Project Name Rev
C C49
A
Date: Friday, May 07, 2010 Sheet 23 of 59
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5 4 3 2 1
 5 4 3 2 1

+V3.3AL {6,22,23,25,27,28,30,32,34,35,36,37,41,42,43,44,45,46,47,48,49,50,51,54,56}

+V1.05S {23,25,28,29,30,34,48,54,55,56}

+V3.3S {6,8,14,15,16,22,23,25,26,27,28,29,30,32,33,34,35,36,37,38,40,41,42,43,47,48,49,50,51,53,54,55,56}

+V5S {22,26,30,33,34,36,38,40,41,42,49,50,53,54}

+V3.3AL

SMBCLK R515 2.2K

D D
SMBDATA R516 2.2K

GPIO11 R56 10K

R0402

GPIO60 R375 10K

R0402

SML0CLK R376 10K

R0402
U4B
SML0DATA R377 10K
R0402
BG30 B9 GPIO11
{41} PCIE_RXN1_LAN PERN1 SMBALERT# / GPIO11
BJ30 GPIO74 R509 10K
{41} PCIE_RXP1_LAN PERP1
C392 C0402 BF29 H14 SMBCLK R0402
{41} PCIE_TXN1_LAN PETN1 SMBCLK
C391 C0402 0.1UF/10V,X7R BH29
{41} PCIE_TXP1_LAN PETP1
0.1UF/10V,X7R C8 SMBDATA SML1CLK R544 2.2K
SMBDATA R0402
{37} PCIE_RXN2_3G AW30 PERN2
{37} PCIE_RXP2_3G BA30 PERP2
C393 C0402 BC30 J14 GPIO60 SML1DATA R545 2.2K
{37} PCIE_TXN2_3G PETN2 SML0ALERT# / GPIO60
C394 C0402 0.1UF/10V,X7R BD30 R0402
{37} PCIE_TXP2_3G PETP2
0.1UF/10V,X7R C6 SML0CLK
SML0CLK PEG_A_CLKRQ# R514 10K
AU30

SMBus
PERN3 SML0DATA R0402
AT30 PERP3 SML0DATA G8
delete pcie card for cost down AU32 PETN3
AV32 PETP3
M14 GPIO74
SML1ALERT# / GPIO74
{35} PCIE_RXN4_WLAN BA32 PERN4
{35} PCIE_RXP4_WLAN BB32 PERP4 SML1CLK / GPIO58 E10 SML1CLK {42}
C396 C0402 BD32
{35} PCIE_TXN4_WLAN PETN4
C395
0.1UF/10V,X7R C0402 BE32 G12
{35} PCIE_TXP4_WLAN PETP4 SML1DATA / GPIO75 SML1DATA {42}
0.1UF/10V,X7R

PCI-E*
BF33 PERN5
BH33 PERP5 CL_CLK1 T13 CL_CLK1 {35}

Controller
BG32 PETN5
BJ32 PETP5 CL_DATA1 T11 CL_DATA1 {35}
C C

Link
BA34 PERN6 CL_RST1# T9 CL_RST1# {35}
AW34 PERP6
BC34 PETN6
BD34 PETP6
H1 PEG_A_CLKRQ# R523 0 R0402 ns
PEG_A_CLKRQ# / GPIO47 PCIE_CLKREQ {17}
AT34 PERN7
AU34 PERP7
AU36 AD43 R519 0 R0402
PETN7 CLKOUT_PEG_A_N CLK_PCIE_N11M# {17}
AV36 AD45 R520 0 R0402
PETP7 CLKOUT_PEG_A_P CLK_PCIE_N11M {17}
+V3.3AL
BG34 PERN8 CLKOUT_DMI_N AN4 CLK_EXP_N {8}

PEG
BJ34 PERP8 CLKOUT_DMI_P AN2 CLK_EXP_P {8}
BG36 PETN8
BJ36 PETP8
AT1 R563 0 R0402
R16 CLKOUT_DP_N / CLKOUT_BCLK1_N
CLKOUT_DP_P / CLKOUT_BCLK1_P AT3
10K {41} CLK_PCIE_GLAN# AK48 CLKOUT_PCIE0N
R0402 {41} CLK_PCIE_GLAN AK47 CLKOUT_PCIE0P
From CLK BUFFER
CLKIN_DMI_N AW24 CLK_BUF_SATA_N {6}
P9 PCIECLKRQ0# / GPIO73 CLKIN_DMI_P BA24 CLK_BUF_SATA_P {6}

+V3.3AL AM43 AP3

{37} CLK_PCIE_3G# CLKOUT_PCIE1N CLKIN_BCLK_N CLK_BUF_BCLK_N {6}
{37} CLK_PCIE_3G AM45 CLKOUT_PCIE1P CLKIN_BCLK_P AP1 CLK_BUF_BCLK_P {6}

{37} MiniPCIE_REQ# U4 PCIECLKRQ1# / GPIO18

CLKIN_DOT_96N F18 CLK_BUF_DOT96_N {6}
CLKIN_DOT_96P E18 CLK_BUF_DOT96_P {6}
{35} CLK_PCIE_MINICARD# AM47 CLKOUT_PCIE2N
{35} CLK_PCIE_MINICARD AM48 CLKOUT_PCIE2P
CLKIN_SATA_N / CKSSCD_N AH13 CLK_BUF_EXP_N {6}
R906 R905 N4 AH12
{35} minicard_CLKREQ# PCIECLKRQ2# / GPIO20 CLKIN_SATA_P / CKSSCD_P CLK_BUF_EXP_P {6}
10K 10K
R0402 R0402
+V3.3AL AH42 P41
delete pcie card for cost down CLKOUT_PCIE3N REFCLK14IN CLK_BUF_REF14 {6}
AH41 CLKOUT_PCIE3P
MiniPCIE_REQ# and disable this clock output
B B
R915 8.2K R0402 A8 J42
PCIECLKRQ3# / GPIO25 CLKIN_PCILOOPBACK PCI_CLKFB {27}
minicard_CLKREQ#
+V3.3AL
AM51 AH51 R508 0
CLKOUT_PCIE4N XTAL25_IN R521 10M
AM53 CLKOUT_PCIE4P XTAL25_OUT AH53
R0402
R907 8.2K R0402 M9 AF38 R522 90.9,1%
PCIECLKRQ4# / GPIO26 XCLK_RCOMP R0402 +V1.05S
+V3.3AL
AJ50 CLKOUT_PCIE5N CLKOUTFLEX0 / GPIO64 T45 Y5
AJ52 CLKOUT_PCIE5P
2 1
R908 8.2K R0402 H6 P43
Clock Flex

PCIECLKRQ5# / GPIO44 CLKOUTFLEX1 / GPIO65

25MHz
+V3.3AL AK53 T42 XS2_3d3
CLKOUT_PEG_B_N CLKOUTFLEX2 / GPIO66 C400 C399
AK51 CLKOUT_PEG_B_P
27pF/50V,NPO 27pF/50V,NPO
R909 8.2K R0402 P13 N50 R564 33 CLK_CR_48M {32} C0402 C0402
PEG_B_CLKRQ# / GPIO56 CLKOUTFLEX3 / GPIO67

IbexPeak-M_Rev1_0
+V3.3S

R517
R910 0 R0402 ns 2.2K

Q29
2N7002E-T1
SMBCLK 3 2 SMB_CLK_S {6,14,15,37}

+V3.3S
A +V5S A
1

R518
R911 0 R0402 ns 2.2K
TOPSTAR TECHNOLOGY
Q30
2N7002E-T1 Joseph
Page Name N10M PCIE&PWR&GND
SMBDATA 3 2 SMB_DATA_S {6,14,15,37} Size Project Name Rev
C C49
A
Date: Friday, May 07, 2010 Sheet 24 of 59
1

+V5S
5 4 3 2
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
1
 5 4 3 2 1

+V3.3AL {6,22,23,24,27,28,30,32,34,35,36,37,41,42,43,44,45,46,47,48,49,50,51,54,56}
+V3.3S {6,8,14,15,16,22,23,24,26,27,28,29,30,32,33,34,35,36,37,38,40,41,42,43,47,48,49,50,51,53,54,55,56}
+V1.05S {23,24,28,29,30,34,48,54,55,56}

U4C
D FDI_TXN[7:0] {7} D
BA18 FDI_TXN0
DMI_RXN0 FDI_RXN0 FDI_TXN1
{7} DMI_RXN0 BC24 DMI0RXN FDI_RXN1 BH17
DMI_RXN1 BJ22 BD16 FDI_TXN2
{7} DMI_RXN1 DMI1RXN FDI_RXN2
DMI_RXN2 AW20 BJ16 FDI_TXN3
{7} DMI_RXN2 DMI2RXN FDI_RXN3
DMI_RXN3 BJ20 BA16 FDI_TXN4
{7} DMI_RXN3 DMI3RXN FDI_RXN4
BE14 FDI_TXN5
DMI_RXP0 FDI_RXN5 FDI_TXN6
{7} DMI_RXP0 BD24 DMI0RXP FDI_RXN6 BA14
DMI_RXP1 BG22 BC12 FDI_TXN7
{7} DMI_RXP1 DMI1RXP FDI_RXN7
DMI_RXP2 BA20
{7} DMI_RXP2 DMI2RXP FDI_TXP[7:0] {7}
DMI_RXP3 BG20 BB18 FDI_TXP0
{7} DMI_RXP3 DMI3RXP FDI_RXP0
BF17 FDI_TXP1
DMI_TXN0 FDI_RXP1 FDI_TXP2
{7} DMI_TXN0 BE22 DMI0TXN FDI_RXP2 BC16
+V1.05S DMI_TXN1 BF21 BG16 FDI_TXP3
{7} DMI_TXN1 DMI1TXN FDI_RXP3
DMI_TXN2 BD20 AW16 FDI_TXP4
{7} DMI_TXN2 DMI2TXN FDI_RXP4
DMI_TXN3 BE18 BD14 FDI_TXP5
{7} DMI_TXN3 DMI3TXN FDI_RXP5
BB14 FDI_TXP6
DMI_TXP0 FDI_RXP6 FDI_TXP7
{7} DMI_TXP0 BD22 DMI0TXP FDI_RXP7 BD12
DMI_TXP1 BH21
{7} DMI_TXP1 DMI1TXP
DMI_TXP2 BC20
{7} DMI_TXP2 DMI2TXP
R205 DMI_TXP3 BD18 BJ14
{7} DMI_TXP3 DMI3TXP FDI_INT FDI_INT {7}
49.9,1%

DMI
FDI
R0402 FDI_FSYNC0 BF13 FDI_FSYNC0 {7}
BH25 DMI_ZCOMP
FDI_FSYNC1 BH13 FDI_FSYNC1 {7}
DMI_COMP_R BF25 DMI_IRCOMP
FDI_LSYNC0 BJ12 FDI_LSYNC0 {7}
+V3.3S
FDI_LSYNC1 BG14 FDI_LSYNC1 {7}

R524
10K
R0402

{42} SYS_RST# T6 SYS_RESET# WAKE# J12 PCIE_WAKE# {35,37,41,42}

C C
R527 0 R0402 M6 Y1 CLKRUN#
SYS_PWROK CLKRUN# / GPIO32

System Power Management

SYS_PWROK R528 0 R0402 B17 PWROK

R529 0 R0402 K5 P8
This is suspend power pin MEPWROK SUS_STAT# / GPIO61 PM_SUS_STAT# {42}

R533 10K A10 F3 T74 ICTPns

R0402 LAN_RST# SUSCLK / GPIO62
+V3.3AL
R489 0 R0402 D9 E4 R535 0 R0402 T143 ns
{8} PM_DRAM_PWRGD DRAMPWROK SLP_S5# / GPIO63

C16 H7 R541 0 R0402

{42,51} PM_RSMRST# RSMRST# SLP_S4# PM_SLP_S4# {42,54}
R321
10K
M1 P12 R542 0 R0402 ns
ALW_ACK SUS_PWR_DN_ACK / GPIO30 SLP_S3# PM_SLP_S3# {42,51}
R531
+V3.3AL 10K
R0402 R534 0 R0402 P5 K8 +V3.3AL
{42} PM_PWRBTN# PWRBTN# SLP_M#

也就是AL_PWRGD信号
{42} AC_IN_PCH P7 ACPRESENT / GPIO31 TP23 N2 T144 ns
M电就用S电。此信号不用
C401
R323
0.1UF/25V,Y5V BAT_LOW# A6 BJ10 10K
U20 BATLOW# / GPIO72 PMSYNCH H_PM_SYNC {8}
ns
5

74AHCT1G08GV
ns 1 VCC SOT23_5 RI# F14 F6
{42,51} Main_PWROK RI# SLP_LAN# / GPIO29
4 SYS_PWROK
2 +V3.3AL
{42} EC_IMVP_PWRGD GND IbexPeak-M_Rev1_0
3

ns R525
10K ALW_ACK R402 10K
B B
R0402 R0402

R526 0
+V3.3AL
+V3.3S

R538 10K RI# R540 10K CLKRUN#

R0402 R0402

R537 10K PM_PWRBTN#

R0402

R539 1K PCIE_WAKE#
R0402

10K R536 BAT_LOW#

A A

TOPSTAR TECHNOLOGY
Joseph
Page Name N10M PCIE&PWR&GND
Size Project Name Rev
C C49
A
Date: Friday, May 07, 2010 Sheet 25 of 59
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5 4 3 2 1
 5 4 3 2 1

+V3.3S {6,8,14,15,16,22,23,24,25,27,28,29,30,32,33,34,35,36,37,38,40,41,42,43,47,48,49,50,51,53,54,55,56}

+V5S {22,24,30,33,34,36,38,40,41,42,49,50,53,54}

{16} PCH_LVDS_BKLTEN
+V3.3S

R638
100K

R627 R628
10K 10K
D D

LCTL_DATA

LCTL_CLK

+V3.3S

U4D

R631 R629 T48 BJ46

{16} PCH_LVDS_BKLTEN L_BKLTEN SDVO_TVCLKINN
2.2K 2.2K T47 BG46
{16} PCH_LVDS_VDDEN L_VDD_EN SDVO_TVCLKINP

{22} LVDS_BKLTCTL Y48 L_BKLTCTL SDVO_STALLN BJ48

SDVO_STALLP BG48
PCH_DDC_CLK AB48
PCH_DDC_DATA {16} L_DDC_CLK
PCH_DDC_DATA Y45 BF45
L_DDC_DATA SDVO_INTN
PCH_DDC_CLK {16} SDVO_INTP BH45
LCTL_CLK AB46
LCTL_DATA L_CTRL_CLK
V48 L_CTRL_DATA
AP39 LVD_IBG SDVO_CTRLCLK T51
T156 AP41 T53
R632 ns LVD_VBG SDVO_CTRLDATA
2.37K,1% AT43 LVD_VREFH
AT42 LVD_VREFL DDPB_AUXN BG44
DDPB_AUXP BJ44
DDPB_HPD AU38

LVDS
{16} PCH_LVDS_CLKAM AV53 LVDSA_CLK#
{16} PCH_LVDS_CLKAP AV51 LVDSA_CLK DDPB_0N BD42
DDPB_0P BC42
{16} PCH_LVDS_YAM0 BB47 LVDSA_DATA#0 DDPB_1N BJ42
BA52 BG42

Digital Display Interface

{16} PCH_LVDS_YAM1 LVDSA_DATA#1 DDPB_1P
{16} PCH_LVDS_YAM2 AY48 LVDSA_DATA#2 DDPB_2N BB40
T157 AV47 BA40
ns LVDSA_DATA#3 DDPB_2P
C
DDPB_3N AW38 C
BB48 BA38 +V5S
{16} PCH_LVDS_YAP0 LVDSA_DATA0 DDPB_3P
{16} PCH_LVDS_YAP1 BA50 LVDSA_DATA1
{16} PCH_LVDS_YAP2 AY49 LVDSA_DATA2
T161 AV48 Y49
LVDSA_DATA3 DDPC_CTRLCLK GM_HDMI_DDC_CLK {36}
ns AB49
DDPC_CTRLDATA GM_HDMI_DDC_DATA {36}

1
AP48 LVDSB_CLK#
AP47 LVDSB_CLK DDPC_AUXN BE44
DDPC_AUXP BD44
AY53 AV40 DDPC_HPD 2 3
LVDSB_DATA#0 DDPC_HPD MCH_HDMI_HPD {36}
AT49 LVDSB_DATA#1
AU52 LVDSB_DATA#2 DDPC_0N BE40 IN_D2- {36}
AT53 BD40 Q41
LVDSB_DATA#3 DDPC_0P IN_D2+ {36}
BF41 R635 2N7002
DDPC_1N IN_D1- {36}
AY51 BH41 100K ns
LVDSB_DATA0 DDPC_1P IN_D1+ {36}
AT48 BD38 GM
LVDSB_DATA1 DDPC_2N IN_D0- {36}
AU50 BC38 R636 0 R0402
LVDSB_DATA2 DDPC_2P IN_D0+ {36}
AT51 BB36 GM
LVDSB_DATA3 DDPC_3N MCH_CLK_D4- {36}
DDPC_3P BA36 MCH_CLK_D4+ {36}

CRT_BLUE_R AA52 U50

{38} CRT_BLUE_R CRT_BLUE DDPD_CTRLCLK
CRT_GREEN_R AB53 U52
{38} CRT_GREEN_R CRT_GREEN DDPD_CTRLDATA
CRT_RED_R AD53
{38} CRT_RED_R CRT_RED

DDPD_AUXN BC46
CRT_DDC_CLK_R V51 BD46
{38} CRT_DDC_CLK_R CRT_DDC_CLK DDPD_AUXP
CRT_DDC_DATA_R V53 AT38
{38} CRT_DDC_DATA_R CRT_DDC_DATA DDPD_HPD

DDPD_0N BJ40
CRT_HSYNC_R Y53 BG40
{38} CRT_HSYNC_R CRT_HSYNC DDPD_0P
CRT_VSYNC_R Y51 BJ38
{38} CRT_VSYNC_R CRT_VSYNC DDPD_1N
DDPD_1P BG38
CRT

DDPD_2N BF37
AD48 DAC_IREF DDPD_2P BH37
AB51 CRT_IRTN DDPD_3N BE36
B DDPD_3P BD36 B
R702 150,1% GM CRT_BLUE_R R630 IbexPeak-M_Rev1_0
1K,1%

R703 150,1% GM CRT_GREEN_R

R704 150,1% GM CRT_RED_R

A A

TOPSTAR TECHNOLOGY
Joseph
Page Name PCH
Size Project Name Rev
C C49
A
Date: Friday, May 07, 2010 Sheet 26 of 59
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5 4 3 2 1
 5 4 3 2 1

+V3.3AL {6,22,23,24,25,28,30,32,34,35,36,37,41,42,43,44,45,46,47,48,49,50,51,54,56}

+V3.3S {6,8,14,15,16,22,23,24,25,26,28,29,30,32,33,34,35,36,37,38,40,41,42,43,47,48,49,50,51,53,54,55,56}

+V1.8S {11,16,29,30,47,54,55}

D D

+V3.3S +V3.3AL
PLTRST buffer H40
U4E
AY9
AD0 NV_CE#0
N34 AD1 NV_CE#1 BD1
C44 AD2 NV_CE#2 AP15
R207 R208 A38 BD8
AD3 NV_CE#3
0 0 C36 AD4
R0402 R0402 J34 AV9
ns AD5 NV_DQS0
A40 AD6 NV_DQS1 BG8
D45 AD7
E36 AD8 NV_DQ0 / NV_IO0 AP7
C189 H48 AP6
AD9 NV_DQ1 / NV_IO1
E40 AD10 NV_DQ2 / NV_IO2 AT6
0.1UF/25V,Y5V C40 AT9
C0402 AD11 NV_DQ3 / NV_IO3
M48 AD12 NV_DQ4 / NV_IO4 BB1
5

C M45 AD13 NV_DQ5 / NV_IO5 AV6 C

VCC 1 PLT_RST# F53 BB3
AD14 NV_DQ6 / NV_IO6
{8,17,34,35,37,41,42} BUF_PLT_RST# 4 M40 AD15 NV_DQ7 / NV_IO7 BA4
2 M43 BE4

NVRAM
GND AD16 NV_DQ8 / NV_IO8
J36 AD17 NV_DQ9 / NV_IO9 BB6
U6 R206 K48 BD6
AD18 NV_DQ10 / NV_IO10
3

R210 74AHCT1G08GV 10K F40 BB7

SOT23_5 R0402 AD19 NV_DQ11 / NV_IO11
100K C42 AD20 NV_DQ12 / NV_IO12 BC8
R0402 K46 BJ8
AD21 NV_DQ13 / NV_IO13
M51 AD22 NV_DQ14 / NV_IO14 BJ6
J52 AD23 NV_DQ15 / NV_IO15 BG6
K51 AD24
L34 AD25 NV_ALE BD3
F42 AD26 NV_CLE AY6
PCI_GNT#0 J40 AD27
PCI_GNT1# PCI_GNT0# Boot BIOS G46 AD28
F44 AD29 NV_RCOMP AU2
PCI_GNT#1 1 1 SPI M47 AD30

PCI
H36 AD31 NV_RB# AV7
1 0 PCI
J50 C/BE0# NV_WR#0_RE# AY8
R212 R213 0 0 LPC G42 AY5
1K 1K C/BE1# NV_WR#1_RE#
H47 C/BE2#
R0402 R0402 G34 AV11
ns ns C/BE3# NV_WE#_CK0
NV_WE#_CK1 BF5
INT_PIRQA# G38
INT_PIRQB# PIRQA#
H51 PIRQB#
INT_PIRQC# B37 H18
INT_PIRQD# PIRQC# USBP0N
A44 PIRQD# USBP0P J18
USBP1N A18 CAM_USB_PN3 {22}
PCI_GNT#3
PCI_REQ#0
LVDS_SEL_PCH
F51
A46
REQ0# USBP1P C18
N20
CAM_USB_PP3 {22} MINICARD
REQ1# / GPIO50 USBP2N MINICARD_USB_PN2 {37}
{16} LVDS_BLT_SEL B45 REQ2# / GPIO52 USBP2P P20 MINICARD_USB_PP2 {37}
PCI_REQ#3 M53 J20
REQ3# / GPIO54 USBP3N MINICARD_USB_PN1 {35} CAMERA
USBP3P L20 MINICARD_USB_PP1 {35}
PCI_GNT#3 Low=A16 swap override/ R214 PCI_GNT#0 F48 F20
Top Block Swap Mode Topblock Swap Override enable 1K PCI_GNT#1 GNT0# USBP4N
K45 GNT1# / GPIO51 USBP4P G20
Strap High=Default R0402 GNT2# F36 A20
B GNT2# / GPIO53 USBP5N BT_USB_PN5 {22} BT B
ns PCI_GNT#3 H53 C20
4.7K in checklist GNT3# / GPIO55 USBP5P BT_USB_PP5 {22}
USBP6N M22
INT_PIRQE# B41 N22
INT_PIRQF# PIRQE# / GPIO2 USBP6P
K53 PIRQF# / GPIO3 USBP7N B21
INT_PIRQG# A36 D21
PIRQG# / GPIO4 USBP7P
{16} LVDS_DDC_SEL A48 PIRQH# / GPIO5 USBP8N H22 USB_CR_PN8 {32} CARD READER
USBP8P J22 USB_CR_PP8 {32}
PCI_RST#
USB

K6 PCIRST# USBP9N E22 USB_PN9 {40} Esata_usb conn

PCI pullup +V3.3S PCI_SERR# E44
USBP9P F22
A22
USB_PP9 {40}
SERR# USBP10N USB_PN10 {41}
PCI_PERR# E50 C22
PERR# USBP10P USB_PP10 {41} USB CONN
USBP11N G24 USB_PN11 {41}
USBP11P H24 USB_PP11 {41}
PCI_FRAME# R216 8.2K R0402 PCI_IRDY# A42 L24
IRDY# USBP12N T25 ns
PCI_IRDY#
PCI_TRDY#
R217
R218
8.2K
8.2K
R0402
R0402
T26
ICTP ns
PCI_PAR
PCI_DEVSEL#
H44
F46
PAR USBP12P M24
A24
T27 ns Attribution
DEVSEL# USBP13N T28 ns
PCI_STOP# R219 8.2K R0402 PCI_FRAME# C46 FRAME# USBP13P C24 T29 ns TBD
PCI_SERR# R220 8.2K R0402
PCI_DEVSEL# R221 8.2K R0402 PCI_LOCK# D49
PCI_PERR# R222 8.2K R0402 PLOCK# USB_BIAS
USBRBIAS# B25
PCI_LOCK# R223 8.2K R0402 PCI_STOP# D41
PCI_REQ#0 R224 8.2K R0402 PCI_TRDY# STOP#
C48 TRDY# USBRBIAS D25
LVDS_SEL_PCH R912 8.2K R0402
LVDS_BLT_SEL R226 8.2K R0402 T30 PCI_PME M7 R227
PCI_REQ#3 R228 8.2K R0402 ICTP ns PME# OC0# 22.6,1%
OC0# / GPIO59 N16
LVDS_DDC_SEL R237 8.2K R0402 PLT_RST# D5 J16 OC1# R0402
GNT2# R252 8.2K R0402 PLTRST# OC1# / GPIO40 OC2#
OC2# / GPIO41 F16
INT_PIRQA# R229 8.2K R0402 47 R510 N52 L16 OC3#
{42} CLK_591PCI CLKOUT_PCI0 OC3# / GPIO42
INT_PIRQB# R230 8.2K R0402 47 R511 P53 E14
{34} CLK_TCMPCI CLKOUT_PCI1 OC4# / GPIO43 USB_OC#4 {40}
INT_PIRQC# R231 8.2K R0402 22 R506 P46 G16
{24} PCI_CLKFB CLKOUT_PCI2 OC5# / GPIO9 USB_OC#5 {41}
INT_PIRQD# R232 8.2K R0402 47 R507 P51 F12 OC6#
{37} PCI_CLK_DEBUG CLKOUT_PCI3 OC6# / GPIO10
INT_PIRQE# R233 8.2K R0402 P48 T15 OC7#
INT_PIRQF# R235 8.2K R0402 CLKOUT_PCI4 OC7# / GPIO14
INT_PIRQG# R236 8.2K R0402
IbexPeak-M_Rev1_0
PCI_RST# R238 8.2K R0402 ns +V3.3AL
+V1.8S
A +V1.8S A

OC0# R0402 10K R917

R913 OC1# R0402 10K R918

1K,1% R914 TOPSTAR TECHNOLOGY
R0402 10K OC3# R0402 10K R919
R0402 Joseph
PM PM OC6# R0402 10K R921 Page Name N10M PCIE&PWR&GND
OC7# R0402 10K R922 Size Project Name Rev
1

C C49
Q42 OC2# R0402 10K R927 A
LVDS_SEL_PCH 2 3 Date: Friday, May 07, 2010 Sheet 27 of 59
{16} LVDS_SEL_PCH LVDS_SEL {16}
MMBT3904-FSOT23 PROPERTY NOTE: this document contains information confidential and property to
PM TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5 4 3 2 1
 5 4 3 2 1

+V1.1S_VTT {8,10,11,48,49,53}
+V3.3AL {6,22,23,24,25,27,30,32,34,35,36,37,41,42,43,44,45,46,47,48,49,50,51,54,56}
+V3.3S {6,8,14,15,16,22,23,24,25,26,27,29,30,32,33,34,35,36,37,38,40,41,42,43,47,48,49,50,51,53,54,55,56}
+V1.05S {23,24,25,29,30,34,48,54,55,56}

D D

+V3.3S GPIO24 R557 10K R0402 ns

SATA4GP R241 10K R0402 ns

U4F
GPIO0 R546 10K
GPIO0 Y3 AH45 SATA_CLKREQ# R560 10K R0402
EXTSMI# R547 10K BMBUSY# / GPIO0 CLKOUT_PCIE6N
CLKOUT_PCIE6P AH46
C38 GPIO27 R337 10K R0402 ns
GPIO6 R548 10K EXTSMI# TACH1 / GPIO1
GPIO6 D37
EC_RUNTIME_SCI# R549 10K TACH2 / GPIO6
CLKOUT_PCIE7N AF48

MISC
J32 TACH3 / GPIO7 CLKOUT_PCIE7P AF47
SATA2GP R239 10K {42} EC_RUNTIME_SCI#
GPIO8 F10 internal pull up. default to use internal VccVRM
SATA4GP R553 10K GPIO8 +V1.05S
LAN_PHY K9 U2
LAN_PHY_PWR_CTRL / GPIO12 A20GATE H_A20GATE {42}
GPIO17 R554 10K
GPIO15 T7
GPIO22 R555 10K GPIO15
SATA4GP AA2 AM3
SATA4GP / GPIO16 CLKOUT_BCLK0_N / CLKOUT_PCIE8N BCLK_CPU_N {8}
STP_PCI# R559 10K
GPIO17 F38 AM1
TACH0 / GPIO17 CLKOUT_BCLK0_P / CLKOUT_PCIE8P BCLK_CPU_P {8}
SATA5GP R242 10K
GPIO22 Y7 BG10 R486
SCLOCK / GPIO22 PECI H_PECI {8}

GPIO
GPIO48 R565 10K 56
GPIO24 H10 T1 R0402
GPIO24 RCIN# H_RCIN# {42}
H_RCIN# R569 10K
GPIO27 AB12 BE10
GPIO27 PROCPWRGD VCCPWRGD_0 {8}

CPU
C C
GPIO28 V13 BD10 THERMTRIP_R# R485 54.9,1% R0402
GPIO28 THRMTRIP# THERMTRIP# {8,34}
STP_PCI# M11 STP_PCI# / GPIO34
SATA_CLKREQ# V6 SATACLKREQ# / GPIO35
SATA2GP AB7 BA22
SATA2GP / GPIO36 TP1
GPIO37 AB13 AW22
+V3.3AL SATA3GP / GPIO37 TP2
GPIO38 V3 BB22
SLOAD / GPIO38 TP3
GPIO8 R550 10K GPIO39 P3 AY45
SDATAOUT0 / GPIO39 TP4
LAN_PHY R551 10K T38 H3 AY46
ICTP ns PCIECLKRQ6# / GPIO45 TP5
GPIO15 R552 1K T41 F1 AV43
ICTP ns PCIECLKRQ7# / GPIO46 TP6
GPIO24 R556 10K ns GPIO48 AB6 AV45
SDATAOUT1 / GPIO48 TP7
GPIO28 R558 10K SATA5GP AA4 AF13
SATA5GP / GPIO49 TP8
GPIO57 R568 10K GPIO57 F8 M18
GPIO57 TP9

TP10 N18

A4 VSS_NCTF_1 TP11 AJ24

A49 VSS_NCTF_2

NCTF

RSVD
A5 VSS_NCTF_3 TP12 AK41
A50 VSS_NCTF_4
A52 VSS_NCTF_5 TP13 AK42
A53 VSS_NCTF_6
B2 VSS_NCTF_7 TP14 M32
+V3.3S B4 VSS_NCTF_8
B52 VSS_NCTF_9 TP15 N32
B53 VSS_NCTF_10
B
BE1 VSS_NCTF_11 TP16 M30 B
BE53 VSS_NCTF_12
BF1 VSS_NCTF_13 TP17 N30
R567 R575R574 BF53
10K 10K 10K VSS_NCTF_14
BH1 VSS_NCTF_15 TP18 H12
ns ns ns BH2 VSS_NCTF_16
BH52 VSS_NCTF_17 TP19 AA23
BH53 VSS_NCTF_18
BJ1 VSS_NCTF_19 NC_1 AB45
GPIO37 BJ2 VSS_NCTF_20
BJ4 VSS_NCTF_21 NC_2 AB38
GPIO38 BJ49 VSS_NCTF_22
BJ5 VSS_NCTF_23 NC_3 AB42
GPIO39 BJ50 VSS_NCTF_24
BJ52 VSS_NCTF_25 NC_4 AB41
BJ53 VSS_NCTF_26
D1 VSS_NCTF_27 NC_5 T39
D2 VSS_NCTF_28
D53 VSS_NCTF_29
E1 VSS_NCTF_30 INIT3_3V# P6
R578 R577R576 E53
10K 10K 10K VSS_NCTF_31
TP24 C10

IbexPeak-M_Rev1_0

For differentiate BIOS version

A A

TOPSTAR TECHNOLOGY
Joseph
Page Name N10M PCIE&PWR&GND
Size Project Name Rev
C C49
A
Date: Friday, May 07, 2010 Sheet 28 of 59
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5 4 3 2 1
 5 4 3 2 1

+V1.1S_VTT {8,10,11,48,49,53}
+V1.05S {23,24,25,28,30,34,48,54,55,56}
+V3.3S {6,8,14,15,16,22,23,24,25,26,27,28,30,32,33,34,35,36,37,38,40,41,42,43,47,48,49,50,51,53,54,55,56}
+V1.8S {11,16,27,30,47,54,55}

D D

+V3.3S

+V1.05S

U4G POWER
AB24 AE50 FB291 2 FB0603
VCCCORE[1] VCCADAC[1]
AB26 VCCCORE[2]
AB28 AE52 C412 C424 120ohm@100MHz,500mA
VCCCORE[3] VCCADAC[2]
C402 C403 AD26 VCCCORE[4] C411

CRT
AD28 VCCCORE[5] VSSA_DAC[1] AF53 C133 C134 C139
10uF/6.3V,X5R 1uF/10V,X7R AF26 0.01uF/16V,X7R 0.1UF/10V,X7R 1uF/10V,X7R
VCCCORE[6] 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R

VCC CORE
AF28 VCCCORE[7] VSSA_DAC[2] AF51
AF30 VCCCORE[8]
AF31 VCCCORE[9]
AH26 VCCCORE[10]
AH28 +V3.3S
VCCCORE[11]
AH30 VCCCORE[12]
AH31 VCCCORE[13] VCCALVDS AH38
AJ30 +V1.8S
VCCCORE[14]
AJ31 VCCCORE[15] VSSA_LVDS AH39

AP43 FB311 2 FB0603

+V1.05S VCCTX_LVDS[1]
VCCTX_LVDS[2] AP45
AT46 C413 C425 120ohm@100MHz,500mA

LVDS
VCCTX_LVDS[3]
AK24 VCCIO[24] VCCTX_LVDS[4] AT45 C414
0.01uF/16V,X7R 0.1UF/10V,X7R 1uF/10V,X7R
FB271 2 FB0603 VCCAPLL BJ24 VCCAPLLEXP +V3.3S
VCC3_3[2] AB34
120ohm@100MHz,500mA C404
ns AN20 VCCIO[25] VCC3_3[3] AB35
C 1uF/10V,X7R AN22 C

HVCMOS
ns VCCIO[26]
AN23 VCCIO[27] VCC3_3[4] AD35
+V1.05S AN24 VCCIO[28] C426
AN26 VCCIO[29]
AN28 VCCIO[30]
BJ26 VCCIO[31]
R570 0 R0805 BJ28 0.1UF/10V,X7R
VCCIO[32]
AT26 VCCIO[33]
AT28 VCCIO[34]
AU26 +V1.8S
C405 C406 C407 VCCIO[35]
AU28 VCCIO[36]
10uF/6.3V,X5R 1uF/10V,X7R 1uF/10V,X7R AV26 VCCIO[37]
AV28 VCCIO[38] VCCVRM[2] AT24
AW26 +V1.05S
VCCIO[39]
AW28 VCCIO[40] C415

DMI
BA26 VCCIO[41] VCCDMI[1] AT16
BA28 1uF/10V,X7R
VCCIO[42]
BB26 VCCIO[43] VCCDMI[2] AU16 C416
BB28 VCCIO[44]
BC26 1uF/10V,X7R
C408 C409 VCCIO[45]
PCI E*

BC28 VCCIO[46]
1uF/10V,X7R 1uF/10V,X7R BD26 +V1.8S
VCCIO[47]
BD28 VCCIO[48]
BE26 VCCIO[49] VCCPNAND[1] AM16
BE28 VCCIO[50] VCCPNAND[2] AK16
BG26 VCCIO[51] VCCPNAND[3] AK20
BG28 VCCIO[52] VCCPNAND[4] AK19 C417
BH27 VCCIO[53] VCCPNAND[5] AK15
AK13 1uF/10V,X7R
+V3.3S VCCPNAND[6]
AN30 VCCIO[54] VCCPNAND[7] AM12
NAND / SPI

AN31 VCCIO[55] VCCPNAND[8] AM13

+V1.8S AM15
VCCPNAND[9]
+V1.05S AN35 VCC3_3[1]

AT22 VCCVRM[1]
B B
FB281 2 FB0603 BJ18 AM8
VCCFDIPLL VCCME3_3[1] +V3.3S
VCCME3_3[2] AM9
120ohm@100MHz,500mA
FDI

C410 AM23 VCCIO[1] VCCME3_3[3] AP11

ns VCCME3_3[4] AP9
1uF/10V,X7R
ns C427

IbexPeak-M_Rev1_0
0.1UF/10V,X7R

A A

TOPSTAR TECHNOLOGY
Joseph
Page Name N10M PCIE&PWR&GND
Size Project Name Rev
C C49
A
Date: Friday, May 07, 2010 Sheet 29 of 59
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5 4 3 2 1
 5 4 3 2 1

+V1.1S_VTT {8,10,11,48,49,53}
+V1.05S {23,24,25,28,29,34,48,54,55,56}
+V5AL {22,40,41,46,47,48,51,54}
+V3.3AL {6,22,23,24,25,27,28,32,34,35,36,37,41,42,43,44,45,46,47,48,49,50,51,54,56}
+V5S {22,24,26,33,34,36,38,40,41,42,49,50,53,54}
+V3.3S {6,8,14,15,16,22,23,24,25,26,27,28,29,32,33,34,35,36,37,38,40,41,42,43,47,48,49,50,51,53,54,55,56}
PCH_EC_RTC {23}
+V1.8S {11,16,27,29,47,54,55}

+V1.05S +V1.05S
U4J POWER
D D
FB32 1 2 FB0603 AP51 V24
120ohm@100MHz,500mA VCCACLK[1] VCCIO[5]
VCCIO[6] V26
ns C418 C419 AP53 VCCACLK[2] VCCIO[7] Y24 C444
VCCIO[8] Y26
10uF/6.3V,X5R 1uF/10V,X7R 1uF/10V,X7R
ns ns AF23 V28
VCCLAN[1] VCCSUS3_3[1]
VCCSUS3_3[2] U28
R211 0 R0402 AF24 U26
VCCLAN[2] VCCSUS3_3[3] +V3.3AL
VCCSUS3_3[4] U24
VCCSUS3_3[5] P28
Y20 DCPSUSBYP VCCSUS3_3[6] P26
+V1.05S C132 N28
0.1UF/10V,X7R VCCSUS3_3[7]
VCCSUS3_3[8] N26
AD38 M28 C449 C447 C448
VCCME[1] VCCSUS3_3[9]
VCCSUS3_3[10] M26
AD39 L28

USB
VCCME[2] VCCSUS3_3[11] 0.1UF/10V,X7R 0.1UF/10V,X7R 0.1UF/10V,X7R
VCCSUS3_3[12] L26
AD41 VCCME[3] VCCSUS3_3[13] J28
C420 C421 C422 C423 VCCSUS3_3[14] J26
AF43 VCCME[4] VCCSUS3_3[15] H28
10uF/6.3V,X5R 10uF/6.3V,X5R 1uF/10V,X7R 1uF/10V,X7R H26
VCCSUS3_3[16]
AF41 VCCME[5] VCCSUS3_3[17] G28
VCCSUS3_3[18] G26
AF42 VCCME[6] VCCSUS3_3[19] F28
VCCSUS3_3[20] F26
V39 VCCME[7] VCCSUS3_3[21] E28
E26

Clock and Miscellaneous

VCCSUS3_3[22] +V3.3AL
V41 VCCME[8] VCCSUS3_3[23] C28
VCCSUS3_3[24] C26
V42 B27 +V1.05S
VCCME[9] VCCSUS3_3[25]

1
VCCSUS3_3[26] A28
Y39 A26 D37
VCCME[10] VCCSUS3_3[27] 1N4148WS
Y41 U23 SOD323
VCCME[11] VCCSUS3_3[28] +V5AL

2
Y42 VCCME[12] VCCIO[56] V23

C F24 R571 10 R0603 C

V5REF_SUS
V9 C541 +V3.3S
DCPRTC
C428 +V1.8S 1uF/10V,X7R
0.1UF/10V,X7R K49
V5REF

1
AU24 VCCVRM[3]

PCI/GPIO/LPC
D38
C429 J38 C542 +V5S
VCCADPLLA VCC3_3[8] 1N4148WS
BB51 VCCADPLLA[1] SOD323
1uF/10V,X7R BB53 L38 1uF/10V,X7R +V3.3S
VCCADPLLA[2] VCC3_3[9]

2
R572 10 R0603
+V1.05S M36
VCCADPLLB VCC3_3[10]
BD51 VCCADPLLB[1]
BD53 VCCADPLLB[2] VCC3_3[11] N36

AH23 VCCIO[21] VCC3_3[12] P36

AJ35 VCCIO[22]
+V1.05S AH35 U35 C451 C450
C436 C435 C434 VCCIO[23] VCC3_3[13] 0.1UF/10V,X7R 0.1UF/10V,X7R
1uF/10V,X7R 1uF/10V,X7R 1uF/10V,X7R AF34
FB33 1 VCCADPLLA VCCIO[2]
2 FB0603 VCC3_3[14] AD13
120ohm@100MHz,500mA AH34 +V1.05S
VCCIO[3]

C430 C431 AF32 VCCIO[4]

AK3 FB35 1 2 FB0603 ns
10uF/6.3V,X5R 1uF/10V,X7R VCCSATAPLL[1] 120ohm@100MHz,500mA
V12 DCPSST VCCSATAPLL[2] AK1

C437 C445 C446

0.1UF/10V,X7R Y22 10uF/6.3V,X5R 1uF/10V,X7R
DCPSUS ns ns
VCCIO[9] AH22
+V1.05S C438
0.1UF/10V,X7R +V1.8S
P18 VCCSUS3_3[29] VCCVRM[4] AT20
FB34 1 2 FB0603 VCCADPLLB
120ohm@100MHz,500mA +V3.3AL U19 VCCSUS3_3[30]
SATA

+V1.05S
PCI/GPIO/LPC

B VCCIO[10] AH19 B
C432 C433 U20 VCCSUS3_3[31]
VCCIO[11] AD20
10uF/6.3V,X5R 1uF/10V,X7R U22 VCCSUS3_3[32] FB36 1
VCCIO[12] AF22 2 FB0603
120ohm@100MHz,500mA
C439 +V3.3S AD19
0.1UF/10V,X7R VCCIO[13]
V15 VCC3_3[5] VCCIO[14] AF20 C452
VCCIO[15] AF19
V16 AH20 1uF/10V,X7R
VCC3_3[6] VCCIO[16]
Y16 VCC3_3[7] VCCIO[17] AB19
C440 AB20
0.1UF/10V,X7R +V1.05S VCCIO[18]
VCCIO[19] AB22
AD22 +V1.05S
VCCIO[20]
AT18 V_CPU_IO[1]
AA34
CPU

C441 VCCME[13] +V3.3AL

VCCME[14] Y34
4.7UF/10V,Y5V C442 AU18 Y35
C0805 0.1UF/10V,X7R V_CPU_IO[2] VCCME[15]
VCCME[16] AA35

PCH_EC_RTC
RTC

A12 VCCRTC VCCSUSHDA L30

HDA

C443 IbexPeak-M_Rev1_0
0.1UF/10V,X7R C453
1uF/10V,X7R

A A

TOPSTAR TECHNOLOGY
Joseph
Page Name N10M PCIE&PWR&GND
Size Project Name Rev
C C49
A
Date: Friday, May 07, 2010 Sheet 30 of 59
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5 4 3 2 1
 5 4 3 2 1

U4I
AY7 VSS[159] VSS[259] H49
B11 VSS[160] VSS[260] H5
U4H B15 J24
VSS[161] VSS[261]
AB16 VSS[0] B19 VSS[162] VSS[262] K11
B23 VSS[163] VSS[263] K43
AA19 VSS[1] VSS[80] AK30 B31 VSS[164] VSS[264] K47
AA20 VSS[2] VSS[81] AK31 B35 VSS[165] VSS[265] K7
AA22 VSS[3] VSS[82] AK32 B39 VSS[166] VSS[266] L14
AM19 VSS[4] VSS[83] AK34 B43 VSS[167] VSS[267] L18
AA24 VSS[5] VSS[84] AK35 B47 VSS[168] VSS[268] L2
AA26 VSS[6] VSS[85] AK38 B7 VSS[169] VSS[269] L22
D
AA28 VSS[7] VSS[86] AK43 BG12 VSS[170] VSS[270] L32 D
AA30 VSS[8] VSS[87] AK46 BB12 VSS[171] VSS[271] L36
AA31 VSS[9] VSS[88] AK49 BB16 VSS[172] VSS[272] L40
AA32 VSS[10] VSS[89] AK5 BB20 VSS[173] VSS[273] L52
AB11 VSS[11] VSS[90] AK8 BB24 VSS[174] VSS[274] M12
AB15 VSS[12] VSS[91] AL2 BB30 VSS[175] VSS[275] M16
AB23 VSS[13] VSS[92] AL52 BB34 VSS[176] VSS[276] M20
AB30 VSS[14] VSS[93] AM11 BB38 VSS[177] VSS[277] N38
AB31 VSS[15] VSS[94] BB44 BB42 VSS[178] VSS[278] M34
AB32 VSS[16] VSS[95] AD24 BB49 VSS[179] VSS[279] M38
AB39 VSS[17] VSS[96] AM20 BB5 VSS[180] VSS[280] M42
AB43 VSS[18] VSS[97] AM22 BC10 VSS[181] VSS[281] M46
AB47 VSS[19] VSS[98] AM24 BC14 VSS[182] VSS[282] M49
AB5 VSS[20] VSS[99] AM26 BC18 VSS[183] VSS[283] M5
AB8 VSS[21] VSS[100] AM28 BC2 VSS[184] VSS[284] M8
AC2 VSS[22] VSS[101] BA42 BC22 VSS[185] VSS[285] N24
AC52 VSS[23] VSS[102] AM30 BC32 VSS[186] VSS[286] P11
AD11 VSS[24] VSS[103] AM31 BC36 VSS[187] VSS[287] AD15
AD12 VSS[25] VSS[104] AM32 BC40 VSS[188] VSS[288] P22
AD16 VSS[26] VSS[105] AM34 BC44 VSS[189] VSS[289] P30
AD23 VSS[27] VSS[106] AM35 BC52 VSS[190] VSS[290] P32
AD30 VSS[28] VSS[107] AM38 BH9 VSS[191] VSS[291] P34
AD31 VSS[29] VSS[108] AM39 BD48 VSS[192] VSS[292] P42
AD32 VSS[30] VSS[109] AM42 BD49 VSS[193] VSS[293] P45
AD34 VSS[31] VSS[110] AU20 BD5 VSS[194] VSS[294] P47
AU22 VSS[32] VSS[111] AM46 BE12 VSS[195] VSS[295] R2
AD42 VSS[33] VSS[112] AV22 BE16 VSS[196] VSS[296] R52
AD46 VSS[34] VSS[113] AM49 BE20 VSS[197] VSS[297] T12
AD49 VSS[35] VSS[114] AM7 BE24 VSS[198] VSS[298] T41
AD7 VSS[36] VSS[115] AA50 BE30 VSS[199] VSS[299] T46
AE2 VSS[37] VSS[116] BB10 BE34 VSS[200] VSS[300] T49
AE4 VSS[38] VSS[117] AN32 BE38 VSS[201] VSS[301] T5
AF12 VSS[39] VSS[118] AN50 BE42 VSS[202] VSS[302] T8
Y13 VSS[40] VSS[119] AN52 BE46 VSS[203] VSS[303] U30
AH49 VSS[41] VSS[120] AP12 BE48 VSS[204] VSS[304] U31
AU4 VSS[42] VSS[121] AP42 BE50 VSS[205] VSS[305] U32
AF35 VSS[43] VSS[122] AP46 BE6 VSS[206] VSS[306] U34
AP13 VSS[44] VSS[123] AP49 BE8 VSS[207] VSS[307] P38
C AN34 VSS[45] VSS[124] AP5 BF3 VSS[208] VSS[308] V11 C
AF45 VSS[46] VSS[125] AP8 BF49 VSS[209] VSS[309] P16
AF46 VSS[47] VSS[126] AR2 BF51 VSS[210] VSS[310] V19
AF49 VSS[48] VSS[127] AR52 BG18 VSS[211] VSS[311] V20
AF5 VSS[49] VSS[128] AT11 BG24 VSS[212] VSS[312] V22
AF8 VSS[50] VSS[129] BA12 BG4 VSS[213] VSS[313] V30
AG2 VSS[51] VSS[130] AH48 BG50 VSS[214] VSS[314] V31
AG52 VSS[52] VSS[131] AT32 BH11 VSS[215] VSS[315] V32
AH11 VSS[53] VSS[132] AT36 BH15 VSS[216] VSS[316] V34
AH15 VSS[54] VSS[133] AT41 BH19 VSS[217] VSS[317] V35
AH16 VSS[55] VSS[134] AT47 BH23 VSS[218] VSS[318] V38
AH24 VSS[56] VSS[135] AT7 BH31 VSS[219] VSS[319] V43
AH32 VSS[57] VSS[136] AV12 BH35 VSS[220] VSS[320] V45
AV18 VSS[58] VSS[137] AV16 BH39 VSS[221] VSS[321] V46
AH43 VSS[59] VSS[138] AV20 BH43 VSS[222] VSS[322] V47
AH47 VSS[60] VSS[139] AV24 BH47 VSS[223] VSS[323] V49
AH7 VSS[61] VSS[140] AV30 BH7 VSS[224] VSS[324] V5
AJ19 VSS[62] VSS[141] AV34 C12 VSS[225] VSS[325] V7
AJ2 VSS[63] VSS[142] AV38 C50 VSS[226] VSS[326] V8
AJ20 VSS[64] VSS[143] AV42 D51 VSS[227] VSS[327] W2
AJ22 VSS[65] VSS[144] AV46 E12 VSS[228] VSS[328] W52
AJ23 VSS[66] VSS[145] AV49 E16 VSS[229] VSS[329] Y11
AJ26 VSS[67] VSS[146] AV5 E20 VSS[230] VSS[330] Y12
AJ28 VSS[68] VSS[147] AV8 E24 VSS[231] VSS[331] Y15
AJ32 VSS[69] VSS[148] AW14 E30 VSS[232] VSS[332] Y19
AJ34 VSS[70] VSS[149] AW18 E34 VSS[233] VSS[333] Y23
AT5 VSS[71] VSS[150] AW2 E38 VSS[234] VSS[334] Y28
AJ4 VSS[72] VSS[151] BF9 E42 VSS[235] VSS[335] Y30
AK12 VSS[73] VSS[152] AW32 E46 VSS[236] VSS[336] Y31
AM41 VSS[74] VSS[153] AW36 E48 VSS[237] VSS[337] Y32
AN19 VSS[75] VSS[154] AW40 E6 VSS[238] VSS[338] Y38
AK26 VSS[76] VSS[155] AW52 E8 VSS[239] VSS[339] Y43
AK22 VSS[77] VSS[156] AY11 F49 VSS[240] VSS[340] Y46
AK23 VSS[78] VSS[157] AY43 F5 VSS[241] VSS[341] P49
AK28 VSS[79] VSS[158] AY47 G10 VSS[242] VSS[342] Y5
G14 VSS[243] VSS[343] Y6
IbexPeak-M_Rev1_0 G18 Y8
VSS[244] VSS[344]
B
G2 VSS[245] VSS[345] P24 B
G22 VSS[246] VSS[346] T43
G32 VSS[247] VSS[347] AD51
G36 VSS[248] VSS[348] AT8
G40 VSS[249] VSS[349] AD47
G44 VSS[250] VSS[350] Y47
G52 VSS[251] VSS[351] AT12
AF39 VSS[252] VSS[352] AM6
H16 VSS[253] VSS[353] AT13
H20 VSS[254] VSS[354] AM5
H30 VSS[255] VSS[355] AK45
H34 VSS[256] VSS[356] AK39
H38 VSS[257] VSS[366] AV14
H42 VSS[258]

IbexPeak-M_Rev1_0

A A

TOPSTAR TECHNOLOGY
Joseph
Page Name N10M PCIE&PWR&GND
Size Project Name Rev
C C49
A
Date: Friday, May 07, 2010 Sheet 31 of 59
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5 4 3 2 1
 5 4 3 2 1

All of by-pass capacitors must be closed to IC

+V3.3S {6,8,14,15,16,22,23,24,25,26,27,28,29,30,33,34,35,36,37,38,40,41,42,43,47,48,49,50,51,5

REG18V
+V3.3AL {6,22,23,24,25,27,28,30,34,35,36,37,41,42,43,44,45,46,47,48,49,50,51,54,56}

D3.3V
D3.3V
REG18V VDD18
+V3.3AL D3.3V
+V3.3AL
R243 R244 0 R0402 ns
D C191 30K R245 0 R0402 IT1337E-48 PIN MUX D

REG18V
0.1UF/25V,Y5V C190

DGND

DGND
R0402 PINs
C0402 C192 2.2uF/10V,X7R C193 SM/xD SD/MMC MS
RST 4.7uF/10V,X5R C0805 0.1UF/25V,Y5V 05 SM_WPSW SD_CMD MS_BS
U7 C194 C0805 C0402
4.7uF/10V,X5R 06 SM_RD MS_INS

36
35
34
33
32
31
30
29
28
27
26
25
C0805
07 SM_RNB SD_CD

REG18Vout

REG33Vout
SM/SD/MS D7

SM/SD/MS D6

SM/SD/MS D5

VSS
REG33Vin

GPIO6

GPIO5
TC

GPIO1
GPIO4
08 SM_D0 SD_D0 MS_D0
+V3.3AL PWR_SW2
09 SM_D1 SD_D1 MS_D1
PWR_SW2
11 SM_D2 SD_D2 MS_D2
37 24 C195 C197 18 SM_D3 SD_D3 MS_D3
Clk12M-out 38 GPIO7 REG5Vin 2.2uF/10V,X7R C196
Clk12M_out GPIO0/LED 23 1uF/10V,X7R
SM_CE 39 22 C0805 0.1UF/25V,Y5V C0603 22 SM_D4 SD_D4 MS_D4
SM_WP SM_CE/SD_WP SM/SD/MS D4 RST
40 SM_WP/SD_CLK/MS_CLK RST 21 C0402
DGND 41 20 29 SM_D5 SD_D5 MS_D5
VSS GPIO3 ClkSel
42 SM_WR IT1337E-48 ClkSel 19
EE_SDA 43 18 SM_D3 32 SM_D6 SD_D6 MS_D6
EE_SCL EE_SDA SM/SD/MS D3 PWR_SW2
44 EE_CLK SD/MS/xD SM_CD 17
SM_WP_SW/SD_CMD/MS_BS
D3.3V 45 16 34 SM_D7 SD_D7 MS_D7
D3.3V AVDD33 SM_ALE
{27} USB_CR_PP8 46 DP PWR_SW 15
C {27} USB_CR_PN8 47 DM VDD33 14 D3.3V 39 SM_CE SD_WP C
DGND 48 13 DGND
AVSS VSS C198 40 SM_WP SD_CLK MS_CLK
0.1UF/25V,Y5V
SM_RNB/SD_CD
SM_RD/MS_INS

C0402 SM_WP R246 0 R0402 SD_CLK

SM/SD/MS D0
SM/SD/MS D1

SM/SD/MS D2
SM_CLE
Clk48M
XTALO

xD_CD

VDD18
XTALI

+V3.3S

IT1337E-48
1
2
3
4
5
6
7
8
9
10
11
12

QFPS48_0D5_1D6
CLK_CR_48M
SM_WPSW

SM_RNB

3IN1 CONN
SM_RD

SM_D0
SM_D1

SM_D2
VDD18

C199
XTALI

VDD18 0.01uF/25V,X7R
C0402

use 48Mhz crystal　 J2A PWR_SW2

SM_D2 2
ClkSel R247 0 SM_D3 DAT2_SD
3 DAT3_SD VDD_SD 6
R0402 SM_WPSW 4 CMD_SD C201
SD_CLK 7 SD+MMC C200 1uF/10V,X7R
CLK_SD 0.1uF/10V,X7R C0603
B B
CLK_CR_48M {24} SM_D0 9 8
SM_D1 DAT0_SD VSS_SD2
10 DAT1_SD
SM_RNB 1 5
SM_CE CD_SD# VSS_SD1
11 WP_SD#
use 12Mhz crystal　
D3.3V 3IN1
PWR_SW2
R248 0 Clk12M-out Int-12MHz J2B
R0402 SD_CLK 14 13
C202 CLK_MS VCC_MS
EEprom Setting
0.1UF/25V,Y5V XTALI SM_D3 15
U8 C0402 SM_RD DAT3_MS MS
16 INS_MS
1 8 ns SM_D2 17 12 C204
A0 VCC SM_D0 DTA2_MS VSS_MS1 C203 1uF/10V,X7R
2 A1 WP 7 18 DTA0_MS VSS_MS2 21
3 6 EE_SCL SM_D1 19 22 0.1uF/10V,X7RC0603
A2 SCL EE_SDA SM_WPSW DTA1_MS GND1
4 VSS SDA 5 20 BS_MS GND2 23

S-24CS02AFJ-TB-G R249 R250 3IN1

SO8_50_150 0 0
ns R0402 R0402
ns
S0=P12=EEP_SDA
S1=P13=EEP_SCK
TOPSTAR TECHNOLOGY
A A
Joseph
Page Name Cardreader(ITE1337)
Size Project Name Rev
Custom C49
A
Date: Friday, May 07, 2010 Sheet 32 of 59
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5 4 3 2 1
 5 4 3 2 1

+V3.3S {6,8,14,15,16,22,23,24,25,26,27,28,29,30,32,34,35,36,37,38,40,41,42,43,47,48,49,50,51,53,54,55,56}
+V3.3S
+V5S {22,24,26,30,34,36,38,40,41,42,49,50,53,54}
VCC5CDC +V5S
FB10
600ohm@100MHz,1.5A
1 2FB0805

C205 C206 C207 C208 C209 C210 C211

10UF/6.3V,X5R 10UF/6.3V,X5R
0.1UF/25V,Y5V 0.1UF/25V,Y5V C0805 0.1UF/25V,Y5V 0.1UF/25V,Y5V C0805 0.1UF/25V,Y5V

U9 Cross moat place

25
38
1
9
GND_AUD
VerA:Reserve +1.5S power rail for GM C212 4.7uF/10V,X5R

VDD1
VDD2

AVDD1
AVDD2
T31 C0805
ICTP ns A_GPIO0 2 35 CT1 ns R254 75 R0402 SURR_OUT_L
GPIO0 FRONT-OUT-L SURR_OUT_L {41}

+
T32 ct6032 100uF/10V
ICTP ns A_GPIO1 3 36 CT2 ns R255 75 R0402 SURR_OUT_R
GPIO1 FRONT-OUT-R SURR_OUT_R {41}

+
ct6032 100uF/10V
D D
37 C213 4.7uF/10V,X5R
LINE1-VREFO-R C0805
C214 0.1UF/25V,Y5V
VREF 27
C218 C0805
GND_AUD
11 28 VREFOUT 10UF/6.3V,X5R
{23} AZALIA_CODEC_RST# REST# MIC1-VREFO-L R256 4.7K R0402 INT_MIC_L_R
{23} AZALIA_CODEC_BITCLK 6 BITCLK
LINE1-VREFO-L 29
{23} AZALIA_CODEC_SYNC 10 SYNC
30 MIC2_REF
MIC2-VREFO MIC2_REF {41}
{23} AZALIA_CODEC_SDOUT 5 SDOUT
LINE2-VREFO 31
R257 33 8
{23} AZALIA_SDATAIN0 SDIN
32 R258 4.7K R0402 INT_MIC_L_R
MIC1-VREFO-R ns
R259 51K R0402 C219 1uF/10V,X7R 12 33 R260 10K ns
{42} BTL_BEEP PC-BEEP DCVOL VCC5CDC
C0603
JACK_DET_A 13 34 JACK_DET_B
JD1 JD2

{23} SPKR
R261 75K R0402 C220 1uF/10V,X7R C221 14 LINE2-L
ALC662 CEN-OUT 43
C0603
100pF/50V,NPO 15 44
LINE2-R LFE-OUT
R262 R263 MIC2_L R264 75 R0402 C222 4.7uF/10V,X5R C0805 16 45
{41} MIC2_L MIC2-L SIDESURR-OUT-L
4.7K 4.7K
MIC2_R R266 75 R0402 C223 4.7uF/10V,X5R C0805 17 46
{41} MIC2_R MIC2-R SIDESURR-OUT-R
All of JD resistors should be
placed as close as possible to ICTPT33 ns 18 47 EAPD R268 0 R0402 SHUTDOWN#
CD-L SPDIFI/EAPD ns
the sense pin of codec. ICTPT34 ns 20 48
CD-R SPDIFO
INT_MIC_L C225 1uF/10V,Y5V C0603 21 MIC1-L AMP_OUT_L
SURR-OUT-L 39
C224 1uF/10V,Y5V C0603 22
JACK_DET_B R269 5.11K,1% R0402 ns MIC1-R R270 20K,1%
JDREF 40 GND_AUD
23 LINE1-L
C JACK_DET_A R271 5.11K,1% R0402 HP_DET 41 AMP_OUT_R C
HP_DET {41} SURR-OUT-R

CD-GND
VerA:follow the DEMO design in MIC1&MIC2 071108 24

AGND1
AGND2
LINE1-R

GND1
GND2
R272 20K,1% ns MIC1_JD
MIC1_JD {41}
JACK_DET_B R273 20K,1%
QFPS48_0D5_1D6 ALC662

4
7

19

26
42
connecr mic1_jd to senseB
and reserved route to senseA
By Johan 071224

T35 GND_AUD
ICTP
ns

INT_MIC_L_R

FB15 FB0805
INT_MIC_L R274
+
1K 1 2 1
300ohm@100MHz,1.5A 2

1
D17 C231
ESDPAD_R0603 MIC1
EGA1-0603-V05 100pF/50V,NPO Microphone
ns C0402 BZ_D6027
VCC5CDC VCC5CDC
2
ASSY SURR_OUT_L GND_AUD SURR_OUT_R GND_AUD
PQ1 PQ2 PQ3 PQ4
GAIN0 GAIN1 Av(inv)

3
2N7002 2N7002 2N7002 2N7002
SOT23 SOT23 SOT23 SOT23
0 0 6dB R275 R276
B 10K 10K AMP_SHDW1 AMP_SHDW1 B
0 1 10dB GND_AUD 1 1
ns
1 0 15.6dB GAIN0 INPUT:STEREO MIC-IN

2
GAIN1
1 1 21.6dB OUTPUT:CENT/LFE
R277 R278 onboard stereo
10K 10K
ns
microphone VCC5CDC

GND_AUD GND_AUD U10 R279

TPA6017A2 10K
sop20_0d65_4d4g
AMP_OUT_R C0603 R280 20K 17 18 +INTSPR
RIN- ROUT+ +INTSPR {41}
C232 0.22uF/10V,X7R SHUTDOWN#
7 14 -INTSPR
RIN+ ROUT- -INTSPR {41}

3
FB16 1 2FB0805 ns C233
300ohm@100MHz,1.5A 0.47uF/25V,Y5V R281 10K 9 4 +INTSPL Q11
GND_AUD LIN+ LOUT+ 2N7002
C0603
C234 0.22uF/10V,X7R 10 8 -INTSPL VCC5CDC 1
BYPASS LOUT- {42} AMP_SHDW
C235 0.1UF/25V,Y5V C0603 R283
ns AMP_OUT_L C0603 R282 20K 5 16 100K
LIN- VDD

2
C236 0.22uF/10V,X7R 12 6 R284
NC PVDD1 C237 10K
PVDD2 15
SHUTDOWN# 19 1 0.1UF/10V,X7R SOT23
SHDWN# GND1 C239 4.7uF/10V,Y5V
GND_AUD GND2 11
GAIN0 2 13 C238 C0805
GAIN0 GND3 0.1UF/10V,X7R
GND4 20
GAIN1 3 21 GND GND_AUD
GAIN1 GND5

先断开GND和GND_AUD,从一博回来后再开桥连上
GND_AUD
INTSPK1
INT_spkR 2Pin
A CNS2_V A
4 +INTSPL
4 2 2
GND_AUD
3 1 -INTSPL
3 1
TOPSTAR TECHNOLOGY
Joseph
Page Name AZALIA(ALC883)
Size Project Name Rev
C C49
A
Date: Friday, May 07, 2010 Sheet 33 of 59
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5 4 3 2 1
 5 4 3 2 1

H3 H1 H2
+V1.05S {23,24,25,28,29,30,48,54,55,56}
+V3.3S {6,8,14,15,16,22,23,24,25,26,27,28,29,30,32,33,35,36,37,38,40,41,42,43,47,48,49,50,51,53,54,55,56}
+V5S {22,24,26,30,33,36,38,40,41,42,49,50,53,54}
+V3.3AL {6,22,23,24,25,27,28,30,32,35,36,37,41,42,43,44,45,46,47,48,49,50,51,54,56}
+V1.1S_VTT {8,10,11,48,49,53}
+V1.5S {35,37,54}
FAN CPU_HOLE_2 CPU_HOLE_2
ns PM H4
TH_230_132_118_6 TH_220_132_118_6 TH_220_132_118_6

FAN

1
2
3
4
5
6
7

1
2
3
4
5
6
7

1
2
3
4
5
6
7
TH_220_132_118_6
D D

1
2
3
4
5
6
7

1
2
3
4
5
6
7

1
2
3
4
5
6
7
GM

+V5S +V3.3AL +V3.3S

1
2
3
4
5
6
7
R298 R299

1
2
3
4
5
6
7
R297 10K 10K
10K ns

ns
FAN_BACK {42}

3
R302 1K FAN_TACH_ON 1 Q14
2N2222 R304
C243 ns SOT23
0

2
ns
+V5S 1000pF/50V,X7R

ns
Q15
BCP69-16 Vfan
CPUFAN1
SOT223 4
3 2 1 1 4 4
2 2

1
C244 3 5
R306 D18 C245 3 5

1
1K R307 0.1UF/25V,Y5V 10uF/10V,Y5V CONN3_V
1N4148WS

2
1
TCM 10
R0603 R308 SOD323
C1206 CNS3_V
FAN_FB

1
+V3.3S VCC_358 5.11K,1%

1
C246

2
+V3.3S U11 R310 U12A
C 1K 0.1UF/25V,Y5V LM358 C

8
22 10 R311 0 so8_50_150 Shut-Down
{23,37,42} LPC_FRAME# LFRAME# VDD1
16 19 R0805 TCM 3 +V3.3S
{8,17,27,35,37,41,42} BUF_PLT_RST# LRESET# VDD2 +

2
{27} CLK_TCMPCI 21 LCLK VDD3 24 1

1
26 C247 C248 C249 2 Throttling/
{23,37,42} LPC_AD0 LAD0 -
23 4 0.1UF/25V,Y5V 0.1UF/25V,Y5V R313 Un-throttling
{23,37,42} LPC_AD1 LAD1 GND1
R320R312 R309 20 11 10uF/6.3V,X5R TCM TCM R314
{23,37,42} LPC_AD2 LAD2 GND2

4
10K 10K 10K 17 18 TCM C250 10K,1% 4.7K
{23,37,42} LPC_AD3 LAD3 GND3
TCM ns TCM 27 25 R0402
{23,42} INT_SERIRQ SERIRQ GND4

2
PM_CLKRUN# 15 0.1UF/25V,Y5V
LPCPD# CLKRUN# R315 R316
28 LPCPD# NC 1 High-5V
LPCPD# 2 1 100K 2
NC1 FAN1_V {42}
5 200K R0402
LPCPP NC2
9 BA0 NC3 6 Middle-4V
3 BA1 NC4 8
NC5 12
PM_CLKRUN# LPCPP 7 13 Low-3V
PP NC6
C252
R317 R318 14 C251
10K 10K NC-P FAN1_V=3.30V,Vfan=5V 4.7UF/10V,Y5V 0.1uF/25V,Y5V
TCM TCM C0805 C0402
TCM
FAN1_V=2.65V,Vfan=4V 50 55 60 65 70 75 80 85 90 95 100
C253
SOP28_0D65_6D1 FAN1_V=1.98V,Vfan=3V
1uF/10V,X7R
C0603
TCM

+V1.05S

R319
B B
10K

SHDN_LOCK#
SHDN_LOCK# {51}
3

R322 10K 5 2
{8,28} THERMTRIP#
Q16
C254 MMDT3904
4

R324 1000pF/50V,X7R SC70_6

100K
3

Q17
2N7002E-T1
{42} ALT_ON 1

Use for temperature alarm driver.

2

R328
100K

A VerA:Delete GMCH_TEMP signal and components 071026 A

Shut Down PCB PCBA

VIN
CPU R20 MB R20 PCBA
8VCC_358

TOPSTAR TECHNOLOGY
Throttling on
THRMTRIP# SHDN#
PCB PCBA U12B Joseph
AND LM358 Page Name
CPU Temperature MDC&BT/FAN/OTP
THERM_ALERT# so8_50_150
Throttling Off 5 Size
+ Project Name Rev
VDC 0 85 90 95 100 7 C C49
Thermal (Degree) A
6 -
sensor Date: Friday, May 07, 2010 Sheet 34 of 59
PROPERTY NOTE: this document contains information confidential and property to
4

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5 4 3 2 1
 5 4 3 2 1

PCIE_NUT3
Hole+Dowel

+V3.3S {6,8,14,15,16,22,23,24,25,26,27,28,29,30,32,33,34,36,37,38,40,41,42,43,47,48,49,50,51,53,54,55,56}
+V3.3AL {6,22,23,24,25,27,28,30,32,34,36,37,41,42,43,44,45,46,47,48,49,50,51,54,56}
+V1.5S {37,54}

+DATA4

D -DATA4 D
+V3.3S +V3.3AL +V3.3S

1
D39 D40
ESDPAD_R0603 ESDPAD_R0603
EGA1-0603-V05 EGA1-0603-V05 R647
ns ns 0

2
R0603 R648 R649 R644
ns 0 0 0 +V1.5S
R0603 R0603 R0603
ns
+V3.3S_PCIE +V3.3AL_PCIE

MPCIE2
MINIPCIE_l6

52

24

48
28
2

6
Keep USB2.0 Signal stub short

+3.3VAUX
+3.3V0
+3.3V1

+1.5V0
+1.5V1
+1.5V2
R645 0 R0402 +V3.3S +V3.3AL
R646 0 R0402

CHK11
90ohm@100M0.33A
l4_0805 ns ICTP R650 R651
3 4 -DATA4 36 46 ns 10K 10K
{27} MINICARD_USB_PN1 USB_D- LED_WPAN# T162
2 1 +DATA4 38 44 R0402 R0402
{27} MINICARD_USB_PP1 USB_D+ LED_WLAN# Wireless_LED# {43}
42 ns ns
LED_WWAN# T163
ICTP R674 0 R0402 MiniPCIE_REQ1#_R
CL_RST1# {24}
C ns ns C
11 22 R673 0 R0402 minicard_Wake#
{24} CLK_PCIE_MINICARD# REFCLK- PERST# BUF_PLT_RST# {8,17,27,34,37,41,42}

PCIE mini Card

13 1 minicard_Wake# R652 0 R0402 ns
{24} CLK_PCIE_MINICARD REFCLK+ WAKE# PCIE_WAKE# {25,37,41,42}
7 MiniPCIE_REQ1#_R R653 0 R0402 ns
CLKREQ# minicard_CLKREQ# {24}

{24} PCIE_TXN4_WLAN 31 PETN0

33 32 R654 0 R0402 ns
{24} PCIE_TXP4_WLAN PETP0 SMB_DATA CL_DATA1 {24}
30 R655 0 R0402 ns
SMB_CLK CL_CLK1
+V3.3AL {24}

{24} PCIE_RXN4_WLAN 23 PERN0

{24} PCIE_RXP4_WLAN 25 PERP0 T49 ICTP ns
CHANNEL_CLK 5
T55 ICTP ns
CHANNEL_DATA 3
ns ICTP T23 R0402
17 RESERVED0
ns ICTP T22 10K
19 RESERVED1 R657
+V3.3AL 20 R660 0 R0402
+V3.3S RESERVED_DISABLE HW_RATIO_OFF# {42}
R108 0 37
R104 0 R0603 R0603 RESERVED_PCIE0
39 RESERVED_PCIE1
R53 0 41 16 ns
RESERVED_PCIE2 RESERVED_SIM0 T164
ns 43 14 R664 ICTP
0 R0402 ns
RESERVED_PCIE3 RESERVED_SIM1 PWR_SW_VCC2 {41,42,46}
R0603 45 12 R666 0 R0402 ns
RESERVED_PCIE4 RESERVED_SIM2 EC_DEBG_UTXD {42}
47 10 R668 0 R0402 ns
RESERVED_PCIE5 RESERVED_SIM3 EC_DEBG_URXD {42}
49 8 ns
RESERVED_PCIE6 RESERVED_SIM4 T165
51 ICTP
RESERVED_PCIE7

GND10
GND11
GND12
GND13
GND14
GND15
GND16
GND17
GND18
GND19
GND20
B B
GND0
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9 +V3.3S_PCIE +V3.3AL_PCIE

C454 C455 C456 C457

PCIE MINI CARD 10UF/6.3V,X5R 0.1UF/25V,Y5V 10UF/6.3V,X5R 0.1UF/25V,Y5V
9
15
21
27
29
35
4
18
26
34
40
50
53
54
56
57
58
59
60
61
55
C0805 C0402 C0805 C0402

ns R284,R295,R337,R341, Install R283

For chang PCIE SPEC to 1.1
Swain 081104

+V1.5S

C458 C459 C460 C461 C462

10UF/6.3V,X5R 0.1UF/25V,Y5V 0.1UF/25V,Y5V 0.1UF/25V,Y5V 0.1UF/25V,Y5V
C0805 C0402 C0402 C0402 C0402

A A
TOPSTAR TECHNOLOGY
Joseph
Page Name
PCIE MINI SLOT 1
Size Project Name Rev
A3 C49
A
Date: Friday, May 07, 2010 Sheet 35 of 59
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5 4 3 2 1
 5 4 3 2 1

AD+ {41,44,46}
+V5S {22,24,26,30,33,34,38,40,41,42,49,50,53,54}
+V3.3S {6,8,14,15,16,22,23,24,25,26,27,28,29,30,32,33,34,35,37,38,40,41,42,43,47,48,49,50,51,53,54,55,56}
+V3.3AL {6,22,23,24,25,27,28,30,32,34,35,37,41,42,43,44,45,46,47,48,49,50,51,54,56}
+V3.3S +V3.3S +V3.3S +V3.3GPU {17,20,21,38,55}

R670 R669
4.7K ns 4.7K
R661 R656
4.7K 4.7K DDC_EN GM/HDMI TMS_EN
ns
R671 R658
0 0

DDCBUF_EN
ns
GM/HDMI

CFG
D GND GND D
GM/HDMI
+V3.3S

C516 C517
0.01uF/25V,X7R 0.01uF/25V,X7R

GM/HDMI GM/HDMI +V5_HDMI

GND +V5_HDMI

5VDDCDA_HDMI
5VDDCCK_HDMI
DDCBUF_EN R672

HDMIHP_C
+V3.3S R706 2.2K
DDC_EN

TMS_EN
2.2K
CFG

5VDDCCK_HDMI
C518 C519 5VDDCDA_HDMI
0.01uF/25V,X7R 0.01uF/25V,X7R GM/HDMI
GM/HDMI GM/HDMI
G7
G6

G5
G4
36
35
34
33
32
31
30
29
28
27
26
U25 25
g7
g6
GND7
FUNCTION4
FUNCTION3
VCC3V5
DDC_EN
GND6
HPD_SINK
SDA_SINK
SCL_SINK
GND5
VCC3V4
TMDS_EN
g5
g4
GM/HDMI GND
GND G1
g1
gnd10 49
37 GND8 GND4 24
38 23 IFPC_TXD2P C520 C521
{26} IN_D2+ IN_D1- OUT_D1-
39 22 IFPC_TXD2N 0.01uF/25V,X7R 0.01uF/25V,X7R
{26} IN_D2- IN_D1+ OUT_D1+
40 VCC3V6 VCC3V3 21
41 20 IFPC_TXD1P
{26} IN_D1+ IN_D2- OUT_D2-
42 19 IFPC_TXD1N
{26} IN_D1- IN_D2+ OUT_D2+
43 18 GM/HDMI GM/HDMI
GND9 GND3 IFPC_TXD0P
{26} IN_D0+ 44 IN_D3- OUT_D3- 17
45 16 IFPC_TXD0N
{26} IN_D0- IN_D3+ OUT_D3+
ANALOG1(REXT)

46 VCC3V7 VCC3V2 15
IFPC_TXC
HPD_SOURCE

47 14
SDA_SOURCE
SCL_SOURCE

{26} MCH_CLK_D4+ IN_D4- OUT_D4-

48 13 IFPC_TXC#
FUNCTION1
FUNCTION2

{26} MCH_CLK_D4- IN_D4+ OUT_D4+ +V3.3S

ANALOG2

g2 G2
VCC3V1

C G3 C
VCC3V

g3
GND1

GND2
gnd18
GND

Note:The ESD protection devices should be placed as

close to the HDMI connector as
1
2
3
4
5
6
7
GM_HDMI_DDC_DATA 8
9
10
11
12
G8

CH7318 possible so that when ESD strikes occur, the

GND discharges can be quickly absorbed or
GM_HDMI_DDC_CLK

diverted to the ground/power plane before it is

GND
PC0
PC1

coupled to another signal path nearby.

C522
GM/HDMI 0.01uF/25V,X7R
+V3.3S GND R161 0 R0603
R162 0 R0603
intel demo 499 and chro demo 1.2k by homy 1029 HDMI +V5_HDMI
GU9
GM/HDMI CHK2HDMI
l4_0805 ns +V5S
+V3.3S 4 3 100M0.33A IFPC_TXD6P_esd 1 10 IFPC_TXD6P_esd
{20} IFPC_TXD2P LINE_1 NC4 HDMI_CON1 FB9
R659 1 CHK3 2 IFPC_TXD6N_esd 2 9 IFPC_TXD6N_esd D4
{20} IFPC_TXD2N LINE_2 NC3
R890 GND_HDMI GC171 0.1uF/10V,X7R 3 8 1 1 2 1 2120ohm@100MHz,500mA
1.2K 499,1% IFPC_TXD5P_esd C0402 VDD GND IFPC_TXD5P_esd D2+
4 3 4 7 2
{26}

{20} IFPC_TXD1P
MCH_HDMI_HPD

CH7318 PS8101 IFPC_TXD5N_esd LINE_3 NC2 IFPC_TXD5N_esd D2 SHTELD 1N5819HW-F FB0603

{20} IFPC_TXD1N 1 2 HDMI 5 LINE_4 NC1 6 3 D2-
4 SOD123 C181 R164
D1+ 0.1UF/25V,Y5V 100K
100M0.33A AZ1045
5 D1 SHTELD
R163
0 R0603 6 HDMI C0402 R0402
l4_0805 HDMI D1- HDMI
GND R165 0 R0603 IFPC_TXD4P_esd 7 20
GND ns HDMI D0+ GND1
8 D0 SHTELD GND2 21
Colay 8101 and 7318 by xiezx HDMI IFPC_TXD4N_esd 9 HDMI
R166 0 R0603 IFPC_TXC_esd D0- HDMI
10 CK+
R167 0 R0603 11 22 GND_HDMI GND_HDMI
IFPC_TXC#_esd CK SHTELD GND3
HDMI GU10 12 CK- GND4 23
CHK4HDMIl4_0805 13
IFPC_TXD4P_esd CEC
{20} IFPC_TXD0P 4 3 100M0.33A 1 LINE_1 NC4 10 14 RESERVED
1 ns IFPC_TXD4N_esd 5VDDCCK_HDMI
{20} IFPC_TXD0N CHK5 2 2 LINE_2 NC3 9 15 SCL
GND_HDMI GC172 0.1uF/10V,X7R 3 8 +V5_HDMI 5VDDCDA_HDMI 16
IFPC_TXC_esd C0402 VDD GND SDA GND_HDMI
{20} IFPC_TXC 4 3 4 LINE_3 NC2 7 17 DCC/CEC_GND
1 2 IFPC_TXC#_esd HDMI 5 6 18
{20} IFPC_TXC# LINE_4 NC1 +5V
HDMIHP_C 19 HP_DET
100M0.33A
R168 0 R0603 AZ1045 HDMI_CON
l4_0805
R169 0 R0603 HDMI
Colay 8101 and 7318 by xiezx +V3.3S +V3.3S HDMIns HDMI
B HDMI B
GND_HDMI GND_HDMI
Colay COMCHK with 0ohm
R662 R663
4.7K 4.7K R667 R665
ns PS8101 2.2K 2.2K +V5_HDMI
GM/HDMI GM/HDMI
PC0

GM_HDMI_DDC_DATA {26}

3
R170
GM_HDMI_DDC_CLK {26}
PC1 R0402 R0402 0 D6 R171
R0402 BAT54A 0
+V3.3GPU +V3.3GPU PM/HDMI ns R0402 GND_HDMI
1 PM/HDMI

2
change 4.7k to 2.2k 080508 hads
先断开GND和GND_HDMI,从一博回来后再开桥连上
R930 GR55
4.7K 4.7K R172
1

CH7318 R0402 4.7K

PM/HDMI PM/HDMI

2 3 5VDDCCK_HDMI
{20} HDMI_DDC_CLK
GND PM/HDMI
BSS138 C182
GQ1 10pF/50V,NPO
C0402 +V3.3GPU
R173 0 R0402 PM/HDMI
ns

GND_HDMI GR56
10K +V3.3AL
+V3.3GPU +V3.3GPU R0402

GPU_HDMI_HPD {21,42}
GR57 R174 PM/HDMI
4.7K 4.7K GQ3 GQ4 GR58
1

3
R0402 PM/HDMI 2N7002 2N7002 1K
A PM/HDMI SOT23 SOT23 R0402 A

2 3 5VDDCDA_HDMI HDMIHP_C R456 1K 1 1

{20} HDMI_DDC_DATA
PM/HDMI

100pF/50V,NPO
PM/HDMI GR59 GC173 GR60
PM/HDMI

2
BSS138 C183 100K 10K
GQ2 10pF/50V,NPO R0402 C0402 R0402
C0402 TOPSTAR TECHNOLOGY
R175 0 R0402 PM/HDMI PM/HDMI PM/HDMI Joseph
ns
Page Name HDMI CONN
PM/HDMI
GND_HDMI GND_HDMI GND_HDMI Size
PM/HDMI PM/HDMI Project Name Rev
A2 C49
A
Date: Friday, May 07, 2010 Sheet 36 of 59
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5 4 3 2 1
 5 4 3 2 1

+V3.3S {6,8,14,15,16,22,23,24,25,26,27,28,29,30,32,33,34,35,36,38,40,41,42,43,47,48,49,50,51,53,54,55,56}
+V1.5S {35,54}
+V3.3AL {6,22,23,24,25,27,28,30,32,34,35,36,41,42,43,44,45,46,47,48,49,50,51,54,56}
+VDC {22,44,46,47,48,49,50,53,54,55}
MPCIE_NUT1 MPCIE_NUT2
Hole+Dowel Hole+Dowel

3G 3G

+DATA8

-DATA8
+V3.3S +V3.3AL +V3.3AL

1 1 +V3.3S +V3.3AL
D19 D20
EGA10603V05A1-B EGA10603V05A1-B R332 R329 R333
ESDPAD_R0603 ESDPAD_R0603 0 0 0
ns ns R0603 R0603 R0603 +V1.5S
D 2 2 ns 3G 3G D
R677 R678
3.3PCIE2 3.3ALPCIE2 10K 10K
ns ns
MPCIE1
MINIPCIE_D
Keep USB2.0 Signal stub short

52

24

48
28
2

6
3G
minicard_CLKREQ#_R

+3.3V0
+3.3V1

+3.3VAUX

+1.5V0
+1.5V1
+1.5V2
R679 0 3G WAKE#
R680 0 3G

CHK12
{27} MINICARD_USB_PN2 3 4 -DATA8 36 46 T166 ns
+DATA8 38 USB_D- LED_WPAN# T167 ns
{27} MINICARD_USB_PP2 2 1 USB_D+ LED_WLAN# 44
ns 42
90ohm@100M0.33A LED_WWAN# T168 ns
l4_0805
{24} CLK_PCIE_3G# 11 REFCLK- PERST# 22 BUF_PLT_RST# {8,17,27,34,35,41,42}
{24} CLK_PCIE_3G 13 1 WAKE# R681 0 ns
REFCLK+ WAKE# PCIE_WAKE# {25,35,41,42}

PCIE mini Card

7 minicard_CLKREQ#_RR684 0 ns
CLKREQ# MiniPCIE_REQ# {24}

{24} PCIE_TXN2_3G 31 PETN0

33 32 R682 0 ns
{24} PCIE_TXP2_3G PETP0 SMB_DATA SMB_DATA_S {6,14,15,24}
30 R683 0 ns SIM_PWR R347 8.2K SIM_DATA
SMB_CLK SMB_CLK_S {6,14,15,24}
R0402

1
23 D21
{24} PCIE_RXN2_3G PERN0
25 ESDPAD_R0603
{24} PCIE_RXP2_3G PERP0

1
5 EGA1-0603-V05 C463 C259 D22
CHANNEL_CLK ns 0.1UF/25V,Y5V C260 100pF/50V,NPO ns
CHANNEL_DATA 3

2
+VDC R675 0 R0402 ns 17 C0402 1uF/10V,X7R C0402
R695 0 R0402 Debug RESERVED0
{8,17,27,34,35,41,42} BUF_PLT_RST# 19 C0603
RESERVED1

2
3G
R697 0 R0402 3G 20 R685 0 3G 3G 3G
RESERVED_DISABLE HW_RATIO_OFF_3G# {42}
R687 0 R0402
Debug 37
{27} PCI_CLK_DEBUG RESERVED_PCIE0
PICE_39 39
R688 0 R0402 3G RESERVED_PCIE1 R689 0 SIM_VPP
41 RESERVED_PCIE2 RESERVED_SIM0 16
R676 0 R0402 Debug 43 14 SIM_REST R690 R691 SIMCONN1
{23,34,42} LPC_FRAME# RESERVED_PCIE3 RESERVED_SIM1
C R698 0 R0402 Debug 45 12 SIM_CLK 10K 10K SIM_PWR C1 C
{23,34,42} LPC_AD0 RESERVED_PCIE4 RESERVED_SIM2 VCC1
R696 0 R0402 Debug 47 10 SIM_DATA ns 3G SIM_REST C2 G1
{23,34,42} LPC_AD1 RESERVED_PCIE5 RESERVED_SIM3 RESET HOLE0
R686 0 R0402 Debug 49 8 SIM_PWR SIM_CLK C3 G2
{23,34,42} LPC_AD2 RESERVED_PCIE6 RESERVED_SIM4 CLK HOLE1
R699 0 R0402 Debug 51
{23,34,42} LPC_AD3 RESERVED_PCIE7

1
D42 C332 C5
+V3.3S 0.1UF/25V,Y5V SIM_VPP GND
C6 VPP

1
+V3.3AL C0402 D23 ns SIM_DATA C7
ns IO
GND10
GND11
GND12
GND13
GND14
GND15
GND16
GND17
GND18
GND19
GND20
GND21
GND22
GND23
GND24
GND25
GND26
GND27

2
GND0
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9

ns C331 CD CD

1
3G ns 47pF/50V,NPO
D41

2
+V3.3AL R700 0 R0603 PICE_39 C0402 SIMCON
+V3.3S R701 0 R0603 ns PCIE MINI CARD ns
9
15
21
27
29
35
4
18
26
34
40
50
53
54
56
57
58
59
60
61
55
62
63
64
65
66
67
68

R401 3G

2
56
R0402
ns

ns SIM card periphery current

许沐锌 081222

+V1.5S
Add Option for 3G card
Swain 080820
3.3PCIE2 3.3ALPCIE2

C468 C469 C470 C471 C472 C473 C474 C475

1uF/10V,X7R 0.1UF/25V,Y5V 0.1UF/25V,Y5V 0.1UF/25V,Y5V 10UF/6.3V,X5R 0.1UF/25V,Y5V 1uF/10V,X7R 0.1UF/25V,Y5V
C0603 C0402 C0402 C0402 C0805 C0402 C0603 C0402
3G 3G 3G 3G 3G 3G 3G 3G

B B

A A

TOPSTAR TECHNOLOGY
Joseph
Page Name
USB Port
Size Project Name Rev
A2 C49 A
Date: Friday, May 07, 2010 Sheet 37 of 59
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5 4 3 2 1
 5 4 3 2 1
+V3.3S {6,8,14,15,16,22,23,24,25,26,27,28,29,30,32,33,34,35,36,37,40,41,42,43,47,48,49,50,51,53,54,55,56}
+V5S {22,24,26,30,33,34,36,40,41,42,49,50,53,54}
CRT INTERFACE +V3.3GPU {17,20,21,36,55}

S46P VerB:staff this BAV99 to

Cross moat place
D Place close to VGA port
improve ESD protection
+V5S Cross moat place
D
VGA CONNECTOR
+V5_VGA
IFB1
R692
PM 0 47ohm/100MHz,500mA ID1 IFB2
GR231 0 1FB0603 2 ROUT 1 2 1 2
{20} CRT_RED
GND_VGA
R330

3
R0603 1N5819 120ohm@100MHz,500mA
IR1 ID2 SOD123 FB0603 IR2 CONNECTOR
{26} CRT_RED_R IC1
150,1% BAT54SPT IC2 100K TOP VIEW
GM 5.6pF/50V,NPO 0.1UF/25V,Y5V VGA1

17
0 IC23 IC3 SOT23
VGADMF
5.6pF/50V,NPO 5.6pF/50V,NPO

2
ns GND_VGA GND_VGA 6 GND
IFB3 GND_VGA NV suggest:2pf 1 R NC
11
R693
0 47ohm/100MHz,500mA GND_VGA+V5_VGA 7 GND
GR232 0 PM NV suggest:22pf 1FB0603 2 GOUT 2 G SDA
12 5VDDCDA
{20} CRT_GREEN

3
8 GND
R0603 ID3 3 B HSYNC 13 HSYNC
IR3 IC24 IC4 IC5 BAT54SPT 9 NC
{26} CRT_GREEN_R
R327 150,1% SOT23 4 NC VSYNC 14 VSYNC
GM 5.6pF/50V,NPO 5.6pF/50V,NPO 5.6pF/50V,NPO 10 GND
0 ns 5 GND CLK
15 5VDDCCK

2
shell
shell
GND_VGA GND_VGA+V5_VGA IC6 IC7 IC8 IC9
R694

16
0 C10518-11505-L 15PF/50V,NPO 15PF/50V,NPO 15PF/50V,NPO 15PF/50V,NPO
GR233 0 PM 1 2 IFB4 FB0603 BOUT D_Bot
{20} CRT_BLUE
47ohm/100MHz,500mA ns ns

3
R0603 IC10 IC11
IR4 ID4 ESD:
150,1% 5.6pF/50V,NPO 5.6pF/50V,NPO BAT54SPT
{26} CRT_BLUE_R
IC25 SOT23 NV suggest use +3.3V
C R326 0 GM
5.6pF/50V,NPO Layout note: GND_VGA S46/修改成跟M21一致的VGA Conn。LJ081223 GND_VGA
C

2
ns 1. +3.3V and GND Route >15mils trace width
GND_VGA
GND_VGA +V5_VGA 2. No more than 75mils
3. ESD diode should no more than 10pf cap.
150ohm电阻前走线阻抗50ohm
(From GPU to CONN)

+V5_VGA +V5_VGA
+V3.3GPU +V3.3S

IC12 IC13
0.1UF/25V,Y5V 0.1UF/25V,Y5V Cross moat place
GND_VGA +V5_VGA

R931 R176
R336
GND_VGA GND_VGA GM 8.2K 8.2K
R0402 R0402
{26} CRT_DDC_DATA_R

0
reserved ciucuit possibility to Cost down 1G125 follow design guide--0929 PM GM IR5 IR6
+V5_VGA Q9 2.2K 2.2K +V5_VGA
VerC: Del VR7 ID6
BSS138
SOT23 2
R928
R331
2 3 5VDDCDA 3
{20} CRT_DDC_DATA VerC: Change to bat54s
{26} CRT_HSYNC_R IC15 IC16
IU1 PM
B 0 GM 74AHCT1G125
SOT23_5
0.1UF/25V,Y5V 0.1UF/25V,Y5V 0 +V3.3GPU +V3.3S
R932
GM
0 +V3.3S
1
B
BAT54SPT

1
1 OE# VCC 5 R335
SOT23 GND_VGA
GR229 0 PM 2 GND_VGA R0402 VerB:BAV99由DIODES改为PHILIPS的
{20} CRT_HSYNC A {26} CRT_DDC_CLK_R R924 for cost down
R923 R177 +V3.3GPU
3 4 CRT_H_SYNC Near U5/U6 ASAP GM 8.2K 8.2K +V5_VGA071016
GND Y 0 VerC: Change to bat54s R0402 R0402 Q10
ID7
BSS138
IU2 IR7 39 HSYNC SOT23 0
2
74AHCT1G125 R0402
SOT23_5 IR8 39 VSYNC R929 PM GM 2 3 PM 5VDDCCK 3
{20} CRT_DDC_CLK
1 OE# VCC 5
PM 1
GR230 0 PM 0
{20} CRT_VSYNC 2 A
BAT54SPT

1
3 4 CRT_V_SYNC GND_VGA
GND Y SOT23
+V3.3S
R925
R0402
R334 GM GND_VGA
{26} CRT_VSYNC_R
+V5_VGA IH1 GM
0 +V3.3GPU
0 R926
2

VSYNC 3 IC14
0.1UF/25V,Y5V
HOLE 0
1
1

ID5 TH_240_92 R0402

ns PM
BAT54SPT GND_VGA
SOT23 Demo has no voltage lever shifter

A ID8
+V5_VGA
GND_VGA
A
2 TOPSTAR TECHNOLOGY
IC17 Joseph
HSYNC 3 0.1UF/25V,Y5V
Page Name CRT Interface
1
Size Project Name Rev
Custom C49
BAT54SPT A
GND_VGA
Date: Friday, May 07, 2010 Sheet 38 of 59
PROPERTY NOTE: this document contains information confidential and property to
SOT23 TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR

5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A
TOPSTAR TECHNOLOGY
Joseph
Page Name EXPRESS CARD
Size Project Name Rev
A3 C49
A
Date: Friday, May 07, 2010 Sheet 39 of 59
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5 4 3 2 1
 5 4 3 2 1

+V5S {22,24,26,30,33,34,36,38,41,42,49,50,53,54}
+V3.3S {6,8,14,15,16,22,23,24,25,26,27,28,29,30,32,33,34,35,36,37,38,41,42,43,47,48,49,50,51,53,54,55,56}
+V5AL {22,30,41,46,47,48,51,54}

D D
SATAHDD_B1 SATAHDD_B2

+V3.3S

FB17 0 R0805
V3.3_SATA
ns
CT3 4.7uF/10V,Y5V C294 C295
C0805 0.1UF/25V,Y5V 0.1UF/25V,Y5V Screw 2*8mm Screw 2*8mm
ns ns ns

ASSY ASSY

+V5S
Average 1A,Peak 1.5A
FB18 0 R0805
V_HDD SATA_HDD1

{23} SATA_TXP0 2 TX
CT4 4.7uF/10V,Y5V C296 C297 0.01uF/25V,X7R 3 1
{23} SATA_TXN0 TX# GND0
C0805 0.1UF/25V,Y5V 0.1UF/25V,Y5V C298 C0402 5 4
{23} SATA_RXN0 RX# GND1
V3.3_SATA C299 C0402 6 7
{23} SATA_RXP0 RX GND2
0.01uF/25V,X7R
8 VCC3_0 GND3 11
9 VCC3_1 GND4 12
V_HDD 10 13
VCC3_2 GND5
14 VCC5_0 GND6 17
15 VCC5_1
+V5S 16 19
VCC5_2 GND7
18
FB19 0 R0805 Average 1A,Peak 1.5A REEVE
23
V_ODD GND23
20 VCC12_0 GND24 24
21 VCC12_1
CT5 4.7uF/10V,Y5V C300 C301 22
C0805 0.1UF/25V,Y5V 0.1UF/25V,Y5V VCC12_2

SATA_HDD CONN
C C

SATAODD_B1 SATAODD_B2

Screw 2*8mm Screw 2*8mm

SATA_CON1
ASSY ASSY
S1 GND1
{23} SATA_TXP1 S2 A+
{23} SATA_TXN1 S3 A- GND6 14
S4 GND2
C302 0.01uF/25V,X7R S5
{23} SATA_RXN1 B-
C303 0.01uF/25V,X7R S6
{23} SATA_RXP1 B+
S7 GND3
V_ODD
P1 DP
P2 +5V_1
P3 +5V_2
P4 MD GND7 15
B
P5 GND4 B
P6 GND5

sata_con

VerB:change the footprint the same as S46P

USB_+V5AL

USB4 CHK8
USB_+V5AL S2 1 2 FUSE 1.1A +V5AL 4 90ohm@100MHz,0.5A
FUSE1812 VCC1 L4_0805
5 HOLE0
6 3 -DATA9 1 2 ns
100uF/10V,TAN

sis use 10K resistor HOLE1 -DATA1 USB_PN9 {27}

7 2 +DATA9 4 3
330PF/50V,X7R

HOLE2 +DATA1 USB_PP9 {27}

C135 C137 CT7 8
100uF/10V,TAN

R339 300K R0402 HOLE3

+ + USB_OC#4 {27} GND 1
C0402

1
CT7343_28 CT6032
ns
Cost down Vih_ttl>=2V
USB_8
USB1F
D27
ESDPAD_R0603
D36
ESDPAD_R0603 R343 0 R0603
C136
R789 Vil_ttl<=0.8V 620700400002 EGA1-0603-V05 EGA1-0603-V05
560K 1000pF/50V,X7R ns ns R344 0 R0603

2
Co-layout CT31-CT6032 R0402 ns
C0402

A A
Keep USB2.0 Signal stub short

TOPSTAR TECHNOLOGY
Joseph
Page Name SATA HDD&ODD
Size Project Name Rev
C C49
A
Date: Friday, May 07, 2010 Sheet 40 of 59
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5 4 3 2 1
 5 4 3 2 1
+V5S {22,24,26,30,33,34,36,38,40,42,49,50,53,54}
+V3.3AL {6,22,23,24,25,27,28,30,32,34,35,36,37,42,43,44,45,46,47,48,49,50,51,54,56}
+V5AL {22,30,40,46,47,48,51,54}
+VDC {22,37,44,46,47,48,49,50,53,54,55}
AD+ {44,46}
+V3.3S {6,8,14,15,16,22,23,24,25,26,27,28,29,30,32,33,34,35,36,37,38,40,42,43,47,48,49,50,51,53,54,55,56}

D Touch_Button Conn Usb_Audio Conn D

+V3.3S +V5AL
USB_AUDIO_CONN1
1 1
2 2
C333 C138 3
1000pF/50V,X7R 3
4 4
C0402 1uF/10V,X7R 5
{27} USB_PP11 5
{27} USB_PN11 6 6
1 1 7 7
2 2 {27} USB_PP10 8 8
3 3 9 9 {27} USB_PN10 9 9
4 4 10 10
{42} C49_switch1 5 5 {27} USB_OC#5 11 11
6 6 8 8 12 12 25 25
{42} C49_switch2 7 7 {33} MIC2_R 13 13 26 26
{33} MIC1_JD 14 14
CNS7_0D5_RA1 15
Conn 6Pin {33} MIC2_L 15
{33} MIC2_REF 16 16
TP_CON2 17 17
{33} SURR_OUT_R 18 18
{33} HP_DET 19 19
{33} SURR_OUT_L 20 20
21 21
{33} -INTSPR 22 22
{33} +INTSPR 23 23
24 24

C 24pin 0.5mm bot FFC C

Touch pad Conn +V3.3AL +V5S +V3.3AL +V5S

PWRCONN1&LANCONN1
PWRCONN1
R383 R384 AD+ 1 1
1

1
Q20 10K Q21 10K 2 2
2N7002E-T1 R0402 2N7002E-T1 R0402 3 3 10 10
ns ns ns ns 4 4
TPCLK 2 3 TP_TPCLK_R TPDAT 2 3 TP_TPDAT_R 5 5 +V3.3AL R982 0 +V3.3_LAN
{42} TPCLK {42} TPDAT
6 6 9 9
7 7 +V3.3S R983 0 ns
TR1 0 R0402 TR2 0 R0402 8 8
CNS8_V
Conn 8Pin

+V3.3S +V3.3_LAN

LANCONN1
B R385 LEFT 1 1
B
1K 2
R0402 2
3 4 3 3
4 4
3
C306 5
{24} PCIE_TXP1_LAN 5
D31 6
{24} PCIE_TXN1_LAN 6
100pF/50V,NPO 7 21
7 21
1 2 {24} PCIE_RXP1_LAN 8 8
TLSW1 BAT54SPT 9
{24} PCIE_RXN1_LAN 9
TMG-534-V 10 10
1

1 +V5S BUTTON4_S 11
1 {24} CLK_PCIE_GLAN 11
2 TP_TPDAT_R 12
2 {24} CLK_PCIE_GLAN# 12
7 3 TP_TPCLK_R +V5S 13 22
7 3 13 22
4 4 {8,17,27,34,35,37,42} BUF_PLT_RST# 14 14
8 5 LEFT 15
8 5 {25,35,37,42} PCIE_WAKE# 15
6 RIGHT 16
6 {42,43} POWERLED# 16
{22,42} LIDR# 17 17
{44,52} Isense_SYSP 18 18
CNS6_1_R1 19
Conn 6Pin {35,42,46} PWR_SW_VCC2 19
R0402 R386 RIGHT 20
TP_CON1 1K 20
+V3.3AL
VerB:converse the connection of TP_CON1 3 4 20pin 0.5mm bot FFC
3

+V5S C307 D32

100pF/50V,NPO 1 2 BAT54SPT
TRSW1
A C308 C309 R387 R388 TMG-534-V TOPSTAR TECHNOLOGY A
1

47K 47K C310 BUTTON4_S

0.1UF/25V,Y5V C0603 R0402 R0402 C0402 Joseph
C0402 1UF/10V,Y5V ns ns 0.1UF/25V,Y5V +V5S Page Name USB2.0&&LED CONN&Qkey CONN
Add pull res ns
Size Project Name Rev
TPDAT A3 C49
A
TPCLK Date: Friday, May 07, 2010 Sheet 41 of 59
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
 5 4 3 2 1

+V3.3S +V5S
+V3.3S {6,8,14,15,16,22,23,24,25,26,27,28,29,30,32,33,34,35,36,37,38,40,41,43,47,48,49,50,51,53,54,55,56}
+V3.3AL {6,22,23,24,25,27,28,30,32,34,35,36,37,41,43,44,45,46,47,48,49,50,51,54,56}
+V5S {22,24,26,30,33,34,36,38,40,41,49,50,53,54}
R389 Q22
8.2K 2N7002E-T1 EC_V3.3AL

1
C313
R0402 10UF/6.3V,X5R C314 C315 C316 C317 C318
R390 C0805
2 3 A20GATE 0 +V3.3AL 0.1UF/25V,Y5V 0.1UF/25V,Y5V 0.1UF/25V,Y5V 0.1UF/25V,Y5V 0.1UF/25V,Y5V
{28} H_A20GATE
ns FB20 R0805
EC Output Signal! 120ohm/100MHz,500mA
1 2FB0603 EC_V3.3AL 1 2 V18R

D33 1 1N4148WS
Should have a 0.1uF capacitor close to every GND-VCC pair + one
SOD323 C319 larger cap on the supply.
C320 C321 0.1UF/25V,Y5V C322
+V3.3S +V5S C0402 1uF/10V,X7R
0.1UF/25V,Y5V
0.1UF/25V,Y5V C0603
Q23 Vin>=1.5V turn on the cup FAN. HDD_ZOUT R391 10K

V18R
2N7002E-T1 HDD_YOUT R392 10K
1

D R393 HDD_XOUT R394 10K D

10K ns

124

111

125
2 3 RCIN#

67

96
33
22
{28} H_RCIN#

9
U14
EC Output Signal!

V18R

AVCC

VCC
VCC
VCC
VCC
VCC
VCC
D34 1 1N4148WS
SOD323 63 SYS_I_Sense
AD0/GPI38 SYS_I_Sense {52}
HDD_ZOUT

ADC
64 +V3.3AL
A20GATE AD1/GPI39 HDD_YOUT CHG_ON R395 10K
1 GA20/GPIO00 AD2/GPI3A 65
RCIN# 2 66 HDD_XOUT ALW_PWROK need move to other
KBRST#/GPIO01 AD3/GPI3B place.pin110&111 follow the

MSIC
20 SCI#/GPIO0E
{28} EC_RUNTIME_SCI# EC_RESET#37 sequence of R18EC
ECRST#
EC Input Signal! C323 change to DG
SYS_I_Sense By Johan 071224
R396 0 EC_BUF_PLT_RST# 12 21
{8,17,27,34,35,37,41} BUF_PLT_RST# {27} CLK_591PCI PCICLK PWM0/GPIO0F BTL_BEEP {33}
SPI_CS#

PWM
3 23 R397 10K
{23,34} INT_SERIRQ SERIRQ PWM1/GPIO10 POWERLED# {41,43} 3300pF/50V,X7R
R0402 4 25 EC_SPI_MOSI R398 10K
{23,34,37} LPC_FRAME# LFRAME# PWM2/GPIO11 SET_I {52} swap for DG C0402
10 34 EC_SPI_MISO R399ns 10K
{23,34,37} LPC_AD0 LAD0 PWM3/GPIO19 EC_BKLT_PWM {22} By Johan 071224
KBCON1 8 SPI_SCK R400ns 10K
{23,34,37} LPC_AD1 LAD1
ACES 85201-2602 +V3.3AL 7 ns

LPC
{23,34,37} LPC_AD2 LAD2
CNS26_1_R_2D5 5 ns
{23,34,37} LPC_AD3 LAD3
EC_PCI_RST# 13 28 EC_FAN_BACK 1 D35
PCIRST#/GPIO05 FANFB0/GPIO14 FAN_BACK {34}
CLKREQ

FAN
26 R403 38 29 1N4148WS
26 CLKRUN#/GPIO1D FANFB1/GPIO15 V3G_1.05G_ON {55}
25 4.7K R0402 CLKREQ 26 SOD323
25 FANPWM0/GPIO12 FAN1_V {34}
24 SCANOUT15 27 R404 1K R405 SM_BAT_SDA2 R406 5.6K
24 FANPWM1/GPIO13 Camera_ON {22}
23 SCANOUT10 R0402 100K
23 SCANOUT11 +V3.3AL SCANIN7 SM_BAT_SCL2 R407 5.6K
22 22 62 KSI7/GPIO37
21 SCANOUT14 SCANIN6 61
21 SCANOUT13 RN1 4.7K SCANIN5 KSI6/GPIO36 LIDR# R408 10K
20 20 60 KSI5/GPIO35
19 SCANOUT12 1 2 SCANIN0 SCANIN4 59
19 SCANOUT3 SCANIN1 SCANIN3 KSI4/GPIO34
18 18 3 4 58 KSI3/GPIO33
17 SCANOUT6 5 6 SCANIN2 SCANIN2 57 83
17 KSI2/GPIO32 PSCLK1/GPIO4A/P80CLK TPCLK {41}
16 SCANOUT8 7 8 SCANIN3 SCANIN1 56 84
16 KSI1/GPIO31 PSDAT1/GPIO4B/P80DAT TPDAT {41}
15 SCANOUT7 ns SCANIN0 55 85
15 KSI0/GPIO30/E51_TXD(ISP) PSCLK2/GPIO4C BT_PWRON {22}
14 SCANOUT4 RN2 4.7K 86
14 PSDAT2/GPIO4D HW_RATIO_OFF# {35}
SCANOUT2 SCANIN4 PCIE_WAKE#_EC

PS2
13 1 2 82 87 R412 10K
13 {55} V1.8G_1.5G_ON KSO17/GPIO49 PSCLK3/GPIO4E VGPU_ON {50}
12 SCANIN7 3 4 SCANIN5 R338 0 81 88
12 {25} AC_IN_PCH KSO16/GPIO48 PSDAT3/GPIO4F GPU_OVT# {21}
SCANOUT1 SCANIN6 SCANOUT15

KB3926
11 11 5 6 54 KSO15/GPIO2F/E51_RXD(ISP)
10 SCANOUT5 7 8 SCANIN7 SCANOUT14 53
10 SCANIN4 SCANOUT13 KSO14/GPIO2E
9 9 52 KSO13/GPIO2D
SCANIN5 SCANOUT12 ALT_ON

KB
8 ns 51 R417 10K ns
8 SCANOUT0 SCANOUT11 KSO12/GPIO2C
7 7 50 KSO11/GPIO2B EC_GPU_SML1DATA {21}
C 28 6 SCANIN2 SCANOUT10 49 +V3.3AL C
28 6 KSO10/GPIO2A EC_GPU_SML1CLK {21}
27 5 SCANIN3 SCANOUT9 48
27 5 SCANOUT9 SCANOUT8 KSO9/GPIO29
4 4 47 KSO8/GPIO28
SCANIN1 SCANOUT7 SML1DATA GPXIOA00

SMBUS
3 46 80 R418 10K
3 KSO7/GPIO27 SDA1/GPIO47 SML1DATA {24}
2 SCANIN0 SCANOUT6 45 79 SML1CLK
2 KSO6/GPIO26 SCL1//GPIO46 SML1CLK {24}
1 SCANIN6 SCANOUT5 44 78 R419 R420 R421
1 KSO5/GPIO25 SDA0/GPIO45 SM_BAT_SDA2 {45}
SCANOUT4 43 KSO4/GPIO24 SCL0/GPIO44 77 SM_BAT_SCL2 {45} Strap pin:Select SPI FLASH(pull Down) 10K 10K 10K Fuction P.M2 P.M1 P.M0
SCANOUT3 42 ns ns ns
SCANOUT2 KSO3/GPIO23/TP_ISP
41 KSO2/GPIO22/TP_ANA_TEST VerA 0 0 0
+V3.3AL Double confirmed SCANOUT1 40 PCB_Mark0
不用的pin上拉到+V3.3AL. By Johan 0711081231 KSO1/GPIO21/TP_PLL
SCANOUT0 39 KSO0/GPIO20/TP_TEST GPXIOA00/SDICS# 97 GPXIOA00 PCB_Mark1 VerB 0 0 1
98 PCB_Mark2
GPXIOA01/SDICLK CHG_LED# {43}
R422 10K ns EC_IMVP_ON
GPXIOA02/SDIMOSI 99 BTL_LED# {43} Verc 0 1 1
EC_IR_IN EC_PMSUSStat#

GPXIOA
R423 10K 6 GPIO04 100
GPXIOA03 PM_PWRBTN# {25}
R424 0 ns PCIE_WAKE#_EC
14 GPIO07/i_clk_8051 101 R425 R426 R427
{25,35,37,41} PCIE_WAKE# GPXIOA04 AMP_SHDW {33}
15 GPIO08/i_clk_peri 102 0 R455 10K 10K 10K
{21,44} AC_IN GPXIOA05 SYS_RST# {25}
16 GPIO0A/CIR_RX2 103 <Option>
{25,51} PM_RSMRST# GPXIOA06 CHG_ON {52}
R428 1K 17 GPIO0B/ESB_CLK 104 0 R459
{22,41} LIDR# GPXIOA07 EC_ME_LOCK# {23} change vera to verb hads
+V3.3AL PWRSW# R429 1K 18 GPIO0C/ESB_DAT_O/ESB_DAT_I 105
GPXIOA08 HW_RATIO_OFF_3G# {37}
19 GPIO0D 106 HW_OFF_BKLT#
{25,51} PM_SLP_S3# GPXIOA09 HW_OFF_BKLT# {22} BIU configuration should match flash speed used
{25,54} PM_SLP_S4# 32 GPIO18 GPXIOA10 107 AC_OFF {44}
R430 10K ns BT_PWRON R9581.5K,1% R0402 36 GPIO1A/NUMLED# 108
{8} CPU_VTT_PWG GPXIOA11 EC_GPU_RST# {17}
EC_IR_IN 73
R431 1K EC_IMVP_ON 74 GPIO40/CIR_RX LABEL1
GPIO

{53} IMVP_ON GPIO41/CIR_RLC_TX U15

{34} ALT_ON 89 GPIO50 Topstar Soft
127 GPIO59/TEST_CLKSPICLKI 109 SPI_CS# 1 8 VCC_SPI R432 0 EC_V3.3AL BIOS Ver: X.XX
{47} V1_5_ON GPXIOD0/SDIMISO C49_switch1 {41} CS# VCC
0 EC_PMSUSStat#
R433 110 EC_SPI_MISO 2 7 HOLD#1 R434 4.7K R0603 EC_V3.3AL
{25} PM_SUS_STAT# GPXIOD1 C49_switch2 {41} Q HOLD# EC Ver: X.XX
PCB_Mark0 EC_V3.3AL WP#1 SPI_SCK
GPXIOD
68 112 4.7K 3 6 R0402 XXXX年XX月XX日
{46} ALWAYS_ON GPO3C GPXIOD2 W# CLK
R436 70 GPO3D 114 PCB_Mark1 R435 R0402 VSS 4 5 EC_SPI_MOSI
{54} MAIN_ON GPXIOD3 VSS D
1K 71 GPO3E 115 PCB_Mark2 EC/BIOS Label
{48} V1_1S_VTT_ON GPXIOD4
{47} V0_75S_ON 72 GPO3F GPXIOD5 116 W25X80A ASSY
+V3.3AL 117 BATT_IN# {45}
GPXIOD6 BKLT_ON {22}
76 118 EC_BUF_PLT_RST# SOIC8_50_208
{53} IMVP_PWRGD GPI43 GPXIOD7
+V3.3AL 75
{25,51} MAIN_PWROK GPI42
R438 EC_SPI_MISO U16
MISO 119
PROCHOT# EC_SPI_MOSI VCC_SPI EC_SPI_MOSI
SPI

10K
90 E51CS#/GPIO52 MOSI 120 8 VDD SI 5
30 126 SPI_SCK 2 EC_SPI_MISO
{35} EC_DEBG_UTXD E51TXD/GPIO16 SPICLK/GPIO58 SO
ns AMP_SHDW 31 128 SPI_CS# WP#1 3 1 SPI_CS#
{35} EC_DEBG_URXD E51RXD/GPIO17/E51CLK change to DG SPICS# WP# CE#
R437 0 92 6 SPI_SCK
{21,36} GPU_HDMI_HPD E51TMR0/GPIO54/WDT_LED# By Johan 071224 SCK
93 HOLD#1 7
{50} VGACORE_PWRGD E51INT0/GPIO55/SCROLED# HOLD#
+V3.3AL R532 0 91 4 VSS
8051

E51TMR1/GPIO53/CAPSLED# VSS
{46} ALW_PWROK 95 E51INT1/GPIO56 XCLK32K/GPIO57 121 VTT_PWG {48,51}
EC_32XCLK1
CLK

122 W25X40 ns
XCLKI EC_32XCLK0 SO8_50_150
XCLKO 123
B EC_V3.3AL B
AGND

R970 10K ns PM_SLP_S3#

GND
GND
GND
GND
GND

R440
KB3926 10K
69

113
94
35
24
11

C324
4.7UF/10V,Y5V
R0402
VerB Colay tow roms
The 0ohm RES will across the isolate C0805 EC_RESET#
island of anolog GND and digital GND

{25} EC_IMVP_PWRGD R441

3
C326
1 Q25 R442
+V3.3S MMBT3904-F 0.01uF/16V,Y5V 0
R444 R0603 C0402 R0402
100

2
0 +V3.3AL
+V3.3AL R0402 ns
PM_SLP_S4# R445 4.7K R0402 R446
ns 10K
PM_SLP_S3# +V3.3AL R0402
R439 R447 4.7K R0402
10K ns
R0402 C329
R448 4.7K R0402 EC_BUF_PLT_RST# 0 R449 EC_PCI_RST#
C327 C328
PWRSW# R0402 EC_32XCLK0 R450 121K,1% C0402
100pF/50V,NPO 100pF/50V,NPO ns
R451
Y3 15pF/50V,NPO
3

10K

1
Q24 C325 R0402 32.768KHz
ns R452 xd3_2X6
3
1 10M ASSY
{35,41,46} PWR_SW_VCC2
2N7002E-T1C0402 R0402
2

R443 1000pF/50V,X7R
C330
2

1M EC_32XCLK1 C0402
R0402
15pF/50V,NPO

+V5S

Q26
1

2N7002E-T1
EC Input Signal!

A 2 3 PROCHOT# A
{8} EC_PROCHOT#

R453 0 ns

R454 0 R0603

TOPSTAR TECHNOLOGY
Joseph
Page Name KBC(PC87541L)
Size Project Name Rev
Custom C49
A
Date: Friday, May 07, 2010 Sheet 42 of 59
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5 4 3 2 1
 5 4 3 2 1

LED 物料要更改满足要求！
+V3.3S

+V3.3S {6,8,14,15,16,22,23,24,25,26,27,28,29,30,32,33,34,35,36,37,38,40,41,42,47,48,49,50,51,53,54,55,56}
Green color WIRELS1 BL-HGB35A-TRB
+V3.3AL {6,22,23,24,25,27,28,30,32,34,35,36,37,41,42,44,45,46,47,48,49,50,51,54,56}
2 1 R530 100
{35} WIRELESS_LED#
LED2_0805 R0402

D D
SATA_LED# ESD1 1 2 EGA1-0603-V05
ns ESDPAD_R0603
HDD1 BL-HGB35A-TRB
2 1 IDE+ R474 100 WIRELESS_LED# ESD2 1 2 EGA1-0603-V05
{23} SATA_LED#
Green color LED2_0805 R0402 ns ESDPAD_R0603

CHARGE_LED ESD3 1 2 EGA1-0603-V05

ns ESDPAD_R0603

C533 BAT_STATE_LED ESD4 1 2 EGA1-0603-V05

1000pF/50V,X7R C367 ns ESDPAD_R0603
C0402 1000pF/50V,X7R
C0402 PWR_LED ESD5 1 2 EGA1-0603-V05
ns ESDPAD_R0603

+V3.3AL

Red/Orange CHARGE1

R BAT_STATE_LED C370 1000pF/50V,X7R C0402

R477 100 R0603 CHARGE_LED 2 1 C371
{42} CHG_LED#
A 0.1UF/10V,X7R CHARGE_LED C372 1000pF/50V,X7R C0402
R478 R0603 BAT_STATE_LED 4
499,1% 3 C0402
{42} BTL_LED#
PWR_LED C373 1000pF/50V,X7R C0402

HA1GE33B AMB/GREEN
LED4_1210A
C POWER1 C
{41,42} POWERLED# R479 100 R0603 PWR_LED 2 1
BL-HGB35A-TRB
Green color LED2_0805

B B

A A

TOPSTAR TECHNOLOGY
Joseph
Page Name LED&Touch PAD&QuickButton
Size Project Name Rev
C C49 A
Date: Friday, May 07, 2010 Sheet 43 of 59
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5 4 3 2 1
 +VDC {22,37,46,47,48,49,50,53,54,55}
+V3.3AL {6,22,23,24,25,27,28,30,32,34,35,36,37,41,42,43,45,46,47,48,49,50,51,54
AD+ {41,46}
BATT+ {45,52}
EC_RTC {23,46}
AD++
PD6
SSM34PT
{52} Isense_SYSN
SMA
1
Co-lay. {41,52} Isense_SYSP
PD1 SBM54PT
18.5-19V/4A PQ5 1 SMB
AO4419 ns
SO8_50_150 PR1
AD+
4A 1 8 8 1 4A
2 7 7 2
3 6 6 3 0.025,1%
S 5 5 S R2512
PR2 D PQ6 D PR3
PC1 51K G AO4419 G 51K PC2
1000pF/50V,X7R R0402 SO8_50_150 R0402 0.01UF/25V,X7R PC3

4
C0402 C0402 0.1UF/25V,X7R
PD2 PD3
ns C0603
1 1

1N4148WS PR4 1N4148WS

AD+ SOD323 51K SOD323
R0402

VCC393
PR5 PQ7

3
PR6 51K 2N7002

8
10 R0402 SOT23
C+ 3 R0402
+
1 AC_OFF# 1
C- 2 -
PU1A 4A

2
LM393 PR7

4
SO8_50_150 51K
R0402 PC4
C0402
1000pF/50V,X7R

AD+ +V3.3AL

VDC1
PQ9 TestP
PD4 AP4407 ns
PR8 SSM34PT SO8_50_150 TPC60
3

75K SMA
R0402 PQ8 1
6A 1
2
8
7
2N7002 +VDC
3 6
SOT23
1 8 1 S 5 9V-19V/6A
9-12.6V/6A 7
6
2
3 G
D
2

PR9 BATT+ 5 S
AC_IN {21,42}

4
51K PQ10 D PR15
R0402 PR10 AP4407 G 51K
PR12 1K SO8_50_150 R0402

4
PC5 20K R0402
1000pF/50V,X7R R0402 PR14
C0402 PR11 51K
2K R0402
AD+ R0402 2 PR37
10 PR16
3 VCC393 R0402 100K
R0402 PR19
BATT+ 1 PR17 10K
PR13 PC6 0 R0402
PD5 10K 0.01uF/25V,X7R R0402

3
BAT54C R0402 C0402 PR24
SOT23 ns AD++ ns 15K,1%

3
PQ11 R0402
PR18 2N7002
0 R0402 1 PQ14
AC_OFF# ns SOT23 2N7002
PR20 1 SOT23
{51} SHDN#

2
51K
8
PR21 PR22 R0402

2
3
AD+ C+ 5 PR26 PR23
+
PR27 7 1 100K
3

2K,1% 49.9k,1% 15K,1% BATT+ C- C- 6 R0402 PR31

-
R0402 R0402 R0402 PU1B 300K 51K
PR28

2
PR25 LM393 R0402 PR36 PQ13 R0402 PC9
4

1 49.9k,1% 15K,1% C587 PC8 SO8_50_150 PR29 300K MMBT3904-F 1000pF/50V,X7R

{42} AC_OFF
PC7 R0402 R0402 51K R0402 SOT23 C0402
PQ12 0.01UF/25V,X7R 0.47uF/25V,Y5V
0.47uF/25V,Y5V R0402
2

1、执行battery learning时电池放电过程， 2N7002 C0402 ns ns

PR30 SOT23 ns
2、S0下，EC监测到电池过压信号， 10K
这两种情况，EC发出AC_OFF高电平信号。 PR38
0
R0402
ns TOPSTAR TECHNOLOGY
Joseph
EC_RTC
Page Name ADAPTER IN
Size Project Name Rev
A3 C49
A
Date: Friday, May 07, 2010 Sheet 44 of 59
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
 PC15
PFB1 0.1uF/25V,X7R
100ohm@100MHz,3A C0603
1 2
PC17
BATT+ {44,52}
FB0805 0.1uF/25V,X7R
AD+ {41,44,46}
PFB2 100ohm@100MHz,3A C0603
+V3.3AL {6,22,23,24,25,27,28,30,32,34,35,36,37,41,42,43,44,46,47,48,49,50,51,54,56}
1 2 ns
PC16 PF1
FB0805 0.1uF/25V,X7R 8A BATCON1
PFB3 C0603 ns FUSE1206
6A 1 2 1 2
6A 1 BATT+
BATT+
PC10 1000pF/50V,X7R 100ohm@100MHz,3A KEY
C0402 FB0805
SM_BAT_SDA2 PR32 100 SM_BAT_SDA 2 SDAT
{42} SM_BAT_SDA2
R0402
SM_BAT_SCL2 100 SM_BAT_SCL 3 SCLK
{42} SM_BAT_SCL2
PR33 R0402
4 TEMP

5 BAT_IN# +V3.3AL

6 GND +V3.3AL
BAT54SPT BAT54SPT
7 GND
6A BATT_CONN
2 2

SM_BAT_SDA2 3 SM_BAT_SDA 3 SM_BAT_SCL

+V3.3AL PC11 PC12
SM_BAT_SCL2 0.1uF/25V,Y5V 1 0.1uF/25V,Y5V 1
C0402 C0402
PZD1 PZD2
GND_BAT
PC13 PC14 PR34
5.6pF/50V,NPO 5.6pF/50V,NPO 300K
C0402 C0402 R0402

PR35 1K
BATT_IN# {42}
R0402

内层桥接走线,宽度保证有240mils.

GND_BAT

TOPSTAR TECHNOLOGY
Joseph
Page Name BATTERY IN
Size Project Name Rev
A3 C49
A
Date: Friday, May 07, 2010 Sheet 45 of 59
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
 5 4 3 2 1

+V3.3AL {6,22,23,24,25,27,28,30,32,34,35,36,37,41,42,43,44,45,47,48,49,5
+VDC {22,37,44,47,48,49,50,53,54,55}
AD+ {41,44}
+V5AL {22,30,40,41,47,48,51,54}
EC_RTC {23,44}

1.输入电容要靠近MOSFET漏极
2.MOS管尽量靠近IC芯片
+V3.3AL
D 3.芯片的Thermal D
GND用至少5个过孔连到信号地,用来散热
PR314 4.信号地和电源地在输出电容的负极连到一起
10K
GND_TPS51125
R0402
+VDC
{42} ALW_PWROK
+VDC
2A 2A
PR315 PR316
7.68K,1% 10K,1%
R0402 R0402
PC19 PC20 PC21 PC262 PC22 PC23 PC24 PC46
4.7uF/25V,X7R 0.1uF/25V,X7R 1000pF/50V,X7R 0.22uF/16V,X7R 1000pF/50V,X7R 0.1uF/25V,X7R 4.7uF/25V,X7R 10uF/ 25V,X7R
C1206 C0603 C0402 PR317 C0603 PR318 C0402 C0603 C1206 C1210
5.11K,1% ns
R0402 15K,1%
PR320 R0402
0

VREF
GND_TPS51125 PR319 ENTRIP1 R0402 ENTRIP1 GND_TPS51125
R0402
200K PR321
PC263
200K

1
EC_RTC R0402
10uF/6.3V,X5R

ENTRIP2

TONSEL

VREF

ENTRIP1
VFB2

VFB1
C0805
7 VO2 VO1 24
C C
+V3.3AL 8 +V5AL
7
6
5

5
6
7
8
PQ15 8 23 PQ16
V3.3A AO4468 PC264 VREG3 PGOOD PC265 AO4468 V5A

D
D
TestP SO8_50_150 0.1uF/25V,X7R 0.1uF/25V,X7R SO8_50_150 TestP
TPC60 4 C0603 9 22 4 TPC60
ns VBST2 VBST1 C0603 ns

G
G
PR51 PR52 PL2

S
S

PC32 PL1 PR54 2.2 R0402 10 PU2 21 2.2 R0402 5.2uH/5.5A

DRVH2 DRVH1
1
2
3

3
2
1
4.7uF/25V,X7R 3.3uH/4.8A 10K TPS51125 LS2_1051 PC36
5A C1206 LS2_8836 R0402
11 20
PR55
10K LL2
4.7uF/25V,X7R
C1206
5A
1 LL2 LL1 1
2

R0402
1

8
7
6
5

PR56
+ 2.2 12 19 PR57
D
1

R0805 PD29 DRVL2 DRVL1 2.2

SKIPSEL

5
6
7
8

2
ns 1N5819 4 PR58 0 PR60 R0805

VREG5
1

SOD123 0 ns

D
VCLK
G2 G1 +
1

GND

1
GND2 GND1

EN0

VIN
PQ17 R0402 R0402
S

PZ1 AO4468 4 PC38 PZ2

1
2
3

2
BZT52C3V6S-F/3.6 SO8_50_150 GND_TPS51125 1000pF/50V,X7R BZT52C5V6S-F/5.6

1
13

14

15

16

17

18

1
SOD323 PC31 PC33 PQ18 PD31 C0402 SOD323

S
1000pF/50V,X7R 220UF/6.3V,OSCON PC37 GND_TPS51125 AO4468 1N5819 ns

3
2
1
C0402 CAP6_6x7_3 1000pF/50V,X7R SO8_50_150 SOD123
C0402 PR322 PC35 PC34
ns 5A 0 PD7 220UF/6.3V,OSCON 1000pF/50V,X7R
R0402 +VDC VREG5
5A Co-lay. SSM34PT CAP6_6x7_3 C0402
SMA
ns
B PC266 PC267 B

VREF
1 PR323 0 R0402 EN0_AL 4.7uF/10V,X5R 10uF/6.3V,X5R
{35,41,42} PWR_SW_VCC2
PD8 ns C0805 C0805
1N4148WS PR324
SOD323 100K
2 R0402 PC268
{42} ALWAYS_ON
ns 0.022uF/16V,X7R
3 C0402 ns

AD+ 1 GND_TPS51125 GND_TPS51125 PR326

PD9 1K
PR65 PR66 BAT54C R0402
100K 15K PC41 SOT23 VREG5
R0402 R0402 0.1uF/25V,X7R PR325 ENTRIP1
C0603 0 R0402 PC269
ns 0.1uF/25V,Y5V
PR327 C0402
3

4.7K ns
R0402 PQ84
2N7002
1 SOT23
PR328 PC270
10K 0.1uF/25V,Y5V
2
3

R0402 C0402 PR329

1 30K
R0402
2

A
PR330 A
30K PQ81 TOPSTAR TECHNOLOGY
R0402 MMBT3904-F
ns SOT23 Joseph
Page Name +V3.3AL/+V5AL
PR331 0 Size Project Name Rev
R0402 A3 C49
A
Date: Friday, May 07, 2010 Sheet 46 of 59
PROPERTY NOTE: this document contains information confidential and property to
GND_TPS51125 TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5 4 3 2 1
 +V0.75S {14,15,54}
+V5AL {22,30,40,41,46,48,51,54}
+V3.3AL {6,22,23,24,25,27,28,30,32,34,35,36,37,41,42,43,44,45,46,48,49,50,51,54,56}
+VDC {22,37,44,46,48,49,50,53,54,55}
+V1.5 {8,11,14,15,54,55,56}
+V1.8S {11,16,27,29,30,54,55}
+V3.3S {6,8,14,15,16,22,23,24,25,26,27,28,29,30,32,33,34,35,36,37,38,40,41,42,43,48,49,50,51,53

+V5AL
+V3.3AL
+VDC 2A
PU3
tps51218 PR70
PR69 QFN10_0D5_0D8G 0
4.7K R0402 PC43 PC44 PC45 PC55

5
6
7
8
9
R0402 PC47 0.1uF/25V,X7R 1000pF/50V,X7R 4.7uF/25V,X7R 10uF/ 25V,X7R
TPS51218 0.1uF/25V,X7R C0603 C0402 C1206 C1210

D
1
{51} DDR_PWG 1 10 C0603
PJ3 PR80 PGOOD VBST PQ19
4
PR73 121K,1% SI4892DY V1_5

G
JOPEN
2K R0402 PR71 PR72 SO8_50_150_PPAK TestP

S
RESISTOR_1 2 TRIP DRVH 9
R0402 0 10K PL3 TPC60
ns

3
2
1
R0402 1.0uH/11A ns
3 8 LS2_6530 12A
{42} V1_5_ON EN SW 1 +V1.5

0.7V 12A

5
6
7
8
9
4 7 PR74 PC49 PC51
VFB V5IN

2
PC48 0 220UF/6.3V,OSCON 0.1uF/10V,X7R

D
R960 C0402 R0402 PR75 CAP6_6x7_3 C0402

1
100K,1% ns 5 6 4 2.2 PZ3

GND
0.022uF/16V,X7R RF DRVL R0805 BZT52C2V0S-F/2.0V

G
+ +

1
PC52 PQ20 ns SOD323

1
4.7uF/10V,X5R AO4706 ns

11

3
2
1

2
PR77 C0805 SO8_50_150_PPAK PC50
PR76 470K 5.5m ohm@4.5V PC53 220UF/6.3V,OSCON OCP>14A
10K,1%
R0402
R0402
Set Fsw 290K PD10
1000pF/50V,X7R
C0402
CAP6_6x7_3 +/-3.3% DC
SSM34PT
SMA
ns 5% DC+ AC Switcher

PR78
11.5K,1% R0402

PC54 PR79
0.022uF/16V,X7R 20K
C0402 ns R0402 ns

PU5
APL5331
SOP8_1D27_4G

PD23 1N4148WS
加强此器件散热。
1A-2A 1 8 SOD323
+V1.5 VIN NC3 V1R8S1
1 ns
PR88 2 7 +V3.3AL TestP
2K,1% GND NC2 TPC60
PC62 R0402 3 6 ns
4.7uF/10V,X5R REFEN VCNTL
1A Max

ADJ/GND
PGND

C0805 4 5 +V3.3S 3 2 +V1.8S

PC61 VOUT NC1 PC65 VIN VOUT
Vo 4
0.1UF/10V,X7R 4.7uF/10V,X5R
C0402 PR90 C0805 1A
9

2K,1% PU12 PR276

1
R0402 APE1117C 220
SOT223 R0402
PC66 PC206 PC207 PC208 PC215
0.1UF/10V,X7R 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R
C0402 C0805 C0805 C0805 C0805 PR277
TPC60 1K
+V3.3AL TestP PR278 R0402
V0_75S1 100,1% ns
ns R0402
PR91
3

4.7K
R0402 PQ21
2N7002 +V0.75S
PR92 1 SOT23
10K
R0402 1A-2A
2
3

PC67 PC68
1 PQ22 10uF/6.3V,X5R 10uF/6.3V,X5R 2A Max
{42} V0_75S_ON
MMBT3904-F C0805 C0805 +/-15mV DC
+/-65mV DC+AC Linear
2

PR93
30K PC69
R0402 0.022uF/16V,X7R TOPSTAR TECHNOLOGY
ns C0402
ns Joseph
Page Name +V1.8/+V0.9S DDR
Size Project Name Rev
A3 C49
A
Date: Friday, May 07, 2010 Sheet 47 of 59
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
 +VDC {22,37,44,46,47,49,50,53,54,55}
+V3.3S {6,8,14,15,16,22,23,24,25,26,27,28,29,30,32,33,34,35,36,37,38,40,41,42,43,47,49,50,51,53,54,55,56}
+V5S {22,24,26,30,33,34,36,38,40,41,42,49,50,53,54}
+V1.05S {23,24,25,28,29,30,34,54,55,56}
+V1.5S {35,37,54}
+V3.3AL {6,22,23,24,25,27,28,30,32,34,35,36,37,41,42,43,44,45,46,47,49,50,51,54,56}
+V5AL +V5AL {22,30,40,41,46,47,51,54}
+V3.3S +V1.1S_VTT {8,10,11,49,53}

+VDC 2A
PU6
tps51218 PR95
PR94 QFN10_0D5_0D8G 0
4.7K R0402 PC72 PC73 PC70 PC74

5
6
7
8
9
R0402 PC71 0.1uF/25V,X7R 1000pF/50V,X7R 10uF/ 25V,X7R 10uF/ 25V,X7R
{42,51} VTT_PWG
TPS51218 0.1uF/25V,X7R C0603 C0402 C1210 C1210

D
1
1 10 C0603
PJ4 PR189 PGOOD VBST PQ23
4
PR98 100K AOL1418 V1_1S1

G
JOPEN
2K R0402 PR96 PR97 SO8_50_150_PPAK TestP

S
RESISTOR_1 2 TRIP DRVH 9
R0402 0 10K PC77 TPC60
ns
2

3
2
1
R0603 PL6 220UF/6.3V,OSCON ns
3 8 CAP6_6x7_3 20A
{42} V1_1S_VTT_ON EN SW 1 +V1.1S_VTT
1.0uH/18A
Co-lay. LS2_1040

5
6
7
8
9

5
6
7
8
9
PR99 PC79
4 VFB V5IN 7
0 C0402 26-28A

2
R961 PC75 R0603 PR100 0.1uF/10V,X7R

1
100K,1% 2.2
0.022uF/16V,X7R 5 6 4 4 ICCmax=31A

GND
RF DRVL R0805 PZ4

G
+ + +

1
C0402

1
PC80 PQ24 PQ65 ns BZT52C2V0S-F/2.0V +/-2% DC,

S
ns 4.7uF/10V,X5R AO4706 AO4706 PC81 SOD323
3% AC+ripple Switcher

11

3
2
1

3
2
1

1
PR102 C0805 SO8_50_150_PPAK SO8_50_150_PPAK 1000pF/50V,X7R ns
470K S_Bot S_Bot C0402
R0402 PD33 PD11 ns
Set Fsw 290K SSM34PT SBM54PT
SMA SMB
PC82 PR104 20K PR266 ns
0.022uF/16V,X7R R0402 ns 0 PC76 PC78
C0402 ns R0603 220UF/6.3V,OSCON 220UF/6.3V,OSCON
CAP6_6x7_3 CAP6_6x7_3
0.7V
PR103 4.99K,1%
R0402

PR333 PQ37
VTT_SELECT Vo
Arrandale: High 1.05V
3
71.5K,1%
ns 2N7002
R0402 SOT23 PR290
PR101 R0402 47K Clarksfield: Low 1.1V
10K,1% 1 +V3.3S
R0402 ns
ns
2

PR291

3
R0402 10K
VTT_SELECT {10}

2
PQ60 1
MMBT3904-F ns 高电平为1.05V/1.1V. V1.1S1 R980 R979 R981
ns 2 Open3mm_3 0 0 0
PR292 Open3*3mm
100K ns

1
Add by Rewave for ns V1.05 10/3/11
R0402
ns

+V5AL
+V3.3AL
+VDC
Co-lay.
PU7
tps51218 PR106 2A
PR105 QFN10_0D5_0D8G 0
4.7K R0402 PC84 PC85 PC83 PC120
5
6
7
8

R0402 PC86 PQ25 0.1uF/25V,X7R 1000pF/50V,X7R 4.7uF/25V,X7R 10uF/ 25V,X7R

{51} V1.05S_PWG ns TPS51218 0.1uF/25V,X7R AO4468 C0603 C0402 C1206 C1210
8A
D
1

1 10 C0603 SO8_50_150 ns
PGOOD VBST
PR109
PJ5 PR260
210K,1% ns
4
ns ns ns
V1_05S
TestP
+/-5% Switcher
G

JOPEN
2K R0402 ns PR107 PR108 PL7 TPC60
S

RESISTOR_1 2 TRIP DRVH 9

R0402 2.2 10K 1.0uH/11A ns
ns
2

3
2
1

ns ns R0603 LS2_6530
3 8
8A
{42} V1_1S_VTT_ON EN SW ns 1 +V1.05S
ns
0.7V Co-lay. PC89
5
6
7
8

4 7 PR111 ns C0402
VFB V5IN

2
0 0.1uF/10V,X7R
D

PR110 ns

1
PC87 R962 R0603 PD12
0.022uF/16V,X7R100K,1% 5 6 4 SSM34PT 2.2 + PZ5
GND

1
RF DRVL R0805 BZT52C2V0S-F/2.0V
G

C0402 SMA
PC90 PQ26 PD32 ns SOD323
S

ns

1
4.7uF/10V,X5R AO4468 1N5819 ns PC88 ns
11

3
2
1

PR113 C0805 SO8_50_150 SOD123 220UF/6.3V,OSCON

ns PR112 200K ns 22/30m ohm@4.5V PC91 CAP6_6x7_3
10K,1% R0402 1000pF/50V,X7R
R0402 Set Fsw 340K ns ns ns C0402
ns ns
ns
TOPSTAR TECHNOLOGY
ns
ns Joseph
PR114 Page Name +V1.5S/+V1.05S CHIPSET
4.99K,1% R0402
Size Project Name Rev
A3 C49
A
Date: Friday, May 07, 2010 Sheet 48 of 59
PC92 ns PR115 PROPERTY NOTE: this document contains information confidential and property to
0.022uF/16V,X7R 20K TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
C0402 ns R0402 ns to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
 PR117 PR118 +V1.1S_VTT
2.2K 2.2K +V1.1S_VTT {8,10,11,48,53}
R0402 R0402 +V5S {22,24,26,30,33,34,36,38,40,41,42,50,53,54}
ns
+V3.3S {6,8,14,15,16,22,23,24,25,26,27,28,29,30,32,33,34,35,36,37,38,40,41,42,43,47,48,50,51,53,54,5
+VGFX {11}
+VDC {22,37,44,46,47,48,50,53,54,55}
预留固定VID方案，用于Debug， +V3.3AL {6,22,23,24,25,27,28,30,32,34,35,36,37,41,42,43,44,45,46,47,48,50,51,54,56}
PR116
后阶段无问题后，取消此处电阻。 2.2K PR119
R0402 2.2K
ns R0402
{11} GFXVR_VID_0 ns

{11} GFXVR_VID_1

{11} GFXVR_VID_2

{11} GFXVR_VID_3

+V3.3S {11} GFXVR_VID_4

{11} GFXVR_VID_5
PR127 PR128
PR126 0 0
4.7K R0402 PC95 PC94
+V3.3AL R0402
{11} GFXVR_VID_6 R0402
ns 0.1uF/25V,X7R 1000pF/50V,X7R
ns C0603 C0402
VGFX_ON
PC93
+VDC 14A
PR130 0.022uF/16V,X7R
2A LL=7 mOhm
3

PJ6 JOPEN 47K C0402 PR131 0 R0402

{11} GFXVR_DPRSLPVR +VGFX
RESISTOR_1 R0402 ns
ns +V3.3S PC96 PC97

5
6
7
8
9
1 2 1 10uF/ 25V,X7R 10uF/ 25V,X7R
PR134 PQ27 PR132 10K R0402 C1210 C1210

D
28

27

26

25

24

23

22
10K 2N7002 ns
2
3

R0402 SOT23 4 PQ28

VID6

VID5

VID4

VID3

VID2
DPRSLPVR

VR_ON
PQ29 PR133 AOL1448 VGFX2

G
{11} GFXVR_EN 1
MMBT3904-F PR136 PR135 PR138 SO8_50_150_PPAK PL8 Co-lay. TestP

S
2K
高电平为1.05V/1.1V. SOT23 2K 0 10K S_Bot 1.0uH/18A TPC60
R0402
2

3
2
1
ns R0402 LS2_1040 ns
PR137
R0402 1 CLK_EN# VID1 21
1 VGFX 14A
30K
R0402 2 20
{51} GFXVR_PWRGD PGOOD VID0

5
6
7
8
9
ns PR141 PR139 1
PC103

2
PR140 47K R0402
PU8 0 2.2 C0402

D
+V5S
PC98 3 RBIAS 19 R0402 R0805 PL4 0.1uF/10V,X7R
VCCP

1
0.022uF/16V,X7R
C0402 PC99 1000pF/50V,X7R
ISL62881 PC100
4 ns 1.0uH/11A
LS2_6530

G
+ +

1
ns C0402 QFNS28_0D4_1G 1uF/10V,X7R PQ30

S
4 VW LGATE 18 ns

1
PR142 R0402 C0603 AO4706 Co-lay.

3
2
1

2
10K,1% 250KHz SO8_50_150_PPAK
5 COMP VSSP 17
PC105 PD13 PD28
3300pF/50V,X7R SSM54PT SSM34PT
C0402 6 16 SMA SMA
PC106 PR145 FB PHASE ns
PC107
PR143 100pF/50V,NPO 2.37K,1% PC104 PC101 PC102 PZ6
470K C0402 R0402 7 15 PC108 1000pF/50V,X7R 220UF/6.3V,OSCON 220UF/6.3V,OSCON BZT52C2V0S-F/2.0V
VSEN UGATE 0.22uF/16V,X7R C0402 CAP6_6x7_3 CAP6_6x7_3 SOD323
R0402
PR144 G2 C0603 ns ns
270pF/25V,X7R GND2
ISUM+
VGFXVSSSEN {11}

BOOT
ISUM-

ns

IMON
75K G1
VDD
GND1
RTN

C0402

VIN
R0402
PC109
GND_ISL62881 PR146 GND_ISL62881 PR148 0.22uF/10V,X7R
8

10

11

12

13

14
6.98K,1% 0 C0603 VGFX_IMON1
R0402 R0402
PR147 TestP
VGFX PR149 10 22.1K,1% TPC60
R0402 R0402 ns
PR150 100 VGFX_IMON {11}
{11} VGFXVCCSEN PR151 0 R0402
R0402
PR152 0
+VDC
PC110 R0402
{11} VGFXVSSSEN 270pF/25V,X7R PR153 1
+V5S
C0402 R0402 PC112
GND_ISL62881 0.1uF/25V,X7R
GND_ISL62881 C0603
PR154 10 PC111
R0402 0.22uF/10V,X7R
GND_ISL62881
C0603 PR155
R0402
PC113 PC114 PC209 3.57K,1%
1000pF/50V,X7R PR156 0.047uF/50V,X7R 0.01uF/25V,X7R PR157
C0402 82.5,1% C0603 C0402 2.49K,1%
PR158 0 R0402 R0402
R0402 PR159
10K,1%
PC116 R0402
0.01uF/25V,X7R PC115 PR160
GND_ISL62881 C0402 0.1uF/25V,X7R 10K,1%
C0603 R0603
PR161
4.02K,1%
R0402 TOPSTAR TECHNOLOGY
NTC thermistor
PR312 PC117 25度下，10K
PC260 0.1uF/10V,X7R 60度下，3.05K Page Name
100 470pF/25V,X7R 80度下，1.71K。 +V1.5AL
C0402
R0402 C0402 放于电感背面。 Size Project Name Rev
ns ns A3 C49
A
GND_ISL62881
Date: Friday, May 07, 2010 Sheet 49 of 59
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
 5 4 3 2 1

+VGA_CORE {17}
+VDC {22,37,44,46,47,48,49,53,54,55}
+V3.3S {6,8,14,15,16,22,23,24,25,26,27,28,29,30,32,33,34,35,36,37,38,40,41,42,43,47,48,49,51,53,54,55,56}
+V3.3AL {6,22,23,24,25,27,28,30,32,34,35,36,37,41,42,43,44,45,46,47,48,49,51,54,56}
+V5S {22,24,26,30,33,34,36,38,40,41,42,49,53,54}

PC118
0.1uF/10V,X7R +V5S
C0402
+VDC
D D

1uF/10V,X7R 2A
C0603 PC272
PU9 PC119 PC121 PC122 PC124
ISL62872 0.1uF/25V,X7R 10uF/ 25V 10uF/ 25V 1000pF/50V,X7R
QFNR20_0D4_0D5 PM C0603 C1210 C1210 C0402
PR332
500mA LGATE PM 2.2
1 LGATE PVCC 20
R0402 PM PM PM PM
PC273
2 PGND VCC 19 PM

5
6
7
8
9
PC125 PL5
PR162 0.1uF/10V,X7R PQ31 1.0uH/11A

D
1uF/10V,X7R NVVDD_SENSE {17}
30K C0402 GND_62872 3 GND BOOT 18 PC126 AOL1448 LS2_6530 Co-lay. PR163
PR164 R0402 ns 0.1uF/25V,X7R C0603 4 SO8_50_150_PPAK 1 10
2K C0603 ns

G
{42} VGPU_ON PM 500mA PR165 2.2 PR166 PL9 R0402

S
4 EN UGATE 17 PM PM R0402 2.2 1.0uH/18A PM

3
2
1
R0402 PM PM Co-lay. R0805 LS2_1040
10A
VID1 5 16 500mA PM PM VGA_CORE
VID1 PHASE 1 +VGA_CORE
+V3.3AL 2 1 PM
10A

5
6
7
8
9
J4 VID0 6 15 PR168 PR167
JOPEN VID0 NC 2.2 9.31K,1%

D
VGA_CORE1

2
RESISTOR_1 R0402 PD27 R0402
ns 7 14 LGATE 4 SSM34PT + + + TestP

1
SREF OCSET 500mA PZ7 TPC60

1
SMA
PQ32 BZT52C2V0S-F/2.0V

S
ns

2
C 8 13 AOL1718 SOD323 C
SET0 VO

3
2
1

1
PM
SO8_50_150_PPAK
PM
PM
Co-Layout ns

9 12 PD14 PC130
PR169 PR170 PR171 SET1 FB PM SSM54PT PC128 0.047uF/50V,X7R
4.99K,1% 10K,1% 45.3K,1% SMA 0.01uF/25V,X7R C0603 PC129
R0402 R0402 R0402 10 11 ns C0402 PM PM GC178
220UF/6.3V,OSCON GC175
PM SET2 PGOOD CAP6_6x7_3220uF/2.5V,POSCAP
220uF/2.5V,POSCAP
9.31K,1% CT7343_19 CT7343_19
PC131 PR172 PM PR173 R0402
0.1uF/10V,X7R PM PM 220K PM
C0402 R0402 ns PM
PC132
PM PR174 100,1% PM
PM
GND_62872 GND_62872 PM
PR175 10K 3300pF/50V,X7R
+V3.3S
R0402 PR176 2.49K,1%
PM
PM
PM

PR177
PR183 0 R0402 4.02K,1%

{42} VGACORE_PWRGD

PM PM
B GND_62872 B
GND_62872
+V3.3S +V3.3S
+VGA_CORE +V3.3S

PD15 PR180
PR178 PR179 1 10
10K 10K 1N5819 R0402
R0402 R0402 SOD123 ns
ns ns

VID0 VID1
PM
3

PR181 PQ33 PR182 PQ34

1K 2N7002 1K 2N7002
1 SOT23 1 SOT23 PR250
{21} GPU_VID0 {21} GPU_VID1
10K
R0402 R0402 R0402
2

PM PM
PR184 PC133 PR185 PC134
PM 10K 0.1uF/10V,X7R
PM 10K 0.1uF/10V,X7R
PM
R0402 C0402 R0402 C0402
ns ns

A
PM PM A
TOPSTAR TECHNOLOGY
Joseph
Page Name +VGA_CORE
Size Project Name Rev
A3 C49
A
Date: Friday, May 07, 2010 Sheet 50 of 59
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5 4 3 2 1
 +V3.3S {6,8,14,15,16,22,23,24,25,26,27,28,29,30,32,33,34,35,36,37,38,40,41,42,43,47,48,49,50,53,54,55,56}
+V5AL {22,30,40,41,46,47,48,54}
+V3.3AL {6,22,23,24,25,27,28,30,32,34,35,36,37,41,42,43,44,45,46,47,48,49,50,54,56}
+V1.05S {23,24,25,28,29,30,34,48,54,55,56}
+V1.5S {35,37,54}
{44} SHDN# +VCC_CORE {10,53}
AD+ {41,44,46}

PR345
10K
PR353 R0402
100 ns PQ35
R0402

2
PR186 0 MMBT2907
R0402 1 SOT23
{34} SHDN_LOCK#
PZ9
BZT52C5V6S-F/5.6

3
SOD323 PQ36 PQ112
+V5AL 2 1 MMBT3904-F MMBT3904-F
SOT23 SOT23

3
+V3.3AL 2 1 1 1

PZ8
2

2
BZT52C3V6S-F/3.6 PR187
SOD323 100 PR351 PC222
PC135 R0402 20K 1000pF/50V,X7R
1uF/10V,X7R R0402 C0402
C0603

+V3.3S

PR188
10K
Power Good Logic CIRCUIT R0402

1 PD16
{42,48} VTT_PWG
3 MAIN_PWROK {25,42}
R965 0 2
{48} V1.05S_PWG
ns
BAT54A
R963 0 1 PD17
{49} GFXVR_PWRGD
GM
3

{47} DDR_PWG 2
TOPSTAR TECHNOLOGY
BAT54A
Joseph
{25,42} PM_RSMRST# 1
Page Name Power Good Logic/OVP
3 Size
R484 1K Project Name Rev
A4 C49
{25,42} PM_SLP_S3# 2 A
R0402 PD18
BAT54A Date: Friday, May 07, 2010 Sheet 51 of 59
C378 PROPERTY NOTE: this document contains information confidential and property to
0.1UF/10V,X7R TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
C0402 to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
 BATT+ {44,45}

+V3.3AL {6,22,23,24,25,27,28,30,32,34,35,36,37,41,42,43,44,45,46,47,48,49,50,51,54,56}

PC149 PR202 0
1.5A
1uF/10V,X7R VDDP 15 2 Isense_SYSN {44}
VDDP ACSET CHG_GND
C0603
PR190 R0402
4.7 5V_internal_LDO PC200 Co-lay.
R0402 1 PC136 PC151 PC152 PC147
PC140 VDD 0.1uF/25V,X7R PD24 SOD323 1000pF/50V,X7R 0.1uF/25V,X7R 4.7uF/25V 10uF/ 25V
CHG_GND
1uF/10V,X7R 24 C0603 1N4148WS C0402 C0603 C1206 C1210
C0603 DCIN 1
ns ns
{41,44} Isense_SYSP 19 CSIP
PC141 PR204 0
PR193 0.1uF/25V,X7R R0402
C0603 20 17 PR195 2.2
{44} Isense_SYSN CSIN UGATE R0402
10 R0402
PD25

1
PC138 PC139 PU10 PQ58
1000pF/25V,X7R 5600pF/50V,Y5V 5 16 VDDP D1 D1 AO4932
C0603 ICOMP ISL6251HAZ BOOT 1
PR197 SO8_50_150
C0402 8
PC142 1N4148WS 10K G1 PR200
SSOP24_25_150 SOD323 R0402 S1 50mOHM,1% PC145
PC155 PC150 0.01uF/25V,X7R 6 0.1uF/25V,X7R PL10 R2512 2A 0.1uF/25V,X7R
C0402 VCOMP C0603 phase C0603
5 7 1 BATT+
R0402 10K 18 phase 15uH/3.6A
PHASE
6 PR192 LS2_1040 PC156
12.63V
CHG_GND 3.3V 11 VADJ
2.2
10uF/ 25V 2A Max
D2 R0805
14 PR203 3 ns C1210
LGATE 0
{42} CHG_ON 3 EN R0402 G2 S2 PC153
13 0.01uF/25V,X7R PC144 PC146
PGND

4
C0402 1uF/25V,Y5V
PR244 10K 9 ns 10uF/ 25V C0805
{42} SET_I CHLIM
21 PR194 C1210
CSOP
PR198 PC178 PC148 2.2 R0402
SET_I 充电电流 15.4K,1% 2.39V_Vref 8
R0402 1uF/10V,X7R VREF 1uF/10V,X7R
CSON 22
ns C0603 C0603
0V 0A PR199 10
10.5K,1% ACLIM PR334 0 R0402
0.4V 0.4A R0402 4 CHG_GND
CELLS
23 ACPRN
0.643Vref PR196
1.2V 1.2A 设置适配器限流值为
ICM 7 SYS_I_Sense {42}
82mV/25m ohm=3.28A.
2V 2A PR201 100 R0402
20K,1% PC154
12
R0402 GND 3300pF/50V,X7R Layout note:
C0402
Far away from critical signal trace
SYS_I_Sense SYS_CURRENT PR191 0

500mV 1A CHG_GND R0402

1.5V 3A CHG_GND
1.67V 3.33A CHG_GND

SYS_CURRENT SYS_I_Sense SYS_I_Trip Cells status Battery Pak

>3.6A >1.8V High Float 2S
<3A <1.5V Low GND 3S
VDD 4S

TOPSTAR TECHNOLOGY
Joseph
Page Name CHARGER
Size Project Name Rev
A3 C49
A
Date: Friday, May 07, 2010 Sheet 52 of 59
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
 5 4 3 2 1

PR341 1K R0402
{10} H_VID0 +V3.3S {6,8,14,15,16,22,23,24,25,26,27,28,29,30,32,33,34,35,36,37,38,40,41,42,43,47,48,49,50,51,54,55,56}
+V5S {22,24,26,30,33,34,36,38,40,41,42,49,50,54}
PR342 1K R0402
{10} H_VID1 +VDC {22,37,44,46,47,48,49,50,54,55}
+VCC_CORE {10}
PR343 1K R0402
{10} H_VID2
PR247 1K R0402 ns
{10} H_VID3 +V1.1S_VTT {8,10,11,48,49}
PR248 1K R0402 ns
{10} H_VID4
PR245 1K R0402 +VDC
{10} H_VID5 +V1.1S_VTT
PR249 PR344 3A
{10} H_VID6
D 1K 1K PC161 D
R0402 R0402 0.01uF/25V,X7R
PR240 2K R0402 PR280 PR279 C0402
{42} IMVP_ON PQ38 PC157 PC158 PC162
1K 1K
PR282 2K R0402 R0402 R0402 AOL1448 10uF/ 25V 10uF/ 25V PC176 0.01uF/25V,X7R
PR205 470 R0402 SO8_50_150_PPAK C1210 C1210 0.1uF/25V,X7R C0402
{10} PM_DPRSLPVR ns C0603
+V1.1S_VTT PR242 10K

5
6
7
8
9
R0402 ns PR206
0

D
{6} CK505_CLK_EN# CPU_GND VCORE1
PR241 R0603
2K R0402 UG2 4 TestP

40

39

38

37

36

35

34

33

32

31
TPC60

G
PR207 PC163 PR208 PQ55 PD20 PC179 ns

S
+V3.3S G9

CLK_EN#

VID6

VID5

VID4

VID3

VID2

VID1

VID0
DPRSLPVR

VR_ON
2K R0402 G9 0.22uF/16V,X7R 10K AOL1718 SBM54PT PC164 220UF/2.5V,POSCAP
G8 G8

3
2
1
C0603 R0402 SO8_50_150_PPAK SMB PL11 220UF/2.5V,POSCAP CT7343_19
1
G7 G7
30 Phase2 25A CT7343_19 +VCC_CORE
{42} IMVP_PWRGD PGOOD BOOT2 1
PR243 10K R0402
+V1.1S_VTT 0.36uH/30A 50A

5
6
7
8
9

5
6
7
8
9
ns PR213 PR210 LS2_1040

1
PR217 10K 0 2.2

D
{10} PM_PSI# 2 PSI# UGATE2 29
R0402 R0603 R0805 PR215 + + + +

1
4 4 ns 10K
PR214 R0402 PR287 PC168

G
3 28

1
CPU_GND RBIAS PHASE2

2
147K,1% PQ42 PC166 1uF/10V,X7R

S
10
R0402 AOL1718 0.01uF/25V,X7R R0402 C0603

3
2
1

3
2
1
PC171 C0402 4 27 SO8_50_150_PPAK C0402

ISEN2
1000pF/50V,X7R {8} VR_PROCHOT# VR_TT# VSSP2 ns
PR218 PC169
CPU_GND
4.02K,1% PR219 NTC 5 NTC LGATE2 26 LG2 PC172 220UF/2.5V,POSCAP PC180
C R0402 470K,1% R0603 PR220 0 R0603 1uF/10V,X7R CT7343_19 220UF/2.5V,POSCAP C

PR222 R0402
PU11 C0603 CT7343_19
NTC thermistor放到
板面最热的地方 6.98K,1%
6 VW ISL62882HRTZ VCCP 25 +V5S
PC174 QFNS40_0D4_1G
C0402 7 24 LG1b PC167
1000pF/50V,X7R COMP LGATE1b
1uF/10V,X7R
PR228 0 R0603

ISEN1
C0603
8 23 PD21
PC181 PC184 C0402 FB LGATE1a SBM54PT
3300pF/50V,X7R 100pF/50V,NPO PR221 0 R0603 SMB
C0402 9 22
PC182 FB2 VSSP1 PC175
100pF/50V,NPO SO8_50_150_PPAK 0.01uF/25V,X7R
AOL1718

3
2
1

3
2
1
C0402 PR229 ISEN2 10 21 C0402 ns PR225 PR288
ISEN2 PHASE1 PQ57

UGATE1
75K 10K 10

S
BOOT1
ISUM+
ISEN1

ISUM-

LG1a R0402
VSEN

1
IMON
4 4 R0402

G
R0402
VDD
RTN

PC170
VIN

PR223
G1
G2
G3

G4
G5
G6
0.22uF/16V,X7R 2.2
PR209 C0603

D
CPU_GND R0805
G1
G2
G3
11

12

13

14

15

16

17

18

19

20
G4
G5
G6
3.57K,1% ns PL13

5
6
7
8
9

5
6
7
8
9
R0402 Phase1 1
PR235
PC173 0.22uF/16V,X7R PR230 PR227 SO8_50_150_PPAK 0.36uH/30A
10 25A

3
2
1
PR289 R0402 C0603 PR238 CPU_GND 0 10K AOL1718 LS2_1040
10 100 PC165 R0603 R0402 PQ56

S
0.22uF/16V,X7R UG1 4 PC186 PC183
ISEN1

G
R0402 R0402
PC177 C0603 0.1uF/25V,X7R 0.01uF/25V,X7R
1000pF/50V,X7R PR211 10 R0402 PQ41 C0603 C0402 PR212 PR224
B +V5S B
PR234 C0402 AOL1448 3.57K,1% 3.57K,1%

D
{10} VCCSENSE
10 PC159 1uF/10V,X7R C0603 SO8_50_150_PPAK R0402 R0402

5
6
7
8
9
R0402 PC191
PC193 PC194 1000pF/50V,X7R
1uF/10V,X7R 0.1UF/10V,X7R C0402 PC160 0.1uF/25V,X7RC0603
ISUM-

C0603 C0402 CPU_GND PC187 PC190 PC185

ns 10uF/ 25V 10uF/ 25V 0.01uF/25V,X7R
PR237 PR231 C1210 C1210 C0402
+VDC
CPU_GND 11.5K,1% 10
PR236 R0402 R0402 Vcore_IMON {10}
{10} VSSSENSE
0
R0402 Vcore_IMON1 3A +VDC
PC196 TestP TPC60
1000pF/50V,X7R PC188 ns
C0402 0.22uF/10V,X7R ISUM+
C0603
CPU_GND PC210
0.01uF/25V,X7R PR216
PR232 PC197 C0402 2.49K,1%
82.5,1% 0.1uF/25V,X7R
R0402
R0402 C0603 PR233
PR246 10K,1%
PC195 R0402
0.01uF/25V,X7R PC189 PR226
0 C0402 0.1uF/25V,X7R 10K,1%
R0603 C0603 R0603
PR239 ISUM-
CPU_GND 1.58K,1%
A
R0402 A
NTC thermistor TOPSTAR TECHNOLOGY
PR313 PC192 25度下，10K
PC261 0.1uF/10V,X7R 60度下，3.05K Joseph
100 470pF/25V,X7R C0402 80度下，1.71K。 Page Name +VCC_CORE
R0402 C0402 放于电感背面。
ns ns Size Project Name Rev
GND_ISL62881 A3 C49
A
Date: Friday, May 07, 2010 Sheet 53 of 59
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5 4 3 2 1
 5 4 3 2 1

+VDC {22,37,44,46,47,48,49,50,53,55}
+V5S {22,24,26,30,33,34,36,38,40,41,42,49,50,53}
+V3.3S {6,8,14,15,16,22,23,24,25,26,27,28,29,30,32,33,34,35,36,37,38,40,41,42,43,47,48,4
+V5AL {22,30,40,41,46,47,48,51}
+V3.3AL {6,22,23,24,25,27,28,30,32,34,35,36,37,41,42,43,44,45,46,47,48,49,50,51,56}
+V1.05S {23,24,25,28,29,30,34,48,55,56}
+V1.5 {8,11,14,15,47,55,56}
+V1.8S {11,16,27,29,30,47,55}
+V0.75S {14,15,47}
AD+ {41,44,46}
BATT+ {44,45,52}
+V1.5S {35,37}
D D
+V3.3AL

PD22
1N4148WS PQ45
+VDC SOD323 AO4468

5
6
7
8
1 SO8_50_150
V3_3S1

D
TestP
2 3 4 TPC60
ns

G
PQ43 PR255 PR256

S
DTB114EK 20K 51K

3
2
1
PR251 SOT23 +V5AL R0402 R0402 +V3.3S

1
100K PC201
R0402 0.01uF/25V,X7R PR254 PR252 PC204
C0402 10K 33K 0.01uF/25V,X7R
R0402 R0402 C0402 PC205
PQ44 1uF/10V,X7R

5
6
7
8
AO4468 C0603
PR253 SO8_50_150

D
1K
R0402 4
V5S1

G
MAIN_OFF TestP

S
TPC60

3
2
1
3 ns +V5S +V1.5
PQ46
C 2N7002 C
1 PC542
{42} MAIN_ON 10uF/10V,Y5V
PC202 PC203
PR257 SOT23 0.01uF/25V,X7R 1uF/10V,X7R PD26 PQ59 ns
2

1K PR258 C0402 C0603 1N4148WS AO4468

R0402 510K SOD323 SO8_50_150 PQ61

5
6
7
8
R0402 1 AO4468

5
6
7
8
SO8_50_150

D
ns

D
dri1.5 4
dri1.5 4

G
PR281 PR283

G
S
10K 100K

S
3
2
1
R0402 R0402

3
2
1
PR284 +V1.5S
100K PC211
R0402 0.01uF/25V,X7R
C0402 PC212
1uF/10V,X7R
C0603

+V1.05S +V0.75S +V1.8S

+V5S +V3.3S +V1.5 +VDC
+V1.5S

100mA 70mA 36mA

2

B PR270 B
2

2
PR259 PR265 100

2
100 PR261 PR262 PR264 100 PR267 PR268 R0402
R0402 100 100 PR263 100 R0402 100 100 PR271
R0402 R0402 100 R0402 ns R0402 R0402 100
1

ns ns R0402 R0402 PR272

1

1
V1_8DISCHG ns 510K

1
R0402

PQ54
3

3
PQ48 PQ50 PQ53 2N7002
3

3
2N7002 PQ49 2N7002 PQ51 PQ52 PQ80 2N7002 SOT23
SOT23 2N7002 SOT23 2N7002 2N7002 2N7002 SOT23
SOT23 1 SOT23 SOT23 SOT23 PR273 10K 1 1 V1_8DISCHG
ns {25,42} PM_SLP_S4#
1 ns1 1 1 1 R0402
2

2
PR275
2

200K
R0402

MAIN_OFF

A A
TOPSTAR TECHNOLOGY
Joseph
Page Name SYSTEM/DISCHARGE
Size Project Name Rev
A3 C49
A
Date: Friday, May 07, 2010 Sheet 54 of 59
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5 4 3 2 1
 5 4 3 2 1

+VDC +V3.3S
+V3.3S {6,8,14,15,16,22,23,24,25,26,27,28,29,30,32,33,34,35,36,37,38,40,4
+V1.05S {23,24,25,28,29,30,34,48,54,56}
+V1.5 {8,11,14,15,47,54,56}
+V1.8S {11,16,27,29,30,47,54}
PR307 PR354 PQ86 Rewave change on 2009/11/11 +V3.3GPU
+V1.05GPU
{17,20,21,36,38}
{17,18,19,20}
51K 10 AO4468
+V1.8GPU {20}

5
6
7
8
R0402 R0402 SO8_50_150 V3_3GPU
+V1.5GPU {18,19}
PM PM TestP

D
PM
S_Top S_Top +VDC {22,37,44,46,47,48,49,50,53,54}
TPC60
+V5S {22,24,26,30,33,34,36,38,40,41,42,49,50,53,54}
+VDC 4 ns
D D

G
+V3.3GPU
PR297

2
<0.5A 0

3
2
1
PR304 PR306 R0402 PM
51K PR308 PR305 220 +V1.8S

3
R0402 PR339 510K 220 R0402 +VDC
PR350
PM 10 R0402 PC219 R0402

1
R0402 PM 1uF/10V,X7R +V3.3S 2 3 +V1.8GPU
1 C0603
51K PM PQ83 PM PM PR335 PR300
<0.5A
3
R0402 2N7002 PC216 51K 0 PM

2
SOT23 0.01uF/25V,X7R PM R0402 R0402 PQ68
PC346

1
PM C0402 PM PR338 ns AO3415
S_Top PR349
1 PM PM 10 1000pF/50V,X7R SOT23 PC220
{42} V3G_1.05G_ON

2
S_Top R0402 PM 1uF/10V,X7R
PR303 PQ66 C0603 PR311

3
2

1K PR302 2N7002 51K PM 100

3
R0402 510K SOT23 R0402 R0402
R0402 PQ71 PM
PM V3GPU_OFF 2N7002

3 1
1
PM SOT23
{42} V1.8G_1.5G_ON 1 PM
PM PQ70

2
PM PR337 PQ77 2N7002

2
1K PR336 2N7002 1 SOT23
C PM C
R0402 510K SOT23
PM R0402

2
+V1.5
+V1.05S PM
PM
PM
PC544
PC543 PQ64 10uF/10V,Y5V
10uF/10V,Y5V PQ69 +VDC AO4468 ns
+VDC ns AO4468 SO8_50_150
SO8_50_150
ns
PR298
PR301 51K PQ67
51K PQ63 R0402 AO4468

5
6
7
8

5
6
7
8
R0402 AO4468 PM PR296 SO8_50_150

5
6
7
8

5
6
7
8
PM SO8_50_150 20K,1%

D
V1_05GPU R0402 V1_5GPU

D
TestP PM 4 4 TestP
TPC60 TPC60

G
4 4
ns ns
G

S
3

3
PR299 S

3
2
1

3
2
1
20K,1% 3 +V1.5GPU
2
1

3
2
1
B PR309 R0402 +V1.05GPU PR340 B
1
PQ75
200K PM 1 200K 3A
R0402 0.53A R0402 PM

2
2N7002 PQ78 PC213
PM
2

2
SOT23 PC217 PC214 PR294 峰值可为2.5A 2N7002 1uF/10V,X7R PR286
0.01uF/25V,X7R 1uF/10V,X7R 100 SOT23 C0603 100
PM C0402 C0603 R0402 PM R0402
PM

1
PM PM
PM PM PC218 PM

3
PQ73 PM 0.01uF/25V,X7R PQ72 PM
2N7002 C0402 2N7002
SOT23 SOT23
1 1
PM

2
PM PM

TOPSTAR TECHNOLOGY
A Joseph A
Page Name SYSTEM/DISCHARGE
Size Project Name Rev
B C49
A
Date: Friday, May 07, 2010 Sheet 55 of 59
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5 4 3 2 1
 5 4 3 2 1

D D

+V1.5 {8,11,14,15,47,54,55}
+V3.3S {6,8,14,15,16,22,23,24,25,26,27,28,29,30,32,33,34,35,36,37,38,40,41,42,43,47,48,49,50,51,53,54,55}
+V3.3AL {6,22,23,24,25,27,28,30,32,34,35,36,37,41,42,43,44,45,46,47,48,49,50,51,54}
+V1.05S {23,24,25,28,29,30,34,48,54,55}

C C

+V1.05S +V1.05S
+V1.5
+V3.3AL +V1.5
+V3.3S

C599
0.1uF/10V,X5R C596 C613
0.1uF/10V,X5R 0.1uF/10V,X5R
C588 C589 C590 C591 C594 C595 C598 C612 C597
0.1uF/10V,X5R 0.1uF/10V,X5R 0.1uF/10V,X5R 0.1uF/10V,X5R 0.1uF/10V,X5R 0.1uF/10V,X5R 0.1uF/10V,X5R 0.1uF/10V,X5R C592 C593 0.1uF/10V,X5R
0.1uF/10V,X5R 0.1uF/10V,X5R

+V3.3AL +V3.3S

B B

H5 H6

H19 H20
H26 H22 H15 H18 H23 H16 H21 H17 H24 H25

FAN FAN
HOLE HOLE
1

TH_315_118a HOLE HOLE HOLE HOLE HOLE TH_315_118a HOLE HOLE HOLE HOLE HOLE TH_230_126_6 TH_230_126_6
1

1
ns TH_315_118a TH_315_118a TH_315_394_118_P ns TH_315_118a TH_315_118_PTH_315_118a TH_315_118_P TH_315_118_P
TH_175_236D92 TH_315_118_P
ns ns ns ns ns ns ns ns ns ns PM PM

GND GND GND GND GND GND GND GND GND GND
GND GND

1
2
3
4
5
6
7

1
2
3
4
5
6
7
1
2
3
4
5
6
7

1
2
3
4
5
6
7
FD7 FD8 FD2 FD1 FD4 FD3 FD6 FD5

1 1
1 1 1 1 1 1 1 1 1 1
FMARKS FMARKS FMARKS FMARKS FMARKS FMARKS FMARKS FMARKS
ns ns ns ns ns ns ns ns

A A

TOPSTAR TECHNOLOGY
Joseph
Page Name SYSTEM/DISCHARGE
Size Project Name Rev
C C49
A
Date: Friday, May 07, 2010 Sheet 56 of 59
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR

5 4 3 2 1
 5 4 3 2 1

Lid IC
PWR_+V3.3AL
Power Button Switch PWR_+V3.3AL

PQ39
PC274 MMBT2907

2
PU13 0.1UF/10V,X7R IOPR2改为1M，IOPR4改为10K, SOT23
A180 C0402 解决电池电压低时无法开机问题 PWRLED# R964 4.7K R0402 1
SOT23_A 3 4 PWR_Isense_SYSP
VS+ 1 ns

3
PSW1 PWRSWVCC1 PR347 10K
2 PWR_LIDR# DTSM-63N R0402
Output BUTTON4A PR348 30K PWR_PWRSWVCC2 PWRLED1

3
3 PC275 1 2 R512 100 R0402 POWERLED+ 1 2
GND PD34 ns

2
1000pF/50V,X7R ns BL-HB335A-TRB

1
C0402 PD35 PESD1
PC276 PC277 BZT52C5V6S-F/5.6 ESDPAD_R0603 ns
1000pF/50V,X7R 1000pF/50V,X7R SOD323 EGA1-0603-V05

2
BAT54SPT POWERLED+ TESD9 1 2 EGA1-0603-V05

2
ns ESDPAD_R0603

POWERLED+ C226 1000pF/50V,X7R C0402

PWR_+V3.3AL Change Power Switch to seperate Componets ns

D D

PWRCONN&LANCONN PWR_+V3.3AL VDD3D3_LAN

DC Jack FB37
PWR_+V3.3S PWR_+V3.3AL 120ohm/100MHz,500mA
1 2FB0603
IO_AD+ LANCONN2
PJ7 1
DC JACK 5P 1
1 2 2 2
PWR5P_DC1 PFB4 3 R933 3.6K R0402
3 VDD3D3_LAN
PF2 100ohm@100MHz,3A 4
7A FB0805 4 VDD3D3_LAN
5
5 SHLD2 AD+ 1 1 2 4A 1 2
PWR_PCIE_TXP1_LAN
PWR_PCIE_TXN1_LAN 6
5
6
PWRCONN2 add 8111D
PFB5 7 21 IO_AD+ 1 1
FUSE1206 100ohm@100MHz,3A 7 21 R934 10K R0402 10K is used only when 93c56 is used
4 8 2 2
SHLD1 FB0805
PWR_PCIE_RXP1_LAN
9
8
3 3 10 10
Power domain chart
PWR_PCIE_RXN1_LAN 9
3 1 2 10 4 4 ns
AD-2

AD-1 PFB6 10
PWR_CLK_PCIE_GLAN 11 11 5 5 RTL8101E RTL8102E/RTL8111DVDD3D3_LAN
100ohm@100MHz,3A
FB0805
PWR_CLK_PCIE_GLAN# 12
13
12
22
6 6 9 9
7 7
AVDD33 DVDD15
EECS 1 8
8111D uses 93C66 and keep R934.
13 22 CS VCC
2

PC279
PC278
1uF/25V,Y5V
PWR_BUF_PLT_RST# 14
15
14 8 8 AVDD33 3.3V 3.3V EESK 2
EEDI/AUX 3 SK NC1 7
6
Others use 93C46 and remove R934.
PWR_PCIE_WAKE# 15 DI NC2
1uF/25V,Y5V C0805 PWR_Isense_SYSP 16 CNS8_V EEDO 4 5
PWRLED# 16 DO GND
C0805 17 Conn 8Pin AVDD18 1.8V 1.2V C547
PWR_LIDR# 17
18 U31 C0402
18 AT93C46-10SU-2.7 0.1UF/10V,X7R
PWR_PWRSWVCC2 19 19
20 EVDD18 1.8V 1.2V SO8_50_150
20 U32

53
46
37
16

59

58
33

52
49
43
41
38
32
21
15

48
47
45
44
2
GND_JACK通过开桥与大地连接
GND_JACK 20pin 0.5mm bot FFC DVDD15 1.5V 1.2V

VDD33_04
VDD33_03
VDD33_02
VDD33_01

AVDD33_02
AVDD33_01

VDD15_10
VDD15_09

VDD15_08
VDD15_07
VDD15_06
VDD15_05
VDD15_04
VDD15_03
VDD15_02
VDD15_01

EEDO
EESK
EEDI

EECS
去掉8101E的Option LIO_GND

PWR_CLK_PCIE_GLAN 26 REFCLK_P EVDD18_02 28 EVDD18

PWR_CLK_PCIE_GLAN# 27 REFCLK_N EVDD18_01 22

PWR_PCIE_TXP1_LAN 23 HSIP AVDD18_04 14 AVDD18

GND_JACK 24 11
PWR_PCIE_TXN1_LAN HSIN AVDD18_03
C549 C0402 29 8
PWR_PCIE_RXP1_LAN HSOP AVDD18_02
PWR_PCIE_RXN1_LAN
C550 C0402 0.1UF/10V,X7R 30
HSON AVDD18_01 5 FB12 0.01uf caps need to be
0.1UF/10V,X7R
20 63 DVDD15/VDD33 C551 placed close to PIN5
PWR_BUF_PLT_RST# PERSTB VCTRL15
1 CTRL18 C0402
VCTRL18 0.01uF/25V,X7R
PWR_PCIE_WAKE# 19 LANWAKEB
3 LAN_TX0+
PWR_+V3.3S R935 1K R0402 MDIP0 LAN_TX0-
36 ISOLATEB MDIN0 4
6 LAN_TX1+ LIO_GND
MDIP1
R936 54 LED3 MDIN1 7 LAN_TX1- VerC:Add 0.01uF followed demo
LIO_GND 15K R0402 55 9 LAN_TX2+
100M Lan(RTL8101E/8102E) 56
LED2 MDIP2
10 LAN_TX2- for better EMI performance
LED1 MDIN2
VDD3D3_LAN
R937 2.49K,1% R0402 57 LED0 MDIP3 12 LAN_TX3+
add
by Robin 080417
8102E\8111D 13 LAN_TX3-
R939 2K,1% R0402 RSET MDIN3
LIO_GND 64 RSET
8101E 61 LAN_XTALOUT
R978 CKTAL2
60 LAN_XTALIN
CKTAL1 Y7 25MHz
62 GVDD
C C
1 2

EGND1
EGND2

GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
XS2_3d3
0

NC9
NC8
NC7
NC6
NC5
NC4
NC3
NC2
NC1
Colay follow demo board 09.12.24 C559 C560 C561 C562
R0805 C0603 C0402 C0402 C0402
8111D 1uF/10V,Y5V 0.1UF/25V,Y5V 27pF/50V,NPO 27pF/50V,NPO

25
31

G1
G2
G3
G4
G5
G6
G7
G8
G9

51
50
42
40
39
35
34
18
17
8101E 8101E RTL8101E-GR

LIO_GND LIO_GND LIO_GND

VDD3D3_LAN C563 330PF/50V,X7R
LIO_GND TP1 TP2 C0603
Place close to pin 16,37,46,53 C564 4.7uF/10V,Y5V
RTL8111B/8101E circuit removes R68. LIO_GND
C565
C0805
330PF/50V,X7R

ICTP

ICTP
C543 C544 C545 C546
VerD:LAN Delete Caps and change U35
350uH/0.50uH 1:1
R68 is only used for RTL8111C(P)/8111D C573
C0603
330PF/50V,X7R
C0402 C0402 C0402 C0402 some options followed demo C611 C610 LAN_TX0- 2 1CT:1CT TX0- application. Keep R68 and remove ns ns C0603
TD1+ MX1+ 23
0.1UF/25V,Y5V 0.1UF/25V,Y5V board and colay 8102E 0.01uF/25V,Y5V 0.01uF/25V,Y5V
0.1UF/25V,Y5V 0.1UF/25V,Y5V
By K' 080522
VDAC 1 TCT1 MCT1 24 MCT8 C47/C48 to enable Switching regulator.
8111D IO_CASE_GND
8111D LAN_TX0+ 3 TD1- MC1- 22 TX0+ Remove R68, C48 and change C47 to 0 LIO_GND
Place close to Pin2 LAN_TX2+ 5 1CT:1CT
TD2+ MX2+ 20 TX2+
ohm to disable switching regulator. For
AVDD33
PWR_+V3.3AL
C602
VDAC 4 TCT2 MCT2 21 MCT7
RTL8102E remove R68, C47 and C48.
C548 LAN_TX2- 6 19 TX2-
0.1UF/25V,Y5V 0.1uF/25V,Y5V LAN_TX3+ TD2-
1CT:1CT MX2- TX3+
8 TD3+ MX3+ 17
C0402 C0402 R457
8111D VDAC 7 18 MCT6 0
Place close to pin 59 TCT3 MCT3 ns
LAN_TX3- 9 16 TX3-
LAN_TX1- TD3-
1CT:1CT MX3- TX1- RJ45_TX2- RJ45_TX3-
11 TD4+ MX4+ 14
D52
VDAC 10 15 MCT5 AZC099-04S
TCT4 MCT4

4
SOT23_6
C609 C608 LAN_TX1+ 12 13 TX1+ ns
TD4- MX4-
0.01uF/25V,Y5V 0.01uF/25V,Y5V 8111D Tran24_1_7d1
8111D 8111D

LIO_GND

3
RJ45_TX2+ RJ45_TX3+
add two cap place close to pin 11,14
R972
R0805
FB12
0 8101E/8102E AVDD18 U33
TRAN16_50_272 IO_CASE_GND
RN9
L1 Place close to AVDD18 Pins(Pin5,8) 13 N4 N2 5 0x4
CTRL18 FB38 0 R0805 12 4 TX2+ 1 2 RJ45_TX2+
1 N3 N1
4.7uH/0.9A TX2- 3 4 Colay
RJ45_TX2- CHOCK AND RN
C553 VDAC LAN_TX0- 9 8 TX0- TX3+ 5 6 RJ45_TX3+ PWR_+V3.3AL
C0805 C552 C554 C555 C600 C601 TD- TX- TX3- RJ45_TX3-
7 8
8111D C0402 C0402 C0402 C0402 C0402 11 6 MCT5
10UF/6.3V,X5R 0.1UF/25V,Y5V 0.1UF/25V,Y5V 0.1uF/25V,Y5V 0.1uF/25V,Y5V TDC CMT RA0603_8
B Colay 8111D follow demo board 8101E/8111D 0.1UF/25V,Y5V 8111D 8111D LAN_TX0+ TX0+ 8111D B
10 TD+1CT:1CT TX+ 7
8101E/8111D 8101E/8111D
L1 close to Pin1,C553 close to L1 LAN_TX1- 15 2 TX1- R458 IO_CASE_GND
RD- RX-
0
14 3 MCT6 RN8 RJ45_TX0- ns RJ45_TX1+ RJ1
RDC RXC
Place close to EVDD Pins(Pin 22,28) 0x4 RJ45

9
R938 0 R0805 EVDD18 LAN_TX1+ 16 1 TX1+ RA0603_8 D43 RJ45_SC
8101E/8111D C574 C575 RD+1CT:1CT RX+ TX0- RJ45_TX0- AZC099-04S RJ45
1 2

4
C556 C557 C558 C0402 C0402 TX0+ 3 4 RJ45_TX0+ SOT23_6
C0402 C0402 C0805 0.01UF/25V,Y5V 0.01UF/25V,Y5V TX1- 5 6 RJ45_TX1- ns RJ45_TX0+ 1 TX0+
0.1UF/25V,Y5V 0.1UF/25V,Y5V 1uF/25V,Y5V 8101E/8102E 8101E/8102E 8101E/8102E TX1+ 7 8 RJ45_TX1+ RJ45_TX0- 2 TX0- TX0+
RJ45_TX1+ 3 TX1+ TX0-
R973 8101E 8102E/8111D RJ45_TX2+ 4 TX2+ TX1+
TX2+
0 RJ45_TX2- 5 TX2- TX2-
Colay 8111D R0805 RJ45_TX1- 6 TX1- TX1-
8111D LIO_GND RJ45_TX3+ 7 TX3+ TX3+
DVDD15 RJ45_TX3- 8 TX3- TX3-

3
R974
R0805
DVDD15/VDD33 0

10
8101E/8102E RJ45_TX0+ RJ45_TX1-

C566 C567 C568 C569 C570 C571 C572 C605 C606 C607
10UF/6.3V,X5R 0.1UF/25V,Y5V 0.1UF/25V,Y5V 0.1UF/25V,Y5V 0.1UF/25V,Y5V 0.1UF/25V,Y5V 0.1UF/25V,Y5V C0402 C0402 C0402 IO_CASE_GND
C0805 C0402 C0402 C0402 C0402 C0402 C0402 0.1uF/25V,Y5V 0.1uF/25V,Y5V 0.1uF/25V,Y5V MCT8
8101E 8101E/8102E 8101E/8102E 8111D 8111D 8111D MCT7 IO_CASE_GND
MCT5
Place close to DVDD15 Pins MCT6
pin 15,21,43,49,58 *8111C(P)/8111D's Pin58 is AVDD which RJ45_TX2+
RJ45_TX2-
connects to DVDD because AVDD and RJ45_TX3+

LAN_TX0+

LAN_TX1+
LAN_TX0-

LAN_TX1-
DVDD are connected together. RJ45_TX3-

R945 R946 R947 R948 R949 R950 R976 R977

R941 R942 R943 R944 75 75 75 75 75 75 75 75
49.9,1% 49.9,1% 49.9,1% 49.9,1% R0402 R0402 R0402 R0402 R0402 R0402 R0402 R0402
R0402 R0402 R0402 R0402 8101E/8102E
8101E 8101E 8101E 8101E 8101E/8102E 8101E/8102E 8111D 8111D
8101E/8102E

C576 C577
C0402 0.01UF/25V,Y5V C578
0.01UF/25V,Y5V C0402 C1206
AVDD18 VDAC 8101E 8101E 1000pF/2000V

R940 0 R0402 LIO_GND LIO_GND

8101E place close to IC place close to transformer IO_CASE_GND
PH6 PH5 PH4

VDD3D3_LAN R975
R0805 HOLE HOLE HOLE
1

DVDD15/VDD33 TH_236_100 TH_236_100 TH_315_118

A 0 ns ns ns A
8111D C603 C604
C0402
8111D 10uF/6.3V,X5R 0.1uF/25V,Y5V
C0805 8111D
GND_JACK GND_JACK IO_CASE_GND

LIO_GND

TOPSTAR TECHNOLOGY
Joseph
Page Name Power_LAN Board
Size Project Name Rev
A1 C49 A
Date: Friday, May 07, 2010 Sheet 57 of 59
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained with the
expressed written consent of TOPSTAR
5 4 3 2 1
 5 4 3 2 1

A_+V5AL

A_USB_+V5AL
USB IF1 1.6A FUSE1812
Co-layout CT32-CT6032 1 2

100uF/10V,TAN
IR9 300K A_USB_OC#5
IC18
+ + IC19
100uF/10V,TAN IR10 IC20
CT6032 CT7343_28 560K 1000pF/50V,X7R
ns ns

USB2
VCC1 4 Keep USB2.0 Signal stub short
ICHK1 ns
5 HOLE0
D 6 3 -DATA10 4 3 A_USB_PN10 D
HOLE1 -DATA1 +DATA10 A_USB_PP10
7 HOLE2 +DATA1 2 1 2
8 HOLE3
1 90Ω/100MHz 0.5A
GND L4_0805
USB_8

1
USB1F IR11 0
620700400002
IC21 IESD1 IESD2 IR12 0
330PF/50V,X7R

2
ESDPAD_R0603 ESDPAD_R0603
EGA1-0603-V05 EGA1-0603-V05

Aud-GND
A_USB_+V5AL

USB3 USB_AUDIO_CONN2
Keep USB2.0 Signal stub short
VCC1 4 1 1
ICHK2 ns
5 HOLE0 A_+INTSPR 2 2
6 3 -DATA11 4 3 A_USB_PN11 3
HOLE1 -DATA1 A_-INTSPR 3
7 2 +DATA11 1 2 A_USB_PP11 4
HOLE2 +DATA1 4
8 HOLE3 A_SURR_OUT_L 5 5
1 90Ω/100MHz 0.5A 6
GND A_HP_DET 6
L4_0805 7
A_SURR_OUT_R 7 Aud-GND
USB_8 8
USB1F IR13 0 8
A_MIC2_REF 9 9
620700400002 IC22 10
A_MIC2_L 10
1

IR14 0 11
330PF/50V,X7R A_MIC1_JD 11
A_MIC2_R 12 12 25 25
IESD3 IESD4 13 26
13 26
A_USB_OC#5 14 14
2

ESDPAD_R0603 ESDPAD_R0603 15
EGA1-0603-V05 EGA1-0603-V05 15
A_USB_PN10 16 16
A_USB_PP10 17 17
C 18 18
C
A_USB_PN11 19 19
A_USB_PP11 20 20
21 21
22 22
23 23
24 24

24pin 0.5mm bot FFC

A_+V5AL

Audio
FB0805
LINE_OUT1
L 4 FB39 2 1 300ohm@100MHz,2A A_SURR_OUT_L
5 FB0805
3 FB40 2 1 300ohm@100MHz,2A A_SURR_OUT_R
R 2
A_HP_DET
1
2

2SJ1512
1

D44 D45 C579 C580 R951 R952 C581 D46

EGA1-0603-V05 EGA1-0603-V05 100pF/50V,NPO 100pF/50V,NPO 22k 22k 0.1uF/10V,X7R EGA1-0603-V05 INTSPK2
ESDPAD_R0603 ESDPAD_R0603 C0402 C0402 R0402 R0402 C0402 ESDPAD_R0603 INT_spkR 2Pin
1

ns CNS2_R
ns ns ns ns
2

4 A_+INTSPR
4 2 2

3 1 A_-INTSPR
Aud-GND Aud-GND Aud-GND Aud-GND Aud-GND Aud-GND Aud-GND Aud-GND Aud-GND 3 1

B B

Aud-GND

D47
SOD323
1N4148WS
2 1 A_MIC2_REF

2 1
D48
1N4148WS
SOD323

R953 R954 UH2 UH3

4.7K 4.7K
R0402 R0402

FB0805
MIC_IN1 L 4 FB41 2 1 300ohm@100MHz,2A A_MIC2_L
5 FB0805 HOLE HOLE

1
3 FB42 2 1 300ohm@100MHz,2A A_MIC2_R TH_236_100 TH_236_100
R 2 ns ns
A_MIC1_JD
1
2

2SJ1512
1

D49 D50 C582 C583 C584 C585 D51 Aud-GND

EGA1-0603-V05 EGA1-0603-V05 100pF/50V,NPO 100pF/50V,NPO 100pF/50V,NPO 100pF/50V,NPO C586 EGA1-0603-V05
ESDPAD_R0603 ESDPAD_R0603 C0402 C0402 C0402 C0402 0.1uF/10V,X7R ESDPAD_R0603
1

ns ns C0402 ns
ns ns
2

Aud-GND Aud-GND Aud-GND Aud-GND Aud-GND Aud-GND Aud-GND Aud-GND Aud-GND FD9 FD10 FD11 FD12 FD13

1 1 1 1 1 1 1 1 1 1
A R340 0 FMARKS FMARKS FMARKS FMARKS FMARKS A
R341 0 ns ns ns ns ns
R352 0

Aud-GND TOPSTAR TECHNOLOGY

Joseph
Page Name USB_Audio Board
Size Project Name Rev
Custom C49
A
Date: Friday, May 07, 2010 Sheet 58 of 59
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5 4 3 2 1
 5 4 +V3.3S_SB 3 2 1

SBR409
10K
R0402

SBD53

1
D 1N4148WS D
SOD323

Switch1
SWITCH Board Conn
3 4

3
SBC306
SBD31
100pF/50V,NPO
1 2
SBSW1 BAT54SPT +V3.3S_SB
TMG-534-V

2
BUTTON4_S

SB_GND SB_GND+V3.3S_SB SBC333 SBC138

1000pF/50V,X7R
C0402 1uF/10V,X7R
+V3.3S_SB C0603
1 1
2 2
SB_GND 3 3 9 9
4 4
Switch1 5
SBR410 5
6 6 8 8
10K Switch2 7 7
R0402
CNS7_0D5_RA1
C Conn 7Pin C
SBCON2

SBD54

1
1N4148WS
SOD323
要修改CON 的Footprint，PN，Value

Switch2

3 4

3
SBC307 SBD32

100pF/50V,NPO 1
SBSW2
2 BAT54SPT
一个是WIFI开关。
TMG-534-V
一个是电源管理开关。（各种模式切换）

2
BUTTON4_S

+V3.3S_SB

B SBH25 B

HOLE

1
TH_260_220_205
ns

SB_GND
SB_GND

A TOPSTAR TECHNOLOGY A
Joseph
Page Name SWITCH Board
Size Project Name Rev
A3 C49
A
Date: Friday, May 07, 2010 Sheet 59 of 59
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR