G.S.Mandal’s G.S.

Mandal’s
MIT POLYTECHNIC,ROTEGAON(0777) MIT POLYTECHNIC,ROTEGAON(0777)
UNIT TEST II UNIT TEST II
Course : Comp. Engg. & Tech. Course Code : CO/CM5G Semester : Fifth Course : Comp. Engg. & Tech. Course Code : CO/CM5G Semester : Fifth
Subject : Operating System Subject Code : 17512 Subject : Operating System Subject Code : 17512
Time : 1 Hour Date : /10/2015 Max Marks : 25 Time : 1 Hour Date : /10/2015 Max Marks : 25
Instructions : 1.Illustrate your answer with neat sketches wherever Instructions : 1.Illustrate your answer with neat sketches wherever
necessary necessary
2.Figures to the right indicate full marks. 2.Figures to the right indicate full marks.

Q.1. Attempt any THREE
a) What is threading & Multithreading.
b) State & explain criteria in CPU Scheduling.
c) Compare FCFS & SJF Scheduling algorithm.
d) What is Deadlock & give characteristics of Deadlock.
Q.2. Attempt any TWO
a) Difference between Linux & Unix .
b) List & explain architecture of file.
c) Explain the concepts of virtual memory in detail.
09 Marks Q.1. Attempt any THREE 09 Marks
a) What is threading & Multithreading.
b) State & explain criteria in CPU Scheduling.
c) Compare FCFS & SJF Scheduling algorithm.
d) What is Deadlock & give characteristics of Deadlock.
08 Marks Q.2. Attempt any TWO 08 Marks
a) Difference between Linux & Unix .
b) List & explain architecture of file.
c) Explain the concepts of virtual memory in detail.

Q.3. Attempt any TWO
a) Explain Banker’s Algorithm for Deadlock prevention.
b) List & state in one sentence, Eight different type of file .
c) Differentiate between premitive & non premitive .
d) Explain Round Robin Scheduling with simple example.
08 Marks Q.3. Attempt any TWO 08 Marks
a) Explain Banker’s Algorithm for Deadlock prevention.
b) List & state in one sentence, Eight different type of file .
c) Differentiate between premitive & non premitive .
d) Explain Round Robin Scheduling with simple example.
 G.S.Mandal’s G.S.Mandal’s
MIT POLYTECHNIC,ROTEGAON(0777) MIT POLYTECHNIC,ROTEGAON(0777)
UNIT TEST II UNIT TEST II
Course : Comp. Engg. & Tech. Course Code : CM5G Semester : Fifth Course : Comp. Engg. & Tech. Course Code : CM5G Semester : Fifth
Subject : System Programming Subject Code : 17517 Subject : System Programming Subject Code : 17517
Time : 1 Hour Date : /10/2015 Max Marks : 25 Time : 1 Hour Date : /10/2015 Max Marks : 25
Instructions: 1.Illustrate your answer with neat sketches wherever Instructions: 1.Illustrate your answer with neat sketches wherever
necessary necessary
2. Figures to the right indicate full marks. 2. Figures to the right indicate full marks.

Q.1. Attempt any THREE 09 Marks Q.1. Attempt any THREE 09 Marks
a) Define: - a) Allocation b) Relocation c) linking d) loading. a) Define: - a) Allocation b) Relocation c) linking d) loading.

b) Explain single pass algorithm of macroprocessor. b) Explain single pass algorithm of macroprocessor.

c) Explain READ function used for MACRO expansion with flowchart. c) Explain READ function used for MACRO expansion with flowchart.

d) Describe conditional macro expansion with suitable example. d) Describe conditional macro expansion with suitable example.

Q.2. Attempt any TWO 08 Marks Q.2. Attempt any TWO 08 Marks

a) Write the function of ESD, RLD, TXT and END cards in the object deck a) Write the function of ESD, RLD, TXT and END cards in the object deck
and advantage of direct linking loader. and advantage of direct linking loader.

b) Explain overlay structure used in dynamic loading scheme. b) Explain overlay structure used in dynamic loading scheme.

c) Explain code optimization phase of compiler. c) Explain code optimization phase of compiler.

Q.3. Attempt any TWO 08 Marks Q.3. Attempt any TWO 08 Marks
a) Draw the block diagram of phase of compiler and indicate the main a) Draw the block diagram of phase of compiler and indicate the main
function of each phase. function of each phase.

b) Compare following: - compiler and translator. b) Compare following: - compiler and translator.

c) Explain Binders in detail. c) Explain Binders in detail.

 G.S.Mandal’s G.S.Mandal’s
MIT POLYTECHNIC,ROTEGAON(0777) MIT POLYTECHNIC,ROTEGAON(0777)
UNIT TEST II UNIT TEST II
Course : Comp. Engg. & Tech. Course Code : CO4G Semester : Fourth Course : Comp. Engg. & Tech. Course Code : CO4G Semester : Fourth
Subject : Computer Network Subject Code : 17429 Subject : Computer Network Subject Code : 17429
Time : 1 Hour Date : /02/2015 Max Marks : 25 Time : 1 Hour Date : /02/2015 Max Marks : 25
Instructions : 1.Illustrate your answer with neat sketches wherever Instructions : 1.Illustrate your answer with neat sketches wherever
necessary necessary
2.Figures to the right indicate full marks. 2.Figures to the right indicate full marks.

Q.1. Attempt any THREE 09 Marks Q.1. Attempt any THREE 09 Marks
a) Explain RARP. a) Explain RARP.
b) Comparisons between IPv4 and IPv6. b) Comparisons between IPv4 and IPv6.
c) Describe the characteristics of satellite microwave transmission. c) Describe the characteristics of satellite microwave transmission.
d) Describe OSI model with suitable diagram. d) Describe OSI model with suitable diagram.
Q.2. Attempt any TWO 08 Marks Q.2. Attempt any TWO 08 Marks
a) Give the functions of data link layer. a) Give the functions of data link layer.
b) Explain Interface Data Unit and Protocol Data Unit. b) Explain Interface Data Unit and Protocol Data Unit.
c) Distinguish between UTP and STP. c) Distinguish between UTP and STP.
Q.3. Attempt any TWO 08 Marks Q.3. Attempt any TWO 08 Marks
a) State three types of network cables. a) State three types of network cables.
b) Compare OSI and TCP/IP reference model. . b) Compare OSI and TCP/IP reference model. .
c) List the two protocols each associated with application layer, session c) List the two protocols each associated with application layer, session
layer, transport layer, network layer of OSI model. layer, transport layer, network layer of OSI model.
d) Difference between SLIP and PPP. d) Difference between SLIP and PPP.
 G.S.Mandal’s G.S.Mandal’s
MIT POLYTECHNIC,ROTEGAON(0777) MIT POLYTECHNIC,ROTEGAON(0777)
UNIT TEST II UNIT TEST II
Course : Comp. Engg. & Tech. Course Code : CO4G Semester : Fourth Course : Comp. Engg. & Tech. Course Code : CO4G Semester : Fourth
Subject : Advance Microprocessor (EL) Subject Code : 17627 Subject : Advance Microprocessor (EL) Subject Code : 17627
Time : 1 Hour Date : /02/2015 Max Marks : 25 Time : 1 Hour Date : /02/2015 Max Marks : 25
Instructions : 1.Illustrate your answer with neat sketches wherever Instructions : 1.Illustrate your answer with neat sketches wherever
necessary necessary
2.Figures to the right indicate full marks. 2.Figures to the right indicate full marks.

Q.1. Attempt any THREE 09 Marks Q.1. Attempt any THREE 09 Marks
a) List salient features of 80586 (Pentium). a) List salient features of 80586 (Pentium).

b) Describe the concept of separate code and data cache of 80586. b) Describe the concept of separate code and data cache of 80586.

c) State the important concepts of dynamic execution of c) State the important concepts of dynamic execution of
instruction in Pentium Pro architecture. instruction in Pentium Pro architecture.

d) Describe MMX architecture. d) Describe MMX architecture.

Q.2. Attempt any TWO 08 Marks Q.2. Attempt any TWO 08 Marks
a) Explain the super scalar execution in Pentium processor. a) Explain the super scalar execution in Pentium processor.

b) List the advantages of RISC processor. b) List the advantages of RISC processor.

c) State and describe design issues of RISC processors. c) State and describe design issues of RISC processors.

Q.3. Attempt any TWO 08 Marks Q.3. Attempt any TWO 08 Marks
a) State the basic features of RISC processors. a) State the basic features of RISC processors.

b) List the features of SUN ultra SPARC. b) List the features of SUN ultra SPARC.

c) Describe the X86 interrupts. c) Describe the X86 interrupts.