VISVESVARAYA TECHNOLOGICAL UNIVERSITY, BELAGAVI

ANALOG & DIGITAL ELECTRONICS LABORATORY

[18CSL37]

S.J.C INSTITUTE OF TECHNOLOGY, CHICKBALLAPUR

DEPARTMENT OF INFORMATION SCINECE AND ENGINEERING

2018-2019
Course objectives:
This laboratory course enables students to get practical experience in design, assembly and
evaluation/testing of
Analog components and circuits including Operational Amplifier, Timer, etc.
Combinational logic circuits.
Flip - Flops and their operations
Counters and registers using flip-flops.
Synchronous and Asynchronous sequential circuits.
A/D and D/A converters

Course Outcomes:
The student should be able to:
Use appropriate design equations / methods to design the given circuit.
Examine and verify the design of both analog and digital circuits using simulators.
Make us of electronic components, ICs, instruments and tools for design and testing of circuits for
the given the appropriate inputs.
Compile a laboratory journal which includes; aim, tool/instruments/software/components used,
design equations used and designs, schematics, program listing, procedure followed, relevant
theory, results as graphs and tables, interpreting and concluding the findings.

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 Laboratory Programs

PART A (Analog Electronic Circuits)

1. Design an astable multivibrator ciruit for three cases of duty cycle (50%, <50% and >50%) using
NE 555 timer IC. Simulate the same for any one duty cycle.

2. Using ua 741 Opamp, design a 1 kHz Relaxation Oscillator with 50% duty cycle. And simulate
the same.

3. Using ua 741 opamap, design a window comparator for any given UTP and LTP. And simulate the
same.

PART B (Digital Electronic Circuits)

4. Design and implement Half adder, Full Adder, Half Subtractor, Full Subtractor using basic gates.
And implement the same in HDL.

5. Given a 4-variable logic expression, simplify it using appropriate technique and realize the
simplified logic expression using 8:1 multiplexer IC. And implement the same in HDL.

6. Realize a J-K Master / Slave Flip-Flop using NAND gates and verify its truth table. And
implement the same in HDL.

7. Design and implement code converter I)Binary to Gray (II) Gray to Binary Code using basic
gates.

8. Design and implement a mod-n (n<8) synchronous up counter using J-K Flip-Flop ICs and
demonstrate its working.

9. Design and implement an asynchronous counter using decade counter IC to count up from 0 to n
(n<=9) and demonstrate on 7-segment display (using IC-7447)

Conduct of Practical Examination:

Experiment distribution
For laboratories having only one part: Students are allowed to pick one experiment from the
lot with equal opportunity.
For laboratories having PART A and PART B: Students are allowed to pick one experiment
from PART A and one experiment from PART B, with equal opportunity.
Change of experiment is allowed only once and marks allotted for procedure to be made zero
of the changed part only.
Marks Distribution (Courseed to change in accoradance with university regulations)
For laboratories having only one part – Procedure + Execution + Viva-Voce: 15+70+15=100 Marks
For laboratories having PART A and PART B
Part A – Procedure + Execution + Viva = 6 + 28 + 6 = 40 Marks
Part B – Procedure + Execution + Viva = 9 + 42 + 9 = 60 Marks

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 Analog Electronics Hardware Experiments
PART - A
Analog Electronics Experiments

1. Design an astable multivibrator circuit for three cases of duty cycle (50%, <50% and >50%)
using NE 555 timer IC. Simulate the same for any one duty cycle.

Description:
Multivibrator is a form of oscillator, which has a non-sinusoidal output. The output waveform is
rectangular. The multivibrators are classified as
i)Astable or free running multivibrator It alternates automatically between two states (low
and high for a rectangular output) and remains in each state for a time dependent upon the circuit
constants. It is just an oscillator as it requires no external pulse for its operation.
ii)Monostable or one shot multivibrators: It has one stable state and one quasi stable. The
application of an input pulse triggers the circuit time constants and the output goes to the quazi
stable state, after a period of time determined by the time constant, the circuit returns to its initial
stable state. The process is repeated upon the application of each trigger pulse.
iii)Bistable Multivibrators: It has both stable states. It requires the application of an
external triggering pulse to change the output from one state to other. After the output has changed
its state, it remains in that state until the application of next trigger pulse. Flip flop is an example.
Components Required:
555 Timer IC, Resistors of 3.3KΩ, 6.8KΩ, Capacitors of C=0.1 μF, C’=0.01 μF, digital trainer kit(used
to give +5v power supply to 555 IC),CRO.
Design:
For astable multivibrator
TON= 0.693 (RA+RB) C
TOFF=0.693 RB C
With the diode connected in parallel with RB the effect of RB is shunted during charging of the capacitor,
therefore the equations for TON and TOFF is given by
TON= 0.693 RA C
TOFF=0.693 RB C

Case 1: 50% duty cycle

Let Frequency =1kHz, T=1ms, C=0.1 μF
TON = TOFF=0.5ms
For RA, 0.5ms= 0.693 * RA *0.1 *10-6
RA =7.2 kΩ= RB
Case 2: >50% duty cycle, let Duty cycle be 75%
Let Frequency =1kHz, T=1ms, C=0.1 μF
TON = 0.75ms
TOFF= 0.25ms
For RA, 0.75ms= 0.693 * RA *0.1 *10-6
RA =10 kΩ
For RB, 0.25ms= 0.693 * RA *0.1 *10-6

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RB =3.6 kΩ

Case 3: <50% duty cycle, let Duty cycle be 25%

Let Frequency =1kHz, T=1ms, C=0.1 μF
TON = 0.25ms
TOFF= 0.75ms
For RA, 0.25ms= 0.693 * RA *0.1 *10-6
RA =3.6 kΩ
For RB, 0.75ms= 0.693 * RA *0.1 *10-6
RB =10 kΩ
Circuit Diagram:
Figure 1: astable mutivibrator
Connect the pin 2 to the CRO to get the capacitor waveform check the amplitude from the waveform to
get the UTP and LTP values.
Connect pin 3 to CRO to get the output. Find out the TH and TL values.
Procedure:
1. Before making the connections, check the components using multimeter.
2. Make the connections as shown in figure and switch on the power supply.
3. Observe the capacitor voltage waveform at 6th pin of 555 timer on CRO.
4. Observe the output waveform at 3rd pin of 555 timer on CRO (shown below).
5. Note down the amplitude levels, time period and hence calculate duty cycle.

Circuit Diagram and actual connections

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 Simulation:
Circuit diagram: Astable multivibrator for duty cycle >50%

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OUTPUT WAVEFORM

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 Simulation

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 Digital Electronics Hardware Experiments
Logic gates symbols and description

Pin diagrams of Basic gates: AND (IC 7408), OR(IC 7432) & NOT(IC 7404)

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 Pin diagrams of universal gates: NAND (IC 7400) & NOR(IC 7402)

Pin diagram of Triple 3 input AND gate IC 7411 Pin diagram of Dual 4 input OR gate IC 4072

Pin Diagrams

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4. Design and implement Half adder, Full Adder, Half Subtractor, Full Subtractor using basic gates.
And implement the same in HDL.

Components Used:IC 74LS08, 7432, 7404, Patch Chords, Power chords, Trainer kit.

HALF ADDER:
For designing a half adder logic circuit, we first have to draw the truth table for two input variables
i.e. the augend and addend bits, two outputs variables carry and sum bits. In first three binary
additions, there is no carry hence the carry in these cases are considered as0.

TRUTH TABLE FOR HALF ADDER:

Figure 4.1 Half Adder Truth Table

For above truth table we get,

Hence, the logical design of Half Adder would be

A B
1 3

Sum

Carry
10

Figure 4.2 Half Adder Circuit Diagram

FULL ADDER:
Full adder is a conditional circuit which performs full binary addition that means it adds two bits and
a carry and outputs a sum bit and a carry bit. Any bit of augend can either be 1 or 0 and we can
represent with variable A, similarly any bit of addend we represent with variable B. The carry after
addition of same significant bit of augend and addend can represent by C. Hence truth table for all
combinations of A, B and C is asfollows,

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Figure 4.3 Full Adder Truth Table

From the above table, we can draw Kmap for sum (s) and final carry (Cout).

Hence, from Kmaps,

Cout = BC + AC + AB

Circuit diagram

1 3 5

2 4 6 1
2
13 12
3
4 6 2
5 3 1
9 4
10 8 5
11
1
2 12
13

1 3
2
9
4 6 10 13
5 11
12
9 8
10

Figure 4.4 Full Adder Circuit Diagram

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Analog And Digital Electronics Lab CBCS Scheme

HALF SUBTRACTOR:

Half substractor is a combinational circuit which performs substraction of single bit binary
numbers. The substraction combinations of two single bit binary numbers can be,

Now if we draw a truth table for that, with all differences (D) and borrow (b), we get,

Figure 4.5 Half Subtractor Truth Table

Hence, from truth table it is found that,

The above equations can be represented using logic gates.

A B
1 3

6 2 Diff

10

Figure 4.6 Half Subtractor Circuit Diagram

FULL SUBSTRACTOR:
This is not practical to perform subtraction only between two single bit binary numbers. Instead binary
numbers are always multibits. The subtraction of two binary numbers is performed bit by bit from right (LSB)
to left (MSB). During subtraction of same significant bit of minuend and subtrahend, there may be one
borrow bit along with difference bit. This borrow bit (either 0 or 1) is to be added to the next higher significant
bit of minuend and then next corresponding bit of subtrahend to be subtracted from this. It will continue up
to MSB. The combinational logic circuit performs this operation is called full subtractor. Hence, full subtractor
is similar to half subtractor but inputs in full subtractor are three instead of two. Two inputs are for the
minuend and subtrahend bits and third input is for borrowed which comes from previous bits subtraction.
The outputs of full adder are similar to that of half adder, these are difference (D) and borrow (b). The
combination of minuend bit (A), subtrahend bit (B) and input borrow (bi) and their respective differences (D)
and output borrows (b) are represented in a truth table, asfollow

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Analog And Digital Electronics Lab CBCS Scheme

Figure 4.7 Full Subtractor Truth Table

Diff = A'B'bi+A'Bbi’+AB'bi’+ABbi

13 12

1
Difference
10
11
1’
2’ 12’
13’
10
3’ 11
4’ 6’ 12
5’

Figure 4.8 Full Subtractor Circuit Diagram

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 Analog And Digital Electronics Lab CBCS Scheme

Simulation:
VHDL code for adder, subtractor
library ieee;
use ieee.std_logic_1164.all;
entity adder is
port(a,b,c: in std_logic;
HAsum, HAcout, FAsum, FAcout, HSdiff, HSborr, FSdiff, FSborr: out std_logic);
end adder;
architecture dataflow of adder is
begin
HAsum<=
HAcout <=
FAsum<=
FAcout <=
HSdiff<=
HSborr <=
FSdiff<=
FSborr <=
end dataflow;
Waveform:

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5. Given a 4-variable logic expression, simplify it using appropriate technique and realize the
simplified logic expression using 8:1 multiplexer IC. And implement the same in HDL.

Components Used:IC 74LS151, Patch Chords, Power chords, Trainer kit.

Example: Simplify the following function using EVM technique

Y = f(a,b,c,d)=∑m(2,3,4,5,13,15) + dc(8,9,10,11)
Note: Examiner may ask the student to simplify any other Boolean expression in the exam.

Table 5.1 the EVM selection of entered variable and mapping with f
Decimal MSBLSB f EVM entry Description for EVM entry
ABCD
0 000 0 0 Since regardless of changes in input bit D
1 000 1 0 0=D0 output remains 0
2 001 0 1 Since regardless of changes in input bit D
3 001 1 1 1=D1 output remains 1
4 010 0 1 Since regardless of changes in input bit D
5 010 1 1 1=D2 output remains 1
6 011 0 0 Since regardless of changes in input bit D
7 011 1 0 0=D3 output remains 0
8 100 0 X Since regardless of changes in input bit D
9 100 1 X X=D4 output is X
10 101 0 X Since regardless of changes in input bit D
11 101 1 X X=D5 output is X
12 110 0 0 SinceasinputbitDchangesoutputchanges
13 110 1 1 D=D6
14 111 0 0 SinceasinputbitDchangesoutputchanges
15 111 1 1 D=D7

Pin Diagram of ICs Used:

DUAL IN-LINE PACKAGE
DATAINPUTS (MS)

VccD4 D5 D6 D7 A B

16 15 14 13 12 11 10 9
74LS151
1 2 3 4 5 6 7 8

D3 D2 D1 D0 Y W STROBEGND

DATAINPUTS (LS)

Figure 5.1 The pin diagram of 74LS151

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CIRCUIT DIAGRAM

4: D0 Vcc: 16
3:D1
GND: 8
2:D2

1: D3 Y: 5

74LS151 (8:1 MUX)

15: D4
X
14:D5

13:D6

12: D7

7 9:S2 10:S111:S0

ABC

Figure 5.2 Circuit diagram for the given expression Y

Procedure:
1. Verify all the components and patch chords for their workingconditions.
2. Connect all the 1’s from the EVM table EVM entries to high input from the IC trainer’s
kit(i.e.D1, D2 for the givenexample).
3. Connect all the 0’s from the EVM table EVM entries to low input from the IC trainer’s kit (i.e.D0,
D3 for the givenexample).
4. Connect all the X’s from the EVM table EVM entries to low/high input from the IC trainer’s kit(i.e.D4,
D5 for the given example).
5. Connect all the D’s from the EVM table EVM entries to D input from the IC trainer’s kit (i.e.D6,
D7 for the givenexample).
6. If there are any D present in the simplification then, using a NOT gate connect the input D to
pin 1of NOT gate and pin 2 the output i.e., inverted D to the corresponding data pin of74151.
7. Connect A, B and C select lines to pin numbers 9, 10 and 11respectively.
8. Output is available at pin no5.
9. Connect pin No: 8 is ground and pin No:16 is Vcc and pin No:7 is connected toground.
10. Now switch the power button of trainer’skit.
11. Realize all the outputs for the corresponding input(ABC) combinations. Change the 3 inputs A,
B and C only and observe the output at pin No:5 and if the output depends on D then use it
accordingly to get the correspond output. For example in the given expression for inputs 12, 13,
14 and 15 the output depends only on D when ABCs are at 110 and111.
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 Analog And Digital Electronics Lab CBCS Scheme
VHDL code for 8 to 1 MUX (behavioral modeling):
library IEEE;
use IEEE.STD_LOGIC_1164.ALL; // includes the standard library
entity mux1 is
Port ( d : in std_logic_vector(7 downto 0);
sel : in std_logic_vector(2 downto 0); //Input and output is declared as ports
zout : out std_logic);
end mux1;
architecture Behavioral of mux1 is
begin
zout<= d(0) when sel="000" else // Based on the value of selection the value of data
d(1) when sel="001" else //stored in the array I is stored in zout
d(2) when sel="010" else
d(3) when sel="011" else
d(4) when sel="100" else
d(5) when sel="101" else
d(6) when sel="110" else
d(7);
end Behavioral;
TruthTable
INPUTS OUTPUTS
sel (2) sel (1) sel (0) Zout
0 0 0 d(0)
0 0 1 d(1)
0 1 0 d(2)
0 1 1 d(3)
1 0 0 d(4)
1 0 1 d(5)
0 1 1 d(6)
1 1 1 d(7)
Wavefrom: Output
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6. Design and implement code converter I)Binary to Gray II) Gray to Binary Code using
basicgates.

Components Used:IC 74LS151, Patch Chords, Power chords, Trainer kit.

Binary to Gray Code Converter

The logical circuit which converts binary code to equivalent gray code is known as binary to gray code converter. The
gray code is a non weighted code. The successive gray code differs in one bit position only that means it is a unit
distance code. It is also referred as cyclic code. It is not suitable for arithmetic operations. It is the most popular of the
unit distance codes. It is also a reflective code. An n-bit Gray code can be obtained by reflecting an n-1 bit
codeaboutanaxisafter2n-1rows,andputtingtheMSBof0abovetheaxisandtheMSBof1belowtheaxis.
Reflection of Gray codes is shown below. The 4 bits binary to gray code conversion table is

G 4G 3G 2G 1

G2G1 Changes by 1 bit position

Mirror of the above change inG2G1

Mirror of the above change inG2G1

Mirror of the above change inG2G1

Figure 6.1 Binary to Gray Code Converter Truth Table

given below, That means, in 4 bit gray code, (4-1) or 3 bit code is reflected against the axis drawn
after (24-1)th or 8th row. The bits of 4 bit gray code are considered as G4G3G2G1. Now from

conversion table, From above SOPs, let us draw K -maps for G4, G3, G2 and G1.
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Analog And Digital Electronics Lab CBCS Scheme

Design of binary to gray code convertor

Figure 6.2 Binary to Gray Code Converter K-Maps

Logical Circuit Diagram of binary to gray code convertor
A B C D
1 3 5 9

2 4 6 8 1 3
2
1
4 2 3 = G1
5 6

9
10 8
4
12 5 6 = G2
13 11

1
3
2 9
4 8 = G3
6 10
5
A = G4
Figure 6.3 Binary to Gray Code Converter Circuit Diagram

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Grey to Binary Code Converter

In gray to binary code converter, input is a multiplies gray code and output is its equivalent binary
code. Let us consider a 4 bit gray to binary code converter. To design a 4 bit gray to binary code

Figure 6.4 Gray to Binary Code Converter Truth Table

converter, we first have to draw a conversion table.

Design to convert gray to binary

Figure 6.5 Gray to Binary Code Converter K-Maps

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A B C D B4
1 3 5 9
2 4 6 8
1 3 B3
2 1 3
4 2
5 6
11
10
9 8
10 4 6 B2
12 5
13 11
12
13
1’ 3’
2’ 9
4’ 10 8
5’ 6’ B1

Figure 6.6: Gray to Binary convertor logic circuit diagram

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 Analog And Digital Electronics Lab CBCS Scheme

6. Realize a J-K Master / Slave Flip-Flop using NAND gates and verify its truth table. And
implement the same in HDL.

Components used:IC 74LS00, IC 74LS10, Power chords, Patch chords, Trainer kit.

Pin Details of the

ICs:74XX IC-7410

Theory: If both the J and K inputs are held at logic 1 and the CLK signal continues to change, the Q
and Q' outputs will simply change state with each falling edge of the CLK signal. (The master latch
circuit will change state with each rising edge of CLK.) We can use this characteristic to advantage in
a number of ways. A flip-flop built specifically to operate this way is typically designated as a T (for
Toggle) flip-flop. The lone T input is in fact the CLK input for other types of flip-flops.

CIRCUIT DIAGRAM:

Figure 8.1 The circuit diagram of Master-slave JK Flip Flop

In the circuit diagram 8.1 pin Nos: A1,A2, etc indicate pins of first 3 inputNAND(7410)
gate IC. Pin Nos: B1, B2, etc indicate pins of second 3 input NAND(7410) gate IC.
Pin Nos: C1, C2, etc indicate pins of 2 input NAND(7400) gateIC.

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PROCEDURE:
1. Take one 7400, a 2-input NAND gate, IC and two 7410, 3-input NAND gate,ICs.
2. Test all the ICs (7400 and 7410’s) before building thecircuit.
3. Let first 7410 IC be named as A, second 7410 IC as B and 7400 IC asC.
4. Since one 7410 has three number of 3-input NAND gates, our circuit needs 5 number of 3-input
NAND gates. So utilize all the 3 gates of first 7410 IC and use 2 gates of second 7410IC.
5. Build the circuit as shown in the figure 8.1 and provide the clock of 1Hz to pins A13, A3 and
C2,C4 of master and slave JK-flip flopsrespectively.
6. As per the figure 8.1 pin Nos:A2 and A4 are inputs J & K respectively. And pin Nos:A9 &
B13 presets(equal to 1). The pin Nos:C8 and C11 are outputs Q and invertedQ.
7. Connect all the IC’s pin No:7 to ground and pin No:14 toVcc.
8. Now switch on the trainer’skit.
9. Realize the following truth table of Master slave JK-Flip flop for various values of J & K as
per the truthtable.
10. For J=K=0 the output wouldn’t change indicating previous or laststate.
11. When J=1 and K=0 the output Q will be set to1.
12. And when J=0 and K=1 the output will be reset to0.
13. For the last combination when J=K=1, the circuit will produce toggling Q, that is the output
change from 0/1 to 1/0 back to 0/1 and soon.

Function Table: Table 8.1 JK-Flip Flop Function table

Clock J K Qn+1 Comment

0 0 Qn No change
(Last state)

0 1 0 Reset

1 0 1 Set

1 1 Q0 Toggle
 
(1 0 1 0)

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Simulation: VHDL code for JK master slave Flipflop

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity jkflip is
Port ( J, K, clk : in std_logic;
Q : buffer std_logic);
end jkflip;
architecture Behavioral of jkflip is
begin
process(clk)
begin
if rising_edge(clk) then
Q<= ((J and (not Q)) or ((not K) and Q));
end if;
end process;
end Behavioral;

8. Design and implement a mod-n (n<8) synchronous up counter using J-K Flip-
Flop ICs and demonstrate its working.

Components used: IC 74LS76, IC 74LS08, Patch chords, power chords, and Trainer kit.

K1 Q1 Q1 GND K2 Q2

16 15 14 13 12 11 10 9
74LS76
1 2 3 4 5 6 7 8

Clk1PR1 CLR1 J1 Vcc Clk2PR2

Figure 9.1 Pin diagram of 7476

Qn Qn+1 J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0

Figure 9.2 JK-Flip Flop Excitation table

Theory:
The ripple counter requires a finite amount of time for each flip flop to change state. This problem can
be solved by using a synchronous parallel counter where every flip flop is triggered in synchronism with
the clock, and all the output which are scheduled to change do so simultaneously. The counter
Analog And Digital Electronics Lab CBCS Scheme
progresses counting upwards in a natural binary sequence from count 000 to count 100 advancing
count with every negative clock transition and get back to 000 after this cycle.

Table 9.1 Transition & Excitation Table for Mod-5 counter.

Present State Next State Jc Kc Jb Kb Ja Ka
Qc Qb Qa Qc+1 Qb+1 Qa+1
0 0 0 0 0 1 0 x 0 x 1 x
0 0 1 0 1 0 0 x 1 x x 1
0 1 0 0 1 1 0 x x 0 1 x
0 1 1 1 0 0 1 x x 1 x 1
1 0 0 0 0 0 x 1 0 X 0 x
1 0 1 x x x x x x X x x
1 1 0 x x x x x x X x x
1 1 1 x x x x x x X x x
Simplified expressions for each input using K-maps (for Mod-5)

For For
Jc QbQa Qb Qa Qb Qa Qb Qa Qb
Kc Qb Qa Qa Qb Qa Qb Qa
Qc 0 0 1 0
Qc x x x x
Qc x x x x
Qc 1 x x x
Jc = QaQb
Kc = 1
For
Jb QbQa Qb Qa Qb Qa Qb Qa For
Qb
Qc 0 1 x x Kb Qb Qa Qa Qb Qa Qb Qa

Qc x x 1 0
Qc 0 x x x

Qc x x x x

Jb =Qa Kb =Qa

For For
Ja QbQa Qb Qa Qb Qa Qb Qa Qb
Ka Qb Qa Qa Qb Qa Qb Qa
Qc 1 x x 1
Qc x 1 1 x
Qc 0 x x x
Qc x x x x

Ja= Qc Ka =1
Figure 9.3 K-maps for simplification of expressions for each input
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Circuit Diagram for Mod-5

Preset=High

Ja:4 Jb:9 Jc:4 Qc:15

7476(1) Qa 7476(1) Qb 7476(2) Qc

CLKa:1 CLKb:6 CLKc:1

Vcc/1 Vcc/1
Ka:16 Qa:14
Kb:12 Qb:10 Kc:16 Qc:14
3 8 3

CLK

Figure9.4CircuitdiagramforMod-5counter

PROCEDURE:
1. This circuit is designed for Mod-5, i.e., the counter has to start counting from 0 till 4 and after 4 the
counter has to restart from 0 again and so on. But the student is instructed to practice all the possible
Mod values since in the examination he could be asked to design any Modcounter.
2. The 7476 is a 16 pin IC where pin No:5 is Vcc and pin No:13 isground.
3. A single 7476 provides 2 JK flip flops. Since this experiment needs 3 JK flip flops(because the
counter needs 3 bits to represent counter values 000, 001,…, 100), it is needed to use two
7476 ICs as shown in figure9.3
4. Build the transition table 9.1 using the excitation table 9.2 of JK flip flop for all J’s andK’s.
5. Using the transition table 9.1 get the simplified expression for each JK flip flop’s J and K by K-
Maps as shown in the figure 9.3. As it is shown in the figure 9.3 the excitation table is a table
that gives the required input for the obtainedoutputs.
6. From the K-Maps in figure 9.3 it is observed that inputs for first JK-flip flop are Ja=inverted Qc, Ka=1,
for the second JK-Flip flop inputs are Jb=Qa, Kb=Qa and for the third one Jc=QaQb andKc=1.
7. According to the obtained JK-Flip flops input expressions, now design the circuit diagram as
shown in figure9.4
8. Since Jc=QaQb use an AND gate to produce the value to connect pin No:4 of second 7476’s
Jc, by connecting the pin No:3 of 7400 to pinNo:4(Jc)
9. Now switch on the trainer’skit.
10. And observe the output from pin Nos: 15(Qa), 11(Qb) of first 7476 IC and pin No:15(Qc) of
second 7476IC.
Analog And Digital Electronics Lab CBCS Scheme

9.Design and implement an asynchronous counter using decade counter IC to count up from 0
to n (n<=9) and demonstrate on 7-segment display (usingIC-7447).

Components used: 7490,7447, 507 , patch chords and IC trainer’s kit

Description:
Asynchronous counter is a counter in which the clock signal is connected to the clock input of only first
stage flip flop. The clock input of the second stage flip flop is triggered by the output of the first stage flip
flop and so on. This introduces an inherent propagation delay time through a flip flop. A transition of input
clock pulse and a transition of the output of a flip flop can never occur exactly at the same time. Therefore,
the two flip flops are never simultaneously triggered, which results in asynchronous counter operation.

Figure 10.1Pin diagrams

Department of ISE, SJCIT 32

 Analog And Digital Electronics Lab CBCS Scheme

Figure 10.2 Circuit Diagram

Output : verify output on FED 507 Display.