Term End Examination - September 2013

Class NBR : 1021 Slot : A1+TA1

Course Code : EEE575
Course Title : Scripting Languages and
Verification
Time : Three Hours Max.Marks:100
Answer ALL Questions
(10 X 10 = 100 Marks)
1. a) Give the value returned by the Following TCL Commands [5]
(i) linsert {1 2} 0 new stuff
set x [list a {b c} e d]
(ii) lreplace $x 1 2 B C
(iii) lrange $x 1 3
(iv) lsearch {here is a list} l*
(v) lindex {a b {c d e} f} 2
b) Create a new TCL command called “lincrement” which takes two arguments a list and a [5]
value , list contains N number of integers , all integers should be incremented by the
value given in the argument. The default incremental value should be 1 if the value is
not mentioned in the argument.
For eg:
X= 3 4 5
lincrement {$X 10}
The answer should be 13 14 15

2. a) Give the Patterns to match URL and extract protocol, server, port, path. [7]
For eg:
set url http://www.beedub.com:80/index.html
The final answer should be like this
set match
=> http://www.beedub.com:80/index.html
set protocol
=> http
set server
=> www.beedub.com
set x
=> :80
set port
=> 80
set path
=> /index.html

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 b) Explain the use of regsub command with examples. [3]

3. a) Create a menu named STUD in the Custom Designer layout editor or Cosmos layout [5]
editor. The STUD menu should contain a button named PrintLibName. When pushing
the button the library name of the open cell should be printed in the console window.
Write TK script to get user interface.
b) Develop a tcl script that recursively searches all files and directories of the given [5]
directory and returns the list of files that contain the given word. The script must have
two command line arguments, the first is a directory name and the second is a search
string.

4. a) Write a Perl script to read a first name, last name and phone number from the console. [5]
If the user does not type at least some characters for each of these, print “Do not leave
any fields empty” otherwise print “Thank you”.
b) Write a perl script that prints the count of all devices used in the given cell of spice [5]
netlist. The report should contain the number of each model of a device and the total
value of all models of the device type. Device types are: mosfet, diode, resistor,
capacitor, bjt.

5.(a) Write a perl program that reads a list of numbers (on separate lines) until the number 999 is [10]
read, and then prints the total of all the numbers added together. (Be sure not to add in the
999!) For example, if you enter 1, 2, 3, and 999, the program should reply with the answer
of 6 (1+2+3).
OR

5.(b) Create a TCL command called “unshift” which takes a list and an element as an argument, [10]
it deletes the first element in the list and adds the new element in place of that.

6. Declare a two dimensional array mem, using the following statement: [10]
reg [M-1:0] mem [N-1:0];
Use the address to field to either read from or write onto a memory address location,
depending on the value of the ~READ or ~WR signals.
Declare data as inout and address as input. Draw the timing diagram for read and write
protocol.

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 Write verilog tasks (BFMs) for the read and write operations.
READ: Select the memory by lowering a CS signal. Latch the address, after 3ns (enable)
lower the READ signal, hold the READ signal low for 5ns (so that the read data is stable)
WRITE: Select the memory by selecting
selecting a CS signal. Signal WE must wait for 3 ns after
the address is stable, after which the WE signal is lowered (enabled). The WE signal is held
low for a time of 5ns after the data is stable.

7. In the following architecture (Fig 1), the 1-hot

hot multiplexer has a 4 bit select line encoded in [10]
1-hot.
hot. For example, if the value in the select line is ‘0010’, the second input bit is selected.
If by design error, the select line is not encoded in 1-hot,
1 hot, then the input line selected
corresponds to the
he maximum bit position which is 1. Thus if the select line is erroneously
‘0011’, the input bit selected is also the second. The 1-hot
1 hot coded select line is generated by
an internal module in the design, whose state transition diagram is shown also in the figure
(Fig 2).

Fig 1 Fig 2

a) Design a simulation strategy (verification plan) to verify error at the output of the 1-hot
1
encoder. Assume that the initial state of the encoder is ‘0010’. Compute the error
detection latency (that is the number of clock cycles required between the application of
the inputs and the detection of error in the output).
b) What type of verification methodology and test scenarios
scen are used for this design
verification?

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8. a) Consider the following property of an asynchronous handshake between Block1 and [5]
Block2. Property: The ack signal goes high on the assertion of req followed by two
positive edges of the clock signals. Choose the suitable verification topology and test
cases to verify the suitable design.

b) Write a short note on the following terms bringing out the difference between the two: [5]
(i) Formal and functional based verification
(ii) Random and Directed verification
(iii) Error based test case and performance test case.

9. a) What type of verification topology used for 4 bit counter verification and state the [5]
verification scenarios?

b) Packets dispatched can be of 3 network types: atm, ieee or Ethernet. The packets have a [5]
Boolean flag field which indicates whether the packet is “good” or “bad”. The header of
the packets is 32 bits in length. When the packet is atm, the entire header is randomly
r
generated, but when it is ieee or Ethernet the lowest 4 bits are always zero. 20% of the
time atm packets are generated, while remaining time ieee or Ethernet packets are
generated uniformly.. Model the testcase scenarios using Verilog HDL.
HDL

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10.(a) What is code coverage in verification? Difference between code coverage and functional [10]
coverage. Explain different types of code coverage and its examples.
OR
10.(b) Define the code coverage metrics and write the different coverage metrics in the following [10]
code.

module encoder83( else if(in[3] == 1'b1) begin

in,out,Gnt_valid ); out = 3'b011;
input [7:0] in; Gnt_valid = 1'b1; end
output [2:0] out; else if(in[4] == 1'b1)
output Gnt_valid; begin

assign Gnt_valid = |(in); out = 3'b100;

Gnt_valid = 1'b1;
always @(in)
End
begin
else if(in[5] == 1'b1)
if(in[0] == 1'b1)
begin
begin
out = 3'b101;
out = 3'b000; Gnt_valid = 1'b1;
Gnt_valid = 1'b1; End
end else if(in[6] == 1'b1)
else if(in[1] == 1'b1) begin

begin out = 3'b110;

Gnt_valid = 1'b1;
out = 3'b001;
End
Gnt_valid = 1'b1;
else if(in[7] == 1'b1)
end
begin
else if(in[2] == 1'b1)
out = 3'b111;
begin Gnt_valid = 1'b1;
out = 3'b010; end
Gnt_valid = 1'b1; else
end Gnt_valid = 1'b0;
end endmodule

⇔⇔⇔

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