Passive RFID Digital Core

(Course Project : EECS 495)

Bhanu Singh
 Introduction
• Radio Frequency Identification (RFID) system is low-end
wireless communication device.
• The EPC Class-I Generation-2 (C1G2) UHF protocol proposed
by EPC Global specifies the RFID air interface.
• The EPC C1G2 operates in frequency band (860 – 960Mhz).
• A Passive RFID Tag needs to draw power which is only a few
microwatts from the electromagnetic field generated by RFID
reader to work properly in the distance of several meters.
• Passive RFID Tag is a power limited device and the less power
it consumes the longer reading range it can support.
 Signaling – Reader to Tag PIE encoding

6.25us <=Tari<= 25us

Signaling
Components of a Passive RFID Tag

RF- Front End Analog Circuit

Digital Core EEPROM

Block Diagram of Tag Logical State of Tag

 RFID Tag Range Equation

• In passive backscatter systems, the range is set by the forward link (reader-to-
tag) through the radiated power available at the tag. The goal for the design of
a Gen-2 tag is to maximize read range while providing full compliance with the
protocol. The Range Equation below determines the theoretical range in which
the tag will receive adequate power levels to respond to the reader.

• Where:
• EIRP = the effective isotropic radiated power,
(≤ 4 Watts in US as Per FCC regulation)
• Panalog + Pdigital = Ptag = the power required at the tag antenna Input
• G = the tag antenna gain, and ɳ = RF to DC conversion Efficiency of Rectifier
• λ= the free-space wavelength of the RF carrier.
 Design Objective
Tags receive all of their energy from the reader's RF waveform as soon as they
get into the RF field. So the energy for the passive tags is very different from the
other active tags whose energy is supplied by batteries. Its instantaneous energy
is finite, but the total energy is infinite. So our aim is to reduce the instantaneous
power or peak current and make power evenly dissipate in whole working
period. Therefore, the low-power in this design doesn't mean low average-
power; but means low instantaneous power.

Some of the commercial tags like Alien Higgs-3 have sensitivity of -18dBm and
operating distance of 10m, which means the overall power consumption during
whole operation should not exceeded 16µW. Even with 50 % rectifier efficiency
this translates to operating power of 8 µW for the Tag. This small power budget
poses a very stringent requirement to design the Tag logic. The 8uW power
includes Power of Analog, Digital and EEPROM.
 Digital Core - Architecture

PIE Decoder Rx Fsm

symbIn
Analog Front End

Clock Control
CRC/RNG Protocol FSM Mem
clkOsc Unit
I/F

symbOut
TX Encoder Tx FSM
 Low Power Design Strategy
Power Saving through Dynamic Clock Gating using Intelligent Clock controller

Working Modules during

Different Phases of Protocol
RX-FSM TX-FSM

External Memory I/F External Memory I/F

External Memory I/F CRC-16
(Depends on command) (Depends on command)

Random Number
Protocol Unit PIE Decoder Protocol Unit CRC-16
generation

Clock Control Unit

TIME

Idle Period –
After
Waiting for signal RX Data Protocol Processing TX Data
Power-On-Reset Period No Signal

For the anti-collision scheme in the protocol, RN16 (16bits random number) must be generated differently among tags. How to generate RN16 more
random? We use a new method as follows: when a tag falls into the reader's field, it firstly turns into power-on-reset state. At the moment, it fetches
CRC-16 of EPC in the EEPROM (which is defined by the manufacturers) and puts into the RN-generator (RNG) as seed. Then RNG works until tag
detects a low level signal, which means a new command is coming from the reader. Because of the different seeds and different periods of power on-
reset state, the probabilities of same RN among tags are reduced too small, nearly to true random. It also eliminates peaking power because RNG works
at power-on reset state which most sub-modules don't work.
 Verification
. Behavioral Model of RFID_reader is used to verify RFID Tag digital core.
 Verification
• Directed Test case Verification
Clocks
 Synthesis
• Library – SAED_EDK90_CORE (90nm Standard Cell library from Synopsys)
• Frequency 10MhZ (100ns)

Library Corner Power- Power – Area Slack

Dynamic Static (um2) Positive
Saed90nm_typ 1.2V Operating 1.25uW 75uW 19486 38%
Voltage,25 C, Cycle time
Normal Vt

Saed90nm_hvt 1.2V typical, 1.17uW 15.08uW 19447 37 %

High Vt

Saed90nm_typ_tm_hvt 0.7V typical, 680 nW 2.845uW 20942 30 %

high Vt
 Annotating Switching Activity
through RTL simulation
• RTL SAIF (Switching Activity File)
• Library - Saed90nm_typ_tm_hvt
• Dynamic Power - 697 uW
• Static Power – 2.85 uW
• Area – 20748 um2
Thank you