2017 IEEE Transportation Electrification Conference and Expo, Asia-Pacific (ITEC Asia-Pacific)

High Switching Frequency Control Scheme for Dual-

Three-Phase PMSM and Simulation Analysis
Zonglong Yang1, Tongmao Niu2, Qiang Gao1
1
School of Electrical Engineering & Automation, Harbin Institute of Technology, Harbin, China
2
Daqing Oilfield PowerLift Pump Industry Co.,LTD, China
yxyzyzl@163.com, niutm@cnpc.com.cn, gq651@hit.edu.cn

Abstract- The switching frequency of power inverters among the
traditional motor drive systems are almost between 4kHz to
20kHz. The appearance of SiC or GaN devices make it is possible
to increase the switching frequency for improving the
performance of power inverter. In this paper, a high switching
frequency control scheme based on DSP and FPGA is proposed to
drive a SiC power inverter. Multiphase motor drives such as dual-
three phase permanent magnet synchronous motor have many
advantages over the traditional three-phase motor drives. The
scheme in this paper is based on the dual-three phase PMSM. The
simulation results are presented to demonstrate the performance
of this scheme.
Keynotes: high switching frequency; dual-three-phase PMSM;
vector space decomposition theory(VSD); FPGA
I. INTRODUCTION
Si IGBT is widely used in power electronic converters.
But with years of development, Si IGBT is now gradually
approaching the performance limit. Unable to meet the
challenge produced by new application such as electric vehicle,
photovoltaic, new energy, etc. Due to the low on-resistance and
high doping concentration, SiC wide bandgap semiconductor
has lower losses to achieve higher working frequency.
In traditional motor drive systems, a DSP (Digital Signal
Processing) or a MCU (Microcontroller Unit) is fast enough to
finish the control algorithm such as field oriented control (FOC)
or direct torque control (DTC) in a PWM period. But these
microprocessors will not fulfil requirements with the increase
of the PWM control accuracy. Due to the advantages such as
flexible, high speed, and high reliability, Field Programmable
Gate Arrays (FPGA) is gradually applied to the motor drive
systems to increase the controller’s performance such as
current loop bandwidth which is difficult to handle by using the
conventional microprocessor. Due to the programable
architecture, FPGA has more advantages than the ASIC chips.
FPGA can use parallel architecture to accomplish the same
functions as the traditional DSP but using less time. FPGA is
usually being used in the high performances occasions such as
large data throughput or data parallel computing. It’s obvious
that the FPGA can increase the capability in a motor control
system. There are usually two solutions when using FPGA in a
control system, the first is using single FPGA to fully replace
the traditional microprocessor, and the second is making DSP
and FPGA co-processing. There are advantages and
disadvantages between these two plans. Using single FPGA
will increase the cost and the difficulty when devising the
system but has better performance. And the other can decrease
the design complexity but will raise the volume of the control
system. It should be fully considered when designing a control
system.
Due to the development of power electronics, three-phase
AC drive systems have replaced the DC drive systems to be
widely used in the industry applications. But nowadays multi-
phase motors are gradually drawing people’s interest on
account of the high-power capacity which is difficult for three-
phase drive systems due to the limitation of power devices.
Multi-phase motors have many advantages. By raising phases,
multi-phase motors can decrease supply voltage without any
power losses which will reduce the voltage rating of power
devices and will be useful in the occasions where the voltage is
limited. Multi-phase motors such as dual-three phase PMSM
also have the lower torque pulsation than the conventional ones.
Multi-phase motors can enhance the reliability of the drive
system. When one or more phases are isolated from the inverter,
the system will still work while the conventional three-phrase
PMSM is out of order. Owing to this property, multi-phase
motors are often to be used in electric vehicles, warships,
aerospace, etc. Dual-three phase PMSM is a kind of typical
multi-phase motors which has two windings shifted between 30
degrees with each other. The winding diagram of dual-three
phase PMSM is shown as Fig.1.
There are mainly two ways in modeling the dual-three
phase PMSM which are double d-q approach and vector space
decomposition theory (VSD). Double d-q method makes dual-
B
Y X
A
C
Z
Fig. 1. The winding diagram for dual-three phase PMSM

978-1-5386-2894-2/17/$31.00 ©2017 IEEE

978-1-5386-2894-2/17/$31.00 ©2017 IEEE

 2017 IEEE Transportation Electrification Conference and Expo, Asia-Pacific (ITEC Asia-Pacific)

According to the vector space decomposition (VSD) method,

+
the voltage and the current can be decomposed into the three
Udc
subspaces. The transform matrix is written as follows:
A X B Y C Z

1 -1/2 -1/2 √3/2 -√3/2 0

-
0 √3/2 -√3/2 1/2 1/2 -1
1 1 -1/2 -1/2 -√3/2 √3/2 0
T= (4)
3 0 -√3/2 √3/2 1/2 1/2 -1
1 1 1 0 0 0
A X B Y C Z 0 0 0 1 1 1
By multiplying the matrix T, stator voltage and current
can be decoupled to the subspace. When neglecting the
Fig. 2. Six-Phase Inverter Connecting to the dual-three phase PMSM component of o1-o2, we can get:
three phase PMSM equivalent to two conventional three-phase ψα
PMSM. Similar to control two motors at the same time. Vector uα Rs 0 0 0 iα
uβ 0 Rs 0 0 iβ ψ -ψβ
space decomposition theory (VSD) places the voltage and the (5)
current vector into three independent orthogonal sub-spaces uz1 = 0 0 Rs 0 iz1
+
ψz1
+ωe ψ
α
which are α-β, z1-z2 and o1-o2. The former is the current uz2 0 0 0 Rs iz2 ψz2
space which produce the torque, and the middle will generate
ψα iα cosθ
the harmonic current. The latter means the zero-sequence
subspace. VSD is four-dimensional control method therefore ψβ M 0 iβ sinθ
+ (6)
it’s more flexible than the double d-q method. The motor model ψz1 = 0 N iz1 0
ψfd
based on the α-β subspace has the same form as the three- ψz2 iz2 0
phase PMSM. So, method for conventional ones such as
sensorless control schemes will be suitable for the dual-three Lm cos2 θ+Ln sin2 θ Lm sinθcosθ-Ln sinθcosθ
M= (7)
phase PMSM. Dual-three phase PMSM usually supplied by the Lm sinθcosθ-Ln sinθcosθ Lm sin2 θ+Ln cos2 θ
six-phase inverter shown as Fig.2. Laal 0
N= (8)
II. MOTOR MODEL 0 Laal
Dual-three phase PMSM is a high dimension system with Where Lm =3Laad +Laal , Ln =3Laaq +Laal . Laad and Laaq
strong coupling. Referring to the conventional ones we can are the main inductance of d and q axis, Laal is the leakage
deduce the equation. To simplify the system, some assumptions inductance.
should be made as follows:
cosθ sinθ 0 0
1. Magnet saturation, eddy current, skin effect and hysteresis -sinθ cosθ 0 0
Tr/s = (9)
are negligible. 0 0 1 0
2. Linkage established by the magnet and the windings are 0 0 0 1
sinusoidal distributed. To create the motor model, (1) can be transformed into the
state equation. The equations established in static coordinate
3. The surface of the stator and rotor is smooth, without the
can be converted into the two-phase rotating coordinate by the
influence of slotting.
Park transformation, the transform matrix is given at (9).
4. The parameters will not change with the working of the
motor. III．CONTROL SCHEME
Similar to the three-phase PMSM, the equation can be Field oriented control makes the three-phase system
written as follows: equivalent to two-phase system. After the transformation
between the static and the rotate coordinate system, the stator
us =Rs is +pψs (1)
current can be decomposed into two components which one for
ψs =Ls is +Γψfd (2) exciting the magnet field and another for produce torque. Thus,
the PMSM has the similar control performance as the DC motor.
2π 2π In this paper, the control scheme for the dual-three phase
Γ=[cosθ cos(θ- ) cos(θ+ )
3 3 PMSM is based on the FOC.
π 5π π A. Overall Scheme
cos(θ- ) cos(θ- ) cos(θ+ )]T (3)
6 6 2 Due to high switching frequency, a single microprocessor
Where us is the stator voltage, is is the stator current, cannot finish the control procedure in one period. To accelerate
Rs and Ls are the resistance and inductance of the armature the calculation, the control algorithm calculation part and the
winding. ψs means the linkage of each phase, ψfd is the SVPWM generation part should be separated. During each
linkage established by the magnet, θ is the angle of the rotor. period of the SVPWM, DSP will first read the AD results and
 2017 IEEE Transportation Electrification Conference and Expo, Asia-Pacific (ITEC Asia-Pacific)

DSP FPGA
βk Z 2k
id* = 0 + ud uα U dc
PI d d-q
− iABC
ωm* + + uq
α -β
uβ
Six-
v4 75°
PI Speed PI q
− SVPWM Phase Motor
− ωm
i =0 +
*
uZ1 Inverter
Z1
PI Z 1 45° 135°
*
iZ2 =0 − iXYZ v3
+ uZ2 v1 v3
PI Z 2 15°
− ωm αk Z1k
id
v4 v2
iq Tr / s VSD v2
iZ1
iZ2
v1
Fig. 3. The overall scheme for the drive system
then calculate the desire stator voltage which will be applied to Fig. 5. The vector diagram for sector k
the winding. Then according to the desire stator voltage, FPGA π
V* cos(φ+ )
will generate the SVPWM pulses to drive the six-phase inverter. Ta = 3 (13)
Based on the VSD theory, the double closed-loop control π
|V|max cos( )
system for rotor speed and stator current is shown as Fig.3. 3

B. Dual-Three Phase SVPWM Algorithm V* sin(φ)

Tb = π (14)
The six-phase inverter was comprised by six bridge arms. |V|max cos( )
3
Each arm exists two states, thus there exists in 64 states in total.
With the reference of the conventional three-phase inverter, the Where |V|max is the amplitude of the largest vector
voltage vector in each subspace can be written as follows: which means the edge vectors. V* means the amplitude of
the target vector. Φ represents the angle between the target
1 2π -2π π 5π 3π
vector and the first edge of the specific sector. The max
= Udc (SA +SB ej 3 +SC ej 3 +SX ej6 +SX ej 6 +SX ej 2 ) (10) π
3 amplitude of the target vector is Vmax cos( ) by using two-
12
1 2π 2π 5π π 3π vector SVPWM method. But this scheme can’t exert
vZ = Udc (SA +SB e-j 3 +SC ej 3 +SX ej 6 +SY ej6 +SZ ej 2 ) (11)
3 characterizes of multi-dimension. By choosing the four
1 π π π adjacent largest vectors around the target vector, we can get
v0 = Udc (SA +SB +SC +SX ej2 +SY ej2 +SZ ej2 ) (12) four vector SVPWM scheme. This approach is fully considered
3 the vectors both in the α-β and z1-z2 subspace. By selecting
If the switch in the upper arm of phase A is on, then we the angle bisector and its vertical line of each sector, the
define SA =1, instead SA =0. Switch state [(SA SB SC ), (SX SY computation can be simplified. The voltage vector for sector k
SZ )] can be represented by two octal number. According to is shown as Fig.5.
these formula, the vector diagram in the α-β subspace is
Similar to the two-vector approach. Decomposed each
shown as Fig.4. The subspace was divided into twelve sectors
vector into the orthogonal axes, and basing on the volt-second
by the voltage vector who with the maximum amplitude.
balance principle, the duration of each vector is given as
Naturally, the voltage vector in each sector can be composed
follows:
by the two edge vectors of this sector. Similar to the
conventional three-phase inverter, the on-durations of edge u*αk
vectors can be deduced under volt-second balance principle. T1 -3+2√3 -√3 -3-2√3 √3
*
T2 Ts 3-√3 -3+√3 3+√3 -3-√3 uβk (15)
=
v26 Sector 4 v T3 2Udc 3-√3 3-√3 3+√3 3+√3 u*z1k
66
v62 v24 T4
v22 v76 -3+2√3 √3 -3-2√3 -√3 u*z2k
v36 v20 v06 v
v27 v67 v46 64 According to [10], the max amplitude of the target vector
v60 U
v 34

v72 by using four-vector approach is dc . In the cases which the

v42

v32v23 v02 v6 v74 √3

v16
3 25 v04
v65 v44 amplitude of the vector is lower than 0.577Udc, we can use the
v

Sector 7 v37
v v 56 v47 Sector four-vector approach, and if the amplitude is between
v 21 1
30 v
v33v12 v61 40 (0.577-0.622)Udc , two-vector approach is a good choice.
v73 52 v05 v
v75 54 v45
v

v03 C. Algorithm Implementation With FPGA

v 14
v 43
v35

v31 v17 v57 The algorithm above can be implemented by using FPGA.
v13 v10 v71 v50 v41
v01 v55 Once the FPGA received the voltage instructions form DSP, it
v v will generate the PWM pulses to drive the six-phase inverter.
v1153 v15
51
Sector 10 Thus, the response time of current loop is reduced. Making it is
possible to increase the PWM frequency for improving the
Fig. 4. Vector diagram for six-phase inverter
control accuracy. The general structure is shown as follows:
 2017 IEEE Transportation Electrification Conference and Expo, Asia-Pacific (ITEC Asia-Pacific)

FPGA SL =P1 +P2 +P3 +4P4 +8P5 (20)

Time Sequence clk
Generator The correspondence between the sector label and the
specific sector number is given as follows:
Sector
Judgment
Table 1
uα Sector 1 2 3 4 5 6
SVPWM
uβ SVPWM Compare Dead Signals
DSP zα RAM Data Format
Calculation Module
ROM
Zone SL 7,15 14 13 8,12 9 10
Converter
zβ Sector 7 8 9 10 11 12
SL 3,11 2 1 0,4 5 6
AD Input
The core part of the SVPWM pulse generator is the time
Fig. 6. The general structure for the algorithm Implementation
calculation module. The time calculation can be divided into
two steps. First, the target vector should be decomposed into
clk the axes which based on the bisector of the specific sector and
En its vertical line. That means to get u*αk , u*βk , u*z1k and u*z2k .
Data Convertion According to the analysis. The formula is given as follows:
Sector Judgement
kπ kπ
SVPWM Calculation cos sin 0 0
Signal 6 6
Generation u*αk kπ kπ uα
u*βk sin cos 0 0 uβ
= 6 6 (21)
Fig. 7. Signals produced by the sequence generator uz1
u*z1k 5kπ kπ
Each module in the Fig.6 is a IP core, and it can be used 0 0 cos sin uz2
u*z2k 6 6
in another project. Thus, the development time can be reduced. 5kπ 5kπ
The communication between DSP and FPGA in this design is 0 0 -sin cos
achieved by the XINTF peripheral of DSP. FPGA implements 6 6
all the modules internally. During every PWM period, DSP Where the k means the sector number. Due to k can
delivers the data into the RAM and then trigger the time only take discrete values, the trigonometrical values can be
sequence generator to produce the sequence pulse signals to calculated in advance so as to reduce computation load. The
enable the other modules in FPGA. The signals which produced second step is to calculate the duration of the four vectors.
by the sequence generator is simplified as Fig.7. According to (15), the time can be determined. The process
time for the zero vector can be gained by using PWM period
Single precision floating-point type is the common data minus the sum of the durations of the four vectors. If the sum
type which used in floating-point DSP such as TMS320F28335. of the durations exceeds the PWM period, the duration of each
The calculation speed for floating point arithmetic is usually vector needs to be scale down. The compare module calculates
slower than the fixed-point. In order to accelerate the the switching time of each vector according to the durations.
computing, and make full use of the FPGA’s ability of parallel Assume that the clock frequency is 100MHz, and the PWM
computation, the floating-point number can be converted into frequency is 100kHz, and then the time resolution is 10ns.
fixed-point one. By choosing a suitable number of binary bit to The switching times is shown as Fig.8.
denote the fractional part, we can make the error within the
given range. During every PWM period, the counter counts a thousand
times as a timer, and the voltage vector is switched when the
The α-β subspace is divided into twelve sectors by the timer exceeds the switching time. The switch states can be
twelve largest vectors. When calculating the duration of the stored in the ROM which implemented by the FPGA. When
four adjacent vectors around the target vector during a the time counter exceeds the next switching time, then the
SVPWM period, the sector which the target is in should be address is added by one so as to switch the next voltage vector.
known. Thus, we should judge the sector before the time In the real system, the turn-on and turn-off of the switch is not
calculation. Define the components of the voltage vector on
axis α and β as uα and uβ . And define several auxiliary
v0
variables as follows: v3
ur1 = 2-√3 | |- (16) v4
v0
ur2= | |- (17)
v1
ur3 = 2+√3 | |- (18) v2
ur4 =uα , ur5 =uβ (19) v0

If ur1 ≥0, then define P1 =1, else define P1 =0. Similarly, T0 T0 T0 t

T2 T1 T4 T3
the definition for P2 , P3 , P4 and P5 is the same as P1 . By 4 2 4
using these five variables, the label of each sector is defined as
follows: Fig. 8. The switching times
 2017 IEEE Transportation Electrification Conference and Expo, Asia-Pacific (ITEC Asia-Pacific)

Clk 16
Sector 14

Z 12
Z 10

Sector Label
Y 8
Y
X 6
X 4
C 2
C
B 0
B
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08
A
A Time /s

Fig. 9. The timing simulation result Fig. 11. The result of the sector judgement module
instantaneous so the dead zone should be added to the PWM Filtered output voltage
pulses to avoid inverter-bridge short. The dead zone module X A Z C Y B
400
adds the dead time to the PWM signals. When the rising edge
of the signal is detected, a counter begins to work to produce a 350
delay time which is changeable by configuring the count value. 300
The output of the dead zone module can be transmitted to the 250
drive module in the bridge arm by the optocoupler.

Voltage /V
200

IV .SIMULATION 150
100
A. Timing Simulation
50
The functions of the program can be verified by the timing
0
simulation. ModelSim is a powerful tool for timing analysis.
The input signals can be simulated by writing test bench files. 0.03
0 0.005 0.01 0.015 0.02 0.025
The parameters are set as follows: clk=50MHz . uα =-1.76 , Time /s
u =2.42, Zα =Zβ =0. The dead-time is 200ns. The number of
sector is 5 by theoretical calculation. The timing simulation Fig. 12. The filtered output voltage
result is shown as Fig.9.
It can be seen through the figure that the simulation results
are consistent with the theoretical analysis. Through the test,
the program can meet the requirements.
B. MATLAB Simulation
The six-phase inverter can be modeled in the MATLAB
Simulink. The modules can be built by writing S-function or
using the built-in modules. And among the all modules, the
sector judgement module is shown as Fig.10.The uα and u
are the two voltage signals with a difference of 90 degrees. The
simulation time is 0.08s. And the result of the sector judgement Fig. 13. The FFT analysis of the phase voltage
module is the label of sectors, we can use MATLAB functions The amplitude of the modulation wave is 150V , the
to match the result to the real sector number. The result is given frequency is 50Hz. The DC-link voltage is 500V. The filtered
at Fig.11. output voltage is shown Fig.12.
1 |u|
f(u)
Do Fast Fourier analysis to the phase voltage, and the
Ualpha
Fcn result is shown as Fig.13. We can see that the THD of the phase
u(1)-u(2)
voltage is 0.24%.
2 |u|
Ubeta Fcn1
It can be seen from the above that the algorithm will meet
f(u) the requirement. Basing on the electrical and mechanical
Fcn2 equations deduced before, the dual-three phase PMSM can be
4 modeled in the MATLAB Simulink. By using the six-phase
1
Out1
PWM generator module, the completely double-closed loop
control system can be implemented. The simulation parameters
8

Add
for the dual-three phase permanent magnet synchronize
machine are given as follows:
Fig. 10. The sector judgement module
Rs =3.68Ω,Lm =0.0258H,Ln =0.0501H,Laal =0.028H,P=2,
 2017 IEEE Transportation Electrification Conference and Expo, Asia-Pacific (ITEC Asia-Pacific)

ωm From the result, we can see that the rotor speed rise
rapidly to the given value, when the load torque changes, the
50 speed varies little. When there is no load, the stator currents are
almost zero.
40
Speed /rad/s

30
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