Gift University Gujranwala Electrical Engineering

Introduction to DSCH Software and

Implementation of All Gates at Switch
Level

Lab Manual 12

Name Reg. No. Lab Performance/10 Viva/5 Total/25

Task Marks/10

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DIGITAL SYSTEM DESIGN LAB EVALUATION RUBRIC

Lab No. 12: Introduction to DSCH Software and Psychomotor skill level: P3
implementation of all gates at switch level

90%-100% - Excellent 70%-90% - 40%-70% – 0%-40% Needs

Good Satisfactory Improvement
Simulation Results/ Correctly performed Correctly Inaccuracies in Most tasks performed
Experimental Set up simulation. Complete, performed Simulation. incorrectly on
& Results* (12) accurate, neat and simulation. Complete circuit set software. Improper
professional circuit set Accurate up with partial circuit .Set up with no
verification of its or minimal results.
up with verification of construction of
functionality
all the necessary circuit with some
results. minute errors in
results verification.

Safety, Equipment & Full attention to relevant Required attention Some attention and Did Not follow
Material (1) safety procedures & and returned all had to be reminded directions and safety
directions. materials to clean up area and precautions. Had to be
Returned all materials appropriately. equipment; and to asked again and again
appropriately and return materials. to return materials
responsibly.
Lab Report (10) Professional and Report include all Report data is Inadequate and non-
accurate representation required accurate accurate but professional lab report
of lab experiment in data with some presented in non- with inaccurate results.
terms of problem minor inadequacies professional manner Report did not include
statement, circuit design, in presentation. along with some the required analysis
observations, results, errors in analysis and and graphs along with
analysis and conclusion. conclusion wrong or no
conclusion.
VIVA (5) The related questions Student partially able Student partially able Do not know about
are answered fully. to answer to to answer to working of circuit.
question. Aware question. Not Aware Unable to answer the
about the working of about the working of questions.
circuit. circuit.
<------Total points earned = Lab Performance Grade----->

*RESULTS REQUIRED Level

Reproduce circuit on software for given lab task. (6) P3
Show the code of your circuit. (6) P2

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Objectives
 To learn about the DSCH software
 To learn implementation of switch level logic
 To get to know about the usage of DSCH software
 To design switch level logic using DSCH software

Introduction to DSCH
The DSCH program is a logic editor and simulator. DSCH is used to validate the architecture of the
logic circuit before the microelectronics design is started. DSCH provides a user-friendly environment
for hierarchical logic design, and fast simulation with delay analysis, which allows the design and
validation of complex logic structures. DSCH also features the symbols, models and assembly support
for 8051 and PIC16F84 controllers. Designers can create logic circuits for interfacing with these
controllers and verify software programs using DSCH.DSCH3 is the companion software for logic
design. Based on primitives, a hierarchical circuit is built and simulated. Interactive symbols are used
to friendly simulation, which includes delay and power consumption evaluation.

Software Description
 User-friendly environment for rapid design of logic circuits
 Supports hierarchical logic design
 Added a tool on fault analysis at the gate level of digital
 (Faults: Stuck-at-1, stuck-at-0.)
The technique allows injection of single stuck-at fault at the nodes of the circuit.
 Improved interface between DSCH and Winspice.
 Handles both conventional pattern-based logic simulation and intuitive on screen
mouse- driven simulation
 Built-in extractor which generates a SPICE net list from the schematic diagram
(Compatible with PSPICETM and WinSpiceTM)
 Generates a VERILOG description of the schematic for layout conversion
 Immediate access to symbol properties (Delay, fan-out)
 Model and assembly support for 8051 and PIC 16F84 microcontrollers
 Sub-micron, deep-submicron, nanoscale technology support
 Supported by huge symbol library

Switch level Gate

The switch level of modeling provides a level of abstraction between the logic and analog-transistor
levels of abstraction, describing the interconnection of transmission gates, which are abstractions of
individual mos and cmos transistors. The switch level transistors are modeled as being either on or
off, conducting or not conducting. Further, the values carried by the interconnections are abstracted
from the whole range of analog voltages or currents to a small number of discrete values. These values
are referred to as signal strengths.

Features
 Designs at the logic level of abstraction
 Describe a digital circuit in terms of primitive logic functions such as or, and nor, etc.
 Allow for the nets interconnecting the logic functions to carry 0, 1, x and z values
 At the analog-transistor level of modeling, we use an electronic model of the circuit
elements and allow for analog values of voltages or currents to represent logic values on the
interconnections.
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The nmos and pmos Switches

 To instantiate switch elements:

switch_name [instance_name] (output, input, control);

 The instance_name is optional

CMOS Switch
 Is designed to propagate both 0 and 1 well
 Nmos is only able to propagate 0 well
 Pmos is only able to propagate 1 well
 To instantiate CMOS switches :
cmos [instance name] (output, data, ncontrol, pcontrol);
 The instance name is optional
 Exactly equivalent to the following :
nmos (out, data, ncontrol);
pmos (out, data, pcontrol);

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DESIGN AND PROGRAMMING

Example : The CMOS Inverter module

my_not (input x, output f);

// internal declaration

supply1 vdd;

supply0 gnd;

// NOT gate body

pmos p1 (f, vdd, x);

nmos n1 (f, gnd, x);

endmodule

Observation (1 Marks)
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Lab Tasks
 Design the circuit for all primitive logic gates using DSCH Software and also write down their
codes.
[Marks: 6+6=12]

 Make a lab report with code and design of your above lab tasks and results of simulation.
[Marks: 6]

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Review Questions

1. What is difference between switch level and gate level modelling?

(1 Marks)

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2. What is difference between n-mos and p-mos? (1 Marks)

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3. What is CMOS? (1 Marks)

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