Energy Harvesting From Piezoelectric Materials

Fully Integrated in Footwear

In the last few years, there has been an increasing demand for low-power and
portable-energy sources due to the development and mass consumption of portable
electronic devices .Furthermore, the portable-energy sources must be associated with
environmental issues and imposed regulations. These demandssupport research in
the areas of portable-energy generation methods.

In this scope, piezoelectric materials become a strong candidate for energy

generation and storage in future applications .This paper describes the use of
piezoelectric polymers in order toharvest energy from people walking and the
fabrication of a shoe capable of generating and accumulating the energy. In this
scope, electroactive β-polyvinylidene fluoride used as energy harvesting element
was introduced into a bicolor sole prepared by injection, together with the
electronics needed to increase energy transfer and storage efficiency. An
electrostatic generator was also includedin order to increase energy harvesting.

2. INTRODUCTION TO ATMEL

A single chip microcontroller is obtained by integrating all the components of

a microcontroller in one IC package. Hence apart from CPU such a single chip
microcontroller will therefore contain its own clock generator and some amount of
ROM or EPROM, RAM and I/O ports on the same chip. It may also have other
features like timer/counter, USART, PWM, A/D etc., on the chip.

2.1. FEATURES:
• Compatible with MCS®-51 Products
• 8K Bytes of In-System Programmable (ISP) FlashMemory–
Endurance: 10,000 Write/Erase Cycles
• 4.0V to 5.5V Operating Range
• Fully Static Operation: 0 Hz to 33 MHz
• Three-level Program Memory Lock
• 256 x 8-bit Internal RAM
• 32 Programmable I/O Lines
 • Three 16-bit Timer/Counters
• Eight Interrupt Sources
• Full Duplex UART Serial Channel
• Low-power Idle and Power-down Modes
• Dual Data Pointer
• Power-off Flag
• Fast Programming Time

2.2.DESCRIPTION

The AT89S52 is a low-power, high-performance CMOS 8-bit microcontroller

with 8K bytes of in-system programmable Flash memory. The device is
manufactured using Atmel’s high-density nonvolatile memory technology and is
compatible with the industry-standard 80C51 instruction set and pinout. The on-
chip Flash allows the program memory to be reprogrammed in-system or by a
conventional nonvolatile memory pro- grammer. By combining a versatile 8-bit
CPU with in-system programmable Flash on a monolithic chip, the Atmel AT89S52
is a powerful microcontroller which provides a highly-flexible and cost-effective
solution to many embedded control applications.

The AT89S52 provides the following standard features: 8K bytes of Flash,

256 bytes of RAM, 32 I/O lines, Watchdog timer, two data pointers, three 16-bit
timer/counters, a six-vector two-level interrupt architecture, a full duplex serial
port, on-chip oscillator, and clock circuitry. In addition, the AT89S52 is designed
with static logic for operation down to zero frequency and supports two software
selectable power saving modes. The Idle Mode stops the CPU while allowing the
RAM, timer/counters, serial port, and interrupt system to continue functioning. The
Power-down mode saves the RAM con- tents but freezes the oscillator, disabling all
other chip functions until the next interrupt or hardware reset.
2.2.1.PIN DIAGRAM:

Fig: Pin diagram of AT89S52

2.2.2.PIN DESCRIPTION:
VCC - Supply voltage
GND – Ground

PORT 0:
Port 0 is an 8-bit open-drain bi-directional I/O port. As an output port, each
pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be
used as high impedance inputs. Port 0 may also be configured to be the multiplexed
low order address/data bus during accesses to external program and data memory.
In this mode P0 has internal
Pull-ups. Port 0 also receives the code bytes during Flash programming, and outputs
the code bytes during program verification. External pull-ups are required during
program verification.

PORT 1:
Port 1 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 1
output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins
they are pulled high by the internal pull-ups and can be used as inputs. As inputs,
Port 1 pins that are externally being pulled low will source current (IIL) because of
the internal pull-ups Port 1 also receives the low-order address bytes during Flash
programming and verification.

Port Pin Alternate Functions

P1.0 T2 (external count input to Timer/Counter 2), clock-
P1.1 out (Timer/Counter 2 capture/reload trigger and
T2EX
P1.5 direction
MOSI (usedcontrol)
for In-System Programming)

P1.6 MISO (used for In-System Programming)

 P1.7 SCK (used for In-System Programming)

PORT 2:
Port 2 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 2
output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins
they are pulled high by the internal pull-ups and can be used as inputs. As inputs,
Port 2 pins that are externally being pulled low will source current (IIL) because of
the internal pull-ups.
Port 2 emits the high-order address byte during fetches from external
program memory and during accesses to external data memory that uses 16-bit
addresses (MOVX @ DPTR). In this application, it uses strong internal pull-ups when
emitting 1s. During accesses to external data memory that uses 8-bit addresses
(MOVX @ RI); Port 2 emits the contents of the P2 Special Function Register.
Port 2 also receives the high-order address bits and some control signals
during Flash programming and verification.

PORT 3:
Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 3
output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins,
they are pulled high by the inter- nal pull-ups and can be used as inputs. As inputs,
Port 3 pins that are externally being pulled low will source current (IIL) because of

the pull-ups.

Port 3 receives some control signals for Flash programming

and verification.
Port 3 also serves the functions of various special features of the AT89S52,
as shown in the fol- lowing table.

Port Pin Alternate Functions

2.2.3.PORT P3.0 RXD (Serial input port1)

PIN P3.1 TXD (Serial output port)
DESCRIPTION: P3.2 INT0 (External interrupt0)

P3.3 INT1 (External interrupt1)

P3.4 T0 (Timer0 external input)

P3.5 T1 (Timer1 external input)
P3.6 WR(External data memory write )
P3.7 RD(External data memory read )
Port Pin Description

RST:
Reset input. A high on this pin for two machine cycles while the oscillator is
running resets the device.

ALE/PROG:
Address Latch Enable output pulse for latching the low byte of the address
during accesses to external memory. This pin is also the program pulse input
(PROG) during Flash programming.
In normal operation ALE is emitted at a constant rate of 1/6 the oscillator
frequency, and may be used for external timing or clocking purposes. Note,
however, that one ALE pulse is skipped during each access to external Data
Memory.
If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH.
With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise,
the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the
microcontroller is in external execution mode.

PSEN:
Program Store Enable is the read strobe to external program memory. When
the AT89C51 is executing code from external program memory, PSEN is activated
twice each machine cycle, except that two PSEN activations are skipped during
each access to external data memory.
EA/VPP:
External Access Enable (EA) must be strapped to GND in order to enable the
device to fetch code from external program memory locations starting at 0000H up
to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally
latched on reset.
EA should be strapped to VCC for internal program executions. This pin also
receives the 12-volt programming enable voltage (VPP) during Flash programming,
for parts that require 12-volt VPP.

XTAL1:
Input to the inverting oscillator amplifier and input to the internal clock
operating circuit.

XTAL2:
Output from the inverting oscillator amplifier.

2.3. ARCHITECTURE OF ATMEL (AT89S52)

The AT89S52 provides the following standard features: 8K bytes of Flash, 256
bytes of RAM, 32 I/O lines, Watchdog timer, two data pointers, three 16-bit
timer/counters, a six-vector two-level interrupt architecture, a full duplex serial port,
on-chip oscillator, and clock circuitry.
In addition, the AT89S52 is designed with static logic for operation down to
zero frequency and supports two software selectable power saving modes. The Idle
Mode stops the CPU while allowing the RAM, timer/counters, serial port, and
interrupt system to continue functioning.
The Power-down mode saves the RAM con-tents but freezes the oscillator,
disabling all other chip functions until the next interrupt or hardware reset.
2.3.1. BLOCK DIAGRAM OF AT89S52
2.4. REGISTERS:

2.4.1.Special Function Registers:

 A map of the on-chip memory area called the Special Function Register (SFR).
Note that not all of the addresses are occupied, and unoccupied addresses may not
be implemented on the chip. Read accesses to these addresses will in general
return random data, and write accesses will have an indeterminate effect. User
software should not write 1s to these unlisted locations, since they may be used in
future products to invoke new features. In that case, the reset or inactive values of
the new bits will always be 0.

2.4.2. Timer 2 Registers:

Control and status bits are contained in registers T2CON and T2MOD for
Timer 2. The register pair (RCAP2H, RCAP2L) is the Capture/Reload registers for
Timer 2 in 16-bit capture mode or 16-bit auto-reload mode.

2.4.3. Interrupt Registers:

The individual interrupt enable bits are in the IE register. Two priorities can
be set for each of the six interrupt sources in the IP register.

Dual Data Pointer Registers:

To facilitate accessing both internal and external data memory, two banks
of 16-bit Data Pointer Registers are provided: DP0 at SFR address locations 82H-
83H and DP1 at 84H-85H. Bit DPS = 0 in SFR AUXR1 selects DP0 and DPS = 1
selects DP1. The user should ALWAYS initialize the DPS bit to the appropriate
value before accessing the respective Data Pointer Register.

Power Off Flag:

The Power Off Flag (POF) is located at bit 4 (PCON.4) in the PCON SFR. POF is
set to “1” during power up. It can be set and rest under software control and is
not affected by reset.

2.5 Memory Organization

MCS-51 devices have a separate address space for Program and Data
Memory. Up to 64bytes each of external Program and Data Memory can be
addressed.

2.5.1 Program Memory

If the EA pin is connected to GND, all program fetches are directed to
external memory.
On the AT89S52, if EA is connected to VCC, program fetches to addresses

0000H through1FFFH are directed to internal memory and fetches to addresses

2000H through FFFFH are to external memory.

2.4.4. Data Memory:

The AT89C52 implements 256 bytes of on-chip RAM. The upper 128 bytes
occupy a parallel address space to the Special Function Registers. That means the
upper 128bytes have the same addresses as the SFR space but are physically
separate from SFR space. When an instruction accesses an internal location above
address 7FH, the address mode used in the instruction specifies whether the CPU
accesses the upper 128 bytes of RAM or the SFR space. Instructions that use direct
addressing access SFR space.

For example, the following direct addressing instruction accesses the SFR at
location 0A0H (which is P2).
MOV 0A0H, #data
Instructions that use indirect addressing access the upper 128 bytes of RAM.
For example, the following indirect addressing instruction, where R0 contains 0A0H,
accesses the data byte at address 0A0H, rather than P2 (whose address is 0A0H).
MOV @R0, #data
Note that stack operations are examples of indirect addressing, so the upper
128 bytes of data RAM are available as stack space.

2.4.5. Timer 0 and 1:

Timer 0 and Timer 1 in the AT89S52 operate the same way as Timer 0 and
Timer 1 in the AT89C51 and AT89C52.

2.4.6. Timer 2 :
 In the Counter function, the register is incremented in response to a 1-to-0
transition at its corre- sponding external input pin, T2. In this function, the
external input is sampled during S5P2 of every machine cycle. When the samples
show a high in one cycle and a low in the next cycle, the count is incremented.
The new count value appears in the register during S3P1 of the cycle following the
one in which the transition was detected. Since two machine cycles (24 oscillator
periods) are required to recognize a 1-to-0 transition, the maximum count rate is
1/24 of the oscillator frequency. To ensure that a given level is sampled at least
once before it changes, the level should be held for at least one full machine cycle.

2.5. CAPTURE MODE:

In the capture mode, two options are selected by bit EXEN2 in T2CON. If
EXEN2 = 0, Timer 2 is a 16-bit timer or counter which upon overflow sets bit TF2 in
T2CON. This bit can then be used to generate an interrupt.
If EXEN2 = 1, Timer 2 performs the same operation, but a 1-to-0 transition at
external input T2EX also causes the current value in TH2 and TL2 to be captured
into RCAP2H and RCAP2L, respectively.
In addition, the transition at T2EX causes bit EXF2 in T2CON to be set. The
EXF2 bit, like TF2, can generate an interrupt.

TIME IN CAPTURE MODE:

 Fig: Time in capture mode

Timer 2 automatically counting up when DCEN = 0. In this mode, two options

are selected by bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2 counts up to 0FFFFH and
then sets the TF2 bit upon overflow. The overflow also causes the timer registers to
be reloaded with the 16-bit value in RCAP2H and RCAP2L. The values in Timer in
Capture ModeRCAP2H and RCAP2L are preset by software. If EXEN2 = 1, a 16-bit
reload can be triggered either by an overflow or by a 1-to-0 transition at external
input T2EX.
This transition also sets the EXF2 bit. Both the TF2 and EXF2 bits can
generate an interrupt if enabled. Setting the DCEN bit enables Timer 2 to count up
or down, as shown in Figure.
In this mode, the T2EX pin controls the direction of the count. Logic 1 at
T2EX makes Timer 2 count up. The timer will overflow at 0FFFFH and set the TF2
bit. This overflow also causes the 16-bit value in RCAP2H and RCAP2L to be
reloaded into the timer registers, TH2 and TL2, respectively. Logic 0 at T2EX makes
Timer 2 count down. The timer underflows when TH2 and TL2 equal the values
stored in RCAP2H and RCAP2L. The underflow sets the TF2 bit and causes 0FFFFH to
be reloaded into the timer registers. The EXF2 bit toggles whenever Timer 2
overflows or underflows and can be used as a 17th bit of resolution. In this
operating mode, EXF2 does not flag an interrupt.

2.6. INTERRUPTS:
The AT89C52 has a total of six interrupt vectors: two external interrupts
(INT0 and INT1), three timer interrupts (Timers 0, 1, and 2), and the serial port
interrupt. These interrupts are all shown in Figure 6. Each of these interrupt sources
can be individually enabled or disabled by setting or clearing a bit in Special
Function Register IE. IE also contains a global disable bit, EA, which disables all
interrupts at once. Note that Table shows that bit position IE.6 is unimplemented. In
the AT89C51, bit position IE.5 is also unimplemented. User software should not
write 1s to these bit positions, since they may be used in future AT89 products.
Timer 2 interrupt is generated by the logical OR of bits TF2 and EXF2 in register
T2CON.
 In fact, the service routine may have to determine whether it was TF2 or
EXF2 that generated the interrupt, and that bit will have to be cleared in software.
The Timer 0 and Timer 1 flags, TF0 and TF1, are set at S5P2 of the cycle in which
the timers overflow.

2.7.Oscillator Characteristics:

Fig: Oscillator Connection

XTAL1 and XTAL2 are the input and output, respectively, of an inverting
amplifier which can be configured for use as an on-chip oscillator, as shown in
Figure 1. Either quartz crystal or ceramic resonator may be used. To drive the
device from an external clock source, XTAL2 should be left unconnected while
XTAL1 is driven as shown in Fig 2.2 There are no requirements on the duty cycle of
the external clock signal, since the input to the internal clocking circuitry is through
a divide-by-two flip-flop, but minimum and maximum voltage high and low time
specifications must be observed.

2.7.1. Idle Mode:

In idle mode, the CPU puts itself to sleep while all the on chip peripherals
remain active. The mode is invoked by software. The content of the on-chip RAM
and the entire special functions registers remain unchanged during this mode. The
idle mode can be terminated by any enabled interrupt or by a hardware reset. It
should be noted that when idle is terminated by a hard ware reset, the device
normally resumes program execution, from where it left off, up to two machine
cycles before the internal reset algorithm takes control.

Fig: External Clock Drive Configuration

On-chip hardware inhibits access to internal RAM in this event, but access to
the port pins is not inhibited. To eliminate the possibility of an unexpected write to a
port pin when Idle is terminated by reset, the instruction following the one that
invokes Idle should not be one that writes to a port pin or to external memory.

2.7.2. Power-down Mode:

In the power-down mode, the oscillator is stopped, and the instruction that
invokes power-down is the last instruction executed. The on-chip RAM and Special
Function Registers retain their values until the power-down mode is terminated. The
only exit from power-down is a hardware reset. Reset redefines the SFRs but does
not change the on-chip RAM. The reset should not be activated before VCC is
restored to its normal operating level and must be held active long enough to allow
the oscillator to restart and stabilize.
 The AT89C51 provides the following standard features: 4K bytes of Flash, 128
bytes of RAM, 32 I/O lines, two 16-bit timer/counters, five vector two-level interrupt
architecture, a full duplex serial port, and on-chip oscillator and clock circuitry. In
addition, the AT89C51 is designed with static logic for operation down to zero
frequency and supports two software selectable power saving modes. The Idle Mode
stops the CPU while allowing the RAM, timer/counters, serial port and interrupt
system to continue functioning. The Power down Mode saves the RAM contents but
freezes the oscillator disabling all other chip functions until the next hardware reset.

POWER SUPPLY

Power supply unit consists of Step down transformer, Rectifier, Regulator unit,
filters.

TRANSFORMER RECTIFIER FILTER REGULATOR

AC Voltage
DC Voltage
Fig 4.7 Typical Block of Power Supply

4.7.1 CIRCUIT DIAGRAM OF POWER SUPPLY

 Fig 4.8 Circuit Diagram of Power Supply

4.7.2 STEP DOWN TRANSFORMER:

The Step down Transformer is used to step down the main supply voltage from
230V AC to lower value. This 230 AC voltage cannot be used directly, thus it is
stepped down. The step down voltage is consists of 12V.The Transformer consists of
primary and secondary coils. To reduce or step down the voltage, the transformer is
designed to contain less number of turns in its secondary core. The output from the
secondary coil is also AC waveform. Thus the conversion from AC to DC is essential.
This conversion is achieved by using the Rectifier Circuit/Unit.

4.7.3 RECTIFIER:

The Rectifier circuit is used to convert the AC voltage into its corresponding
DC voltage. Rectifier having three types,

 Half wave rectifier.

 Full wave rectifier.
 Bridge rectifier.
 The most important and simple device used in Rectifier circuit is the diode.
This project used to bridge rectifier. A bridge rectifier makes use of four diodes in a
bridge arrangement to achieve full-wave rectification. This is a widely used
configuration, both with individual diodes wired as shown and with single
component bridges where the diode bridge is wired internally.

Fig 4.9 Bridge Rectifier

The simple function of the diode is to conduct when forward biased and not to
conduct in reverse bias. The Forward Bias is achieved by connecting the diode’s
positive with positive of the battery and negative with battery’s negative. The
efficient circuit used is the Full wave Bridge rectifier circuit. The output voltage of
the rectifier is in rippled form, the ripples from the obtained DC voltage are
removed using other circuits available. The circuit used for removing the ripples is
called Filter circuit.
The simple capacitor filter is the most basic type of power supply filter. The
application of the simple capacitor filter is very limited. It is sometimes used on
extremely high-voltage, low-current power supplies for cathode-ray and similar
electron tubes, which require very little load current from the supply. The capacitor
filter is also used where the power-supply ripple frequency is not critical; this
frequency can be relatively high. The capacitor (C1) shown in figure 4-15 is a simple
filter connected across the output of the rectifier in parallel with the load.
Capacitors are used as filter. The ripples from the DC voltage are removed and
pure DC voltage is obtained. And also these capacitors are used to reduce the
harmonics of the input voltage. The primary action performed by capacitor is
charging and discharging. It charges in positive half cycle of the AC voltage and it
will discharge in negative half cycle. Here we used 1000µF capacitor. So it allows
only AC voltage and does not allow the DC voltage. This filter is fixed before the
regulator. Thus the output is free from ripples.

4.7.4 REGULATOR

Regulator regulates the output voltage to be always constant. Regulator

having two types.
 Positive regulator (78XX)
 Negative regulator (79XX)
The output voltage is maintained irrespective of the fluctuations in the input
AC voltage. As and then the AC voltage changes, the DC voltage also changes. Thus
to avoid this Regulators are used. Also when the internal resistance of the power
supply is greater than 30 ohms, the output gets affected. Thus this can be
successfully reduced here. The regulators are mainly classified for low voltage and
for high voltage. Here we used 7805 positive regulator. It reduces the 12V dc
voltage to 5V dc.

The Filter circuit is often fixed after the Regulator circuit. Capacitor is
most often used as filter. The principle of the capacitor is to charge and discharge. It
charges during the positive half cycle of the AC voltage and discharges during the
negative half cycle. So it allows only AC voltage and does not allow the DC voltage.
This filter is fixed after the Regulator circuit to filter any of the possibly found ripples
in the output received finally. Here we used 0.1µF capacitor. The output at this
stage is 5V and is given to the Microcontroller

Piezoelectric sensors:

Piezoelectric sensors have proven to be versatile tools for the measurement of

various processes. They are used for quality assurance, process control and for
research and development in many different industries. Although the piezoelectric
effect was discovered by Curie in 1880, it was only in the 1950s that the
piezoelectric effect started to be used for industrial sensing applications. Since then,
this measuring principle has been increasingly used and can be regarded as a
mature technology with an outstanding inherent reliability. It has been successfully
used in various applications, such as in medical, aerospace, nuclear
instrumentation, and as a pressure sensor in the touch pads of mobile phones. In
the automotive industry, piezoelectric elements are used to monitor combustion
when developing internal combustion engines. The sensors are either directly
mounted into additional holes into the cylinder head or the spark/glow plug is
equipped with a built in miniature piezoelectric sensor [1].

The rise of piezoelectric technology is directly related to a set of inherent

advantages. The high modulus of elasticity of many piezoelectric materials is
comparable to that of many metals and goes up to 10e6 N/m²[dubious – discuss]. Even
though piezoelectric sensors are electromechanical systems that react to
compression, the sensing elements show almost zero deflection. This is the reason
why piezoelectric sensors are so rugged, have an extremely high natural frequency
and an excellent linearity over a wide amplitude range. Additionally, piezoelectric
technology is insensitive to electromagnetic fields and radiation, enabling
measurements under harsh conditions. Some materials used (especially gallium
phosphate [2] or tourmaline) have an extreme stability even at high temperature,
enabling sensors to have a working range of up to 1000°C. Tourmaline shows
pyroelectricity in addition to the piezoelectric effect; this is the ability to generate
an electrical signal when the temperature of the crystal changes. This effect is also
common to piezoceramic materials.

Strain Sensitivity Threshold Span to threshold

Principle
[V/µ*] [µ*] ratio
Piezoelectri
5.0 0.00001 100,000,000
c
Piezoresisti
0.0001 0.0001 2,500,000
ve
Inductive 0.001 0.0005 2,000,000
Capacitive 0.005 0.0001 750,000

One disadvantage of piezoelectric sensors is that they cannot be used for truly
static measurements. A static force will result in a fixed amount of charges on the
piezoelectric material. While working with conventional readout electronics,
imperfect insulating materials, and reduction in internal sensor resistance will result
in a constant loss of electrons, and yield a decreasing signal. Elevated temperatures
cause an additional drop in internal resistance and sensitivity. The main effect on
the piezoelectric effect is that with increasing pressure loads and temperature, the
sensitivity is reduced due to twin-formation. While quartz sensors need to be cooled
during measurements at temperatures above 300°C, special types of crystals like
GaPO4 gallium phosphate do not show any twin formation up to the melting point of
the material itself.

However, it is not true that piezoelectric sensors can only be used for very fast
processes or at ambient conditions. In fact, there are numerous applications that
show quasi-static measurements, while there are other applications with
temperatures higher than 500°C.
Piezoelectric sensors are also seen in nature. Dry bone is piezoelectric, and is
thought by some to act as a biological force sensor.[3][4]

Principle of operation

Depending on how a piezoelectric material is cut, three main modes of operation

can be distinguished: transverse, longitudinal, and shear.[1]

Transverse effect
A force is applied along a neutral axis (y) and the charges are generated
along the (x) direction, perpendicular to the line of force. The amount of
charge depends on the geometrical dimensions of the respective
piezoelectric element. When dimensions a,b,c apply,
Cx = dxyFyb / a,
where a is the dimension in line with the neutral axis, b is in line with the
charge generating axis and d is the corresponding piezoelectric coefficient.[5]
Longitudinal effect
The amount of charge produced is strictly proportional to the applied force
and is independent of size and shape of the piezoelectric element. Using
several elements that are mechanically in series and electrically in parallel is
the only way to increase the charge output. The resulting charge is
Cx = dxxFxn,
where dxx is the piezoelectric coefficient for a charge in x-direction released
by forces applied along x-direction (in pC/N). Fx is the applied Force in x-
direction [N] and n corresponds to the number of stacked elements .
Shear effect
Again, the charges produced are strictly proportional to the applied forces
and are independent of the element’s size and shape. For n elements
mechanically in series and electrically in parallel the charge is
Cx = 2dxxFxn.

In contrast to the longitudinal and shear effects, the transverse effect opens the
possibility to fine-tune sensitivity on the force applied and the element dimension.

Electrical properties

Schematic symbol and electronic model of a piezoelectric sensor

A piezoelectric transducer has very high DC output impedance and can be modeled
as a proportional voltage source and filter network. The voltage V at the source is
directly proportional to the applied force, pressure, or strain.[2] The output signal is
then related to this mechanical force as if it had passed through the equivalent
circuit.

Frequency response of a piezoelectric sensor; output voltage vs applied force

A detailed model includes the effects of the sensor's mechanical construction and
other non-idealities.[3] The inductance Lm is due to the seismic mass and inertia of
the sensor itself. Ce is inversely proportional to the mechanical elasticity of the
sensor. C0 represents the static capacitance of the transducer, resulting from an
inertial mass of infinite size.[3] Ri is the insulation leakage resistance of the
transducer element. If the sensor is connected to a load resistance, this also acts in
parallel with the insulation resistance, both increasing the high-pass cutoff
frequency.

In the flat region, the sensor can be modeled as a voltage source in series with the
sensor's capacitance or a charge source in parallel with the capacitance

For use as a sensor, the flat region of the frequency response plot is typically used,
between the high-pass cutoff and the resonant peak. The load and leakage
resistance need to be large enough that low frequencies of interest are not lost. A
simplified equivalent circuit model can be used in this region, in which Cs represents
the capacitance of the sensor surface itself, determined by the standard formula for
capacitance of parallel plates.[3][4] It can also be modeled as a charge source in
parallel with the source capacitance, with the charge directly proportional to the
applied force, as above.[2]

Sensor design

Metal disks with piezo material, used in buzzers or as contact microphones

Based on piezoelectric technology various physical quantities can be measured; the

most common are pressure and acceleration. For pressure sensors, a thin
membrane and a massive base is used, ensuring that an applied pressure
specifically loads the elements in one direction. For accelerometers, a seismic mass
is attached to the crystal elements. When the accelerometer experiences a motion,
the invariant seismic mass loads the elements according to Newton’s second law of
motion F = ma.

The main difference in the working principle between these two cases is the way
forces are applied to the sensing elements. In a pressure sensor a thin membrane is
used to transfer the force to the elements, while in accelerometers the forces are
applied by an attached seismic mass.

Sensors often tend to be sensitive to more than one physical quantity. Pressure
sensors show false signal when they are exposed to vibrations. Sophisticated
pressure sensors therefore use acceleration compensation elements in addition to
the pressure sensing elements. By carefully matching those elements, the
acceleration signal (released from the compensation element) is subtracted from
the combined signal of pressure and acceleration to derive the true pressure
information.

Vibration sensors can also be used to harvest otherwise wasted energy from
mechanical vibrations. This is accomplished by using piezoelectric materials to
convert mechanical strain into usable electrical energy.[5]

Sensing materials

Two main groups of materials are used for piezoelectric sensors: piezoelectric
ceramics and single crystal materials. The ceramic materials (such as PZT ceramic)
have a piezoelectric constant / sensitivity that is roughly two orders of magnitude
higher than those of single crystal materials and can be produced by inexpensive
sintering processes. The piezoeffect in piezoceramics is "trained", so unfortunately
their high sensitivity degrades over time. The degradation is highly correlated with
temperature. The less sensitive crystal materials (gallium phosphate, quartz,
tourmaline) have a much higher – when carefully handled, almost infinite – long
term stability.

SOFTWARE REQUIREMENTS

6.1 EMBEDDED C

If programming is done using embedded C then it has following advantages.

Knowledge of the processor instruction set is not required. Rudimentary knowledge
of the memory structure of the 8051 CPU is desirable (but not necessary).details
like register allocation and addressing of the various memory types and data types
is managed by the compiler. Programs get a formal structure (which is imposed by
the C programming language) and can be divided into separate functions. This
contributes to source code reusability as well as better overall application structure.
The ability to combine variable selection with specific operations improves program
readability.

Also the keywords and operational functions that more nearly resemble the
human thought process may be used. If embedded C is used the programming and
program test time is drastically reduced. The C run-time library contains many
standard routines such as: formatted output, numeric conversions and floating point
arithmetic. Existing program parts can be more easily included into new programs
because of modular program construction techniques. The language C is a very
portable language (based on the ANSI standard) that enjoys wide popular support
and is easily obtained for most systems. Existing program investments can be
quickly adapted to other processors has needed.

6.2 KEIL COMPILER

 The keil C51 C compiler for the 8051 microcontroller is the most popular 8051
C compiler in the world. It provides more features than any other 8051 C compiler
available today. The C51 compiler allows you to write 8051 microcontroller
applications in C that, once compiled, have the efficiency and speed of assembly
language. Language extensions in the C51 compiler give you full access to all
resources of the 8051.the C51 compiler translates C source files into relocatable
object modules which contain full symbolic information for debugging with the
micro vision debugger or an in-circuit emulator. In addition to the object file, the
compiler generates a listing file which may optionally include symbol table and
cross reference. Some of the features of keil compiler are

 Nine basic data types.

 Interrupt functions may be written in c.
 Full use of the 8051 registers banks.
 Complete symbol and type information for source-level debugging.
 Use of AJMP and ACALL instructions.
 Bit-addressable data objects.
 Support for dual data pointers on ATMEL, AMD, cypress, dallas
semiconductor, infineon, Philips, and triscend microcontrollers.

6.3 FLASH PROGRAMMER:

Flash memory refers to a particular type of EEPROM, or electronically

erasable programmable read only memory. EEPROM erases its content one byte at
a time. This makes it slow to update. Flash memory can erase its data in entire
blocks, making it a preferable technology for application that require frequent
updating of large amounts of data as in the case of a memory stick. If programming
is done using flash memory then the time to develop code is reduced. Also the
products can be tested and tailored at the end of the assembly line and the code
bugs can be corrected in the field. New product features can be added easily, even
remotely.

6.4 UART Protocol

A universal asynchronous receiver/transmitter (usually abbreviated UART is a

type of "asynchronous receiver/transmitter", a piece of computer hardware that
translates data between parallel and serial forms. UARTs are commonly used in
conjunction with other communication standards such as EIA RS-232.

A UART is usually an individual (or part of an) integrated circuit used for serial
communications over a computer or peripheral device serial port. UARTs are now
commonly included in microcontrollers. A dual UART or DUART combines two UARTs
into a single chip. Many modern ICs now come with a UART that can also
communicate synchronously; these devices are called USARTs.

6.4.1 Transmitting and receiving serial data

Serial transmission of digital information (bits) through a single wire or other

medium is much more cost effective than parallel transmission through multiple
wires. A UART is used to convert the transmitted information between its sequential
and parallel form at each end of the link. Each UART contains a shift register which
is the fundamental method of conversion between serial and parallel forms.

The UART usually does not directly generate or receive the external signals
used between different items of equipment. Typically, separate interface devices
are used to convert the logic level signals of the UART to and from the external
signaling levels.

External signals may be of many different forms. Examples of standards for

voltage signaling are RS-232, RS-422 and RS-485 from the EIA. Historically, the
presence or absence of current (in current loops) was used in telegraph circuits.
Some signaling schemes do not use electrical wires. Examples of such are optical
fiber, IrDA (infrared), and (wireless) Bluetooth in its Serial Port Profile (SPP). Some
signaling schemes use modulation of a carrier signal (with or without wires).
Examples are modulation of audio signals with phone line modems, RF modulation
with data radios, and the DC-LIN for power line communication.

Communication may be "full duplex" (both send and receive at the same
time) or "half duplex" (devices take turns transmitting and receiving).

As of 2008, UARTs are commonly used with RS-232 for embedded systems
communications. It is useful to communicate between microcontrollers and also
with PCs. Many chips provide UART functionality in silicon, and low-cost chips exist
to convert logic level signals (such as TTL voltages) to RS-232 level signals (for
example, Maxim's MAX232).

6.4.2 Asynchronous receive and transmit

In asynchronous transmitting, teletype-style UARTs send a "start" bit, five to

eight data bits, least-significant-bit first, an optional "parity" bit, and then one, one
and a half, or two "stop" bits. The start bit is the opposite polarity of the data-line's
idle state. The stop bit is the data-line's idle state, and provides a delay before the
next character can start. (This is called asynchronous start-stop transmission). In
mechanical teletypes, the "stop" bit was often stretched to two bit times to give the
mechanism more time to finish printing a character. A stretched "stop" bit also
helps resynchronization.

The parity bit can either makes the number of "one" bits between any
start/stop pair odd, or even, or it can be omitted. Odd parity is more reliable
because it assures that there will always be at least one data transition, and this
permits many UARTs to resynchronize.

In synchronous transmission, the clock data is recovered separately from the

data stream and no start/stop bits are used. This improves the efficiency of
transmission on suitable channels since more of the bits sent are usable data and
not character framing. An asynchronous transmission sends no characters over the
interconnection when the transmitting device has nothing to send -- only idle stop
bits; but a synchronous interface must send "pad" characters to maintain
synchronism between the receiver and transmitter. The usual filler is the ASCII
"SYN" character. This may be done automatically by the transmitting device.

USART chips have both synchronous and asynchronous modes.

6.4.3 Serial to Parallel Algorithm

A data communication pulse can only be in one of two states but there are
many names for the two states. When on, circuit closed, low voltage, current
flowing, or a logical zero, the pulse is said to be in the "space" condition. When off,
circuit open, high voltage, current stopped, or a logical one, the pulse is said to be
in the "mark" condition. A character code begins with the data communication
circuit in the space condition. If the mark condition appears, a logical one is
recorded otherwise a logical zero.

The start bit is always a 0 (logic low), which is also called a space. The start
bit signals the receiving DTE that a character code is coming. The next five to eight
bits, depending on the code set employed, represent the character. In the ASCII
code set the eighth data bit may be a parity bit. The next one or two bits are always
in the mark (logic high, i.e., '1') condition and called the stop bit(s). They provide a
"rest" interval for the receiving DTE so that it may prepare for the next character
which may be after the stop bit(s). The rest interval was required by mechanical
Teletypes which used a motor driven camshaft to decode each character. At the
end of each character the motor needed time to strike the character bail (print the
character) and reset the camshaft.

All operations of the UART hardware are controlled by a clock signal which
runs at a multiple (say, 16) of the data rate - each data bit is as long as 16 clock
pulses. The receiver tests the state of the incoming signal on each clock pulse,
looking for the beginning of the start bit. If the apparent start bit lasts at least one-
half of the bit time, it is valid and signals the start of a new character. If not, the
spurious pulse is ignored. After waiting a further bit time, the state of the line is
again sampled and the resulting level clocked into a shift register. After the required
number of bit periods for the character length (5 to 8 bits, typically) have elapsed,
the contents of the shift register is made available (in parallel fashion) to the
receiving system. The UART will set a flag indicating new data is available, and may
also generate a processor interrupt to request that the host processor transfers the
received data. In some common types of UART, a small first-in, first-out (FIFO)
buffer memory is inserted between the receiver shift register and the host system
interface. This allows the host processor more time to handle an interrupt from the
UART and prevents loss of received data at high rates.

Transmission operation is simpler since it is under the control of the

transmitting system. As soon as data is deposited in the shift register, the UART
hardware generates a start bit, shifts the required number of data bits out to the
line, generates and appends the parity bit (if used), and appends the stop bits.
Since transmission of a single character may take a long time relative to CPU
speeds, the UART will maintain a flag showing busy status so that the host system
does not deposit a new character for transmission until the previous one has been
completed; this may also be done with an interrupt. Since full-duplex operation
requires characters to be sent and received at the same time, practical UARTs use
two different shift registers for transmitted characters and received characters.

Transmitting and receiving UARTs must be set for the same bit speed,
character length, parity, and stop bits for proper operation. The receiving UART may
detect some mismatched settings and set a "framing error" flag bit for the host
system; in exceptional cases the receiving UART will produce an erratic stream of
mutilated characters and transfer them to the host system.

Typical serial ports used with personal computers connected to modems use
eight data bits, no parity, and one stop bit; for this configuration the number of
ASCII character per seconds equals the bit rate divided by 10.

6.4.4 History

Some early telegraph schemes used variable-length pulses (as in Morse code)
and rotating clockwork mechanisms to transmit alphabetic characters. The first
UART-like devices (with fixed-length pulses) were rotating mechanical switches
(commutators). These sent 5-bit Baudot codes for mechanical teletypewriters, and
replaced morse code. Later, ASCII required a seven bit code. When IBM built
computers in the early 1960s with 8-bit characters, it became customary to store
the ASCII code in 8 bits.

Gordon Bell designed the UART for the PDP series of computers. Western
Digital made the first single-chip UART WD1402A around 1971; this was an early
example of a medium scale integrated circuit.

An example of an early 1980s UART was the National Semiconductor 8250. In

the 1990s, newer UARTs were developed with on-chip buffers. This allowed higher
transmission speed without data loss and without requiring such frequent attention
from the computer. For example, the popular National Semiconductor 16550 has a
16 byte FIFO, and spawned many variants, including the 16C550, 16C650, 16C750,
and 16C850.

Depending on the manufacturer, different terms are used to identify devices

that perform the UART functions. Intel called their 8251 device a "Programmable
Communication Interface". MOS Technology 6551 was known under the name
"Asynchronous Communications Interface Adapter" (ACIA). The term "Serial
Communications Interface" (SCI) was first used at Motorola around 1975 to refer to
their start-stop asynchronous serial interface device, which others were calling a
UART.

Some very low-cost home computers or embedded systems dispensed with a

UART and used the CPU to sample the state of an input port or directly manipulate
an output port for data transmission. While very CPU-intensive, since the CPU timing
was critical, these schemes avoided the purchase of a costly UART chip. The
technique was known as a bit-banging serial port.

6.4.5 STRUCTURE

A UART usually contains the following components:

 • a clock generator, usually a multiple of the bit rate to allow sampling in the
middle of a bit period.
• input and output shift registers
• transmit/receive control
• read/write control logic
• transmit/receive buffers (optional)
• parallel data bus buffer (optional)
• First-in, first-out (FIFO) buffer memory (optional)

These were the software’s and protocols used in monitoring and controlling the
temperature and voltage.