UNIT-I

44. Mention the classification of saturated bipolar logic families.

The bipolar logic family is classified as follows:

RTL- Resistor Transistor Logic DTL- Diode Transistor logic

I2L- Integrated Injection Logic TTL- Transistor Transistor Logic

ECL- Emitter Coupled Logic

45. Mention the important characteristics of digital IC’s?(AU DEC 2010)

Fan out Power dissipation

PropagationDelay NoiseMargin

Fan In Operating temperature

46. Define Fan-out?(AU MAY 2011)

Fan out specifies the number of standard loads that the output of the gate can
drive with out impairment of its normal operation.

47. Define fan in?(AU MAY 2011)

Fan in is the number of inputs connected to the gate without any degradation in
the voltage level.

48. What are the types of TTL logic?

1. Open collector output 2. Totem-Pole Output 3. Tri-state output.

50. Mention the characteristics of MOS transistor?

· The n- channel MOS conducts when its gate- to- source voltage is positive.
· The p- channel MOS conducts when its gate- to- source voltage is negative
· Either type of device is turned of if its gate- to- source voltage is zero.

51. How schottky transistors are formed and state its use?

A schottky diode is formed by the combination of metal and semiconductor. The

presence of schottky diode between the base and the collector prevents the transistor from
going into saturation. The resulting transistor is called as schottky transistor. The use of
schottky transistor in TTL decreases the propagation delay without a sacrifice of power
dissipation.
52. List the different versions of TTL

1. TTL (Std.TTL) 2.LTTL (Low Power TTL)

3. HTTL (High Speed TTL) 4.STTL (Schottky TTL)

5. LSTTL (Low power Schottky TTL)

53. State advantages and disadvantages of TTL

Advantages:

· Easily compatible with other ICs

· Low output impedance

Disadvantages:

· Wired output capability is possible only with tristate and open collector types
· Special circuits in Circuit layout and system design are required.

54. Add the hexadecimal numbers 93 + DE (AU DEC 2010)

171
55. State De Morgan’s theorem.(AU MAY 2011,DEC 2012,MAY 2014)
De Morgan suggested two theorems that form important part of Boolean algebra.They
are 1)the complement of a product is equal to the sum of the complements.(AB)’ = A + B 2)the
complement of a sum term is equal to the product of the complements.(A + B)’ = A’B’

56. What is meant by non weighted codes.(AU DEC 2013)

These codes are not positionally weighted i.e each position within the binary equivalent
of the number is not assigned a fixed value .Thus, unweighted codes do not obey positional
weighted principle.

57. What are the advantages of CMOS. (AU MAY 2013)

1. Consumes less power
2 .Can be operated at high voltages ,resulting in improved noise immunity.
3. Fan-out is more.
4. Better noise margin.

58. Show that excess-3 code is self complementing. (AU DEC 2010)
Excess-3 code is also known as self complementary ,because it can easily be
complemented(9’s complement) to perform addition in the case of subtraction.

59. In which type of TTL gate wired ANS logic is possible.(AU MAY 2012,DEC 2010)
 Open collector AND gate.

60. Give examples for weighted codes.(AU MAY 2014)

8421, 2421

10.Add the hexadecimal numbers:93 and DE. (A.U.DEC-2010)

Ans: 171
7. State the important characteristics of TTL family? (A.U.DEC-2010)

Fan out

Power dissipation

Propagation Delay

Noise Margin

Fan In

Operating temperature

Power supply requirements

8. In which type of TTL gate wired ANS logic is possible? (A.U.MAY-2012, DEC-2010)
Open collector AND gate

9. Define fan-out and fan in characteristics of digital logic families (A.U.MAY-2011)

Fan out specifies the number of standard loads that the output of the gate can drive without
impairment of its normal operation.

Fan in is the number of inputs connected to the gate without any degradation in the voltage level

24. State advantages and disadvantages of TTL .

Adv:
 Easily compatible with other ICs

Low output impedance

Disadv:

Wired output capability is possible only with tristate and open collector types Special
ci9. State the advantages and disadvantages of Totem pole output?
Advantages:
1. External pull up resistor is not required
2. Operating speed is high
Disadvantages:
Output of two gates cannot be tied together.
rcuits in Circuit layout and system design are required.

33. What are the types of TTL logic?

1. Open collector output

2. Totem-Pole Output

3. Tri-state output.

34. What is depletion mode operation MOS?

If the channel is initially doped lightly with p-type impurity a conducting channel exists
at zero gate voltage and the device is said to operate in depletion mode.

35. What is enhancement mode operation of MOS?

If the region beneath the gate is left initially uncharged the gate field must induce a
channel before current can flow. Thus the gate voltage enhances the channel current and such a
device is said to operate in the enhancement mode.

36. Mention the characteristics of MOS transistor?

1. The n- channel MOS conducts when its gate- to- source voltage is positive.
 2. The p- channel MOS conducts when its gate- to- source voltage is negative

3. Either type of device is turned of if its gate- to- source voltage is zero.

37. How schottky transistors are formed and state its use?

A schottky diode is formed by the combination of metal and semiconductor. The

presence of schottky diode between the base and the collector prevents the transistor from

going into saturation. The resulting transistor is called as schottky transistor.

The use of schottky transistor in TTL decreases the propagation delay without a

sacrifice of power dissipation.

38. List the different versions of TTL

1.TTL (Std.TTL) 2.LTTL (Low Power TTL)

3.HTTL (High Speed TTL) 4.STTL (Schottky TTL)

5.LSTTL (Low power Schottky TTL)

39. Why totem pole outputs cannot be connected together.

Totem pole outputs cannot be connected together because such a connection

might produce excessive current and may result in damage to the devices.

.      A 12-bit Hamming code word containing 8 bits of data and 4 parity bits is read from

memory.What was the original 8-bit data word that was written into memory if the 12-bit word

read out is as follows:

a)000011101010 b)101110000110 c)101111110100

Explain the basic working principles of TTL and ECL logic families.

7 What are the types of digital logic families?Explain briefly any two logic

family with circuit diagram.

Draw the circuit of a CMOS two input NAND gate and NOR gate and explain its operation.
13. Expalin about basic circuit and NOR gate of ECL with its characteristics.

14. Explain about TTL, its wired logic and about the totem pole output, three state output TTL with

its characteristics.

UNIT-II
COMBINATIONAL CIRCUITS

1. What is priority encoder? (A.U.MAY-2012)

A priority encoder is an encoder that includes the priority function. The operation of the
priority encoder is such that if two or more inputs are equal to 1 at the same time, the input
having the highest priority will take precedence.

2. What is code converter?

It is a circuit that makes the two systems compatible even though each uses a different
binary code. It is a device that converts binary signals from a source code to its output code.
example : BCD to Xs3 converter

3.What is the difference between decoder and demultiplexer? (A.U.DEC-2011)

A decoder is designed to simply keep one line high. A demultiplexer is designed to set
one output equal to the input 

4.State De Morgan’s theorem. (A.U.MAY-2011,DEC-2012)

De Morgan suggested two theorems that form important part of Boolean algebra. They
are, 1) The complement of a product is equal to the sum of the complements. (AB)’ = A’ + B’ 2)
The complement of a sum term is equal to the product of the complements. (A + B)’ = A’B’
7.How does don’t care condition in k-map help for circuit simplification? (A.U.DEC-2011)
In some logic circuits certain input conditions never occur, therefore the corresponding
output never appears. In such cases the output level is not defined, it can be either high or low.
These output levels are indicated by ‘X’ or‘d’ in the truth tables and are called don’t care
conditions or incompletely specified functions.
8.Why is MUX called as data selector? (A.U.MAY-2011)
A multiplexer is combinational circuit that selects binary information from one of many
input lines and directs it to a single output line. The selection of a particular input line is
controlled by a set of selection lines. Normally there are 2n input lines and n selection lines
whose bit combinations determine which input is selected. So MUX is called as data selector.

9.Show that excess-3 code is self complementing. (A.U.DEC-2010)

Excess-3 code is also known as self complementary, because it can easily be
complemented(9's complement) to perform addition in the case of subtraction.
11. Define logic gates?
Logic gates are electronic circuits that operate on one or more input signals to produce an
output signal. Electrical signals such as voltages or currents exist throughout a digital system in
either of two recognizable values. Voltage- operated circuits respond to two separate voltage
levels that represent a binary variable equal to logic 1 or logic 0.

12. Define duality property.

Duality property states that every algebraic expression deducible from the postulates of
Boolean algebra remains valid if the operators and identity elements are interchanged. If the dual
of an algebraic expression is desired, we simply interchange OR and AND operators and replace
1’s by 0’s and 0’s by 1’s.

13.Find the complement of the functions F1= x’yz’ + x’y’z and F2= x(y’z’ + yz) by applying
De Morgan’s theorem as many times as necessary.
F1’ = (x’yz’ + x’y’z)’ = (x’yz’)’(x’y’z)’ = (x + y’ + z)(x + y +z’)
F2’ = [x(y’z’ + yz)]’ = x’ + (y’z’ + yz)’ = x’ + (y’z’)’(yz)’
= x’ + (y + z)(y’ + z’)

14. Define binary logic?

Binary logic consists of binary variables and logical operations. The variables are
designated by the alphabets such as A, B, C, x, y, z, etc., with each variable having only two
distinct values: 1 and 0. There are three basic logic operations: AND, OR, and NOT.
15.Reduce A.A’C
A.A’C = 0.c [A.A’ = 1] = 0

16. Reduce A(A + B)

A(A + B) = AA + AB = A(1 + B) [1 + B = 1] = A.

17. Reduce A’B’C’ + A’BC’ + A’BC

A’B’C’ + A’BC’ + A’BC = A’C’(B’ + B) + A’B’C = A’C’ + A’BC [A + A’ = 1]
= A’(C’ + BC) = A’(C’ + B) [A + A’B = A + B]

18. Reduce AB + (AC)’ + AB’C(AB + C)

AB + (AC)’ + AB’C(AB + C) = AB + (AC)’ + AAB’BC + AB’CC
= AB + (AC)’ + AB’CC [A.A’ = 0]
= AB + (AC)’ + AB’C [A.A = 1]
= AB + A’ + C’ =AB’C [(AB)’ = A’ + B’]
= A’ + B + C’ + AB’C [A + AB’ = A + B]
= A’ + B’C + B + C’ [A + A’B = A + B]
= A’ + B + C’ + B’C
=A’ + B + C’ + B’
=A’ + C’ + 1
= 1 [A + 1 =1]

19. Simplify the following using De Morgan’s theorem [((AB)’C)’’ D]’

[((AB)’C)’’ D]’ = ((AB)’C)’’ + D’ [(AB)’ = A’ + B’]
= (AB)’ C + D’
= (A’ + B’ )C + D’

20. Show that (X + Y’ + XY)( X + Y’)(X’Y) = 0

(X + Y’ + XY)( X + Y’)(X’Y) = (X + Y’ + X)(X + Y’ )(X’ + Y) [A + A’B = A + B]
= (X + Y’ )(X + Y’ )(X’Y) [A + A = 1]
 = (X + Y’ )(X’Y) [A.A = 1]
= X.X’ + Y’.X’.Y
= 0 [A.A’ = 0]

21. What do you mean by comparator?

A comparator is a special combinational circuit designed primarily to compare the
relative magnitude of two binary numbers.

22. Convert the given expression in canonical SOP form Y = AC + AB + BC

Y = AC + AB + BC
=AC(B + B’ ) + AB(C + C’ ) + (A + A’)BC
=ABC + ABC’ + AB’C + AB’C’ + ABC + ABC’ + ABC
=ABC + ABC’ +AB’C + AB’C’ [A + A =1]

23.Convert the given expression in canonical POS form Y = ( A + B)(B + C)(A + C)

Y = ( A + B)(B + C)(A + C)
= (A + B + C.C’ )(B + C + A.A’ )(A + B.B’ + C)
= (A + B + C)(A + B + C’ )(A + B +C)(A’ + B +C)(A + B + C)(A + B’ + C) [A + BC =
(A + B)(A + C) Distributive law]
= (A + B + C)(A + B + C’)(A’ + B + C)(A’ + B + C)(A + B’ + C)

24. Find the minterms of the logical expression Y = A’B’C’ + A’B’C + A’BC + ABC’
Y = A’B’C’ + A’B’C + A’BC + ABC’ =m0 + m1 +m3 +m6
26. What are combinational circuits?
A combinational circuit consists of logic gates whose outputs at any time are determined
from the present combination of inputs. A combinational circuit performs an operation that can
be specified logically by a set of Boolean functions. It consists of input variables, logic gates,
and output variables.
32. What are decoders?
 A decoder is a combinational circuit that converts binary information from n input lines
to a maximum of 2n unique output lines. If the n bit coded information has unused combinations,
the decoder may have fewer than 2n outputs.

31. What are encoders?

An encoder is a digital circuit that performs the inverse operation of a decoder. An
encoder has 2n and n output lines. The output lines generate the binary code corresponding to the
input value.

32. Define multiplexer.

Multiplexer is a digital switch. If allows digital information from several sources to be
routed onto a single output line.

33. Write the names of Universal gates.

1. NAND gate 2. NOR gate

34. Why are NAND and NOR gates known as universal gates?
The NAND and NOR gates are known as universal gates, since any logic function can be
implemented using NAND or NOR gates.

6. Draw the truth table and logic circuit of half adder. (A.U.MAY-2010,DEC-2012)

TRUTH TABLE
INPUT OUTPUTS
S
A B SUM CARRY
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
 LOGIC CIRCUIT
28.Define half adder.
A combinational circuit that performs the addition of two bits is called a half adder. A
half adder needs two binary inputs and two binary outputs.

29. Define full adder?

A combinational circuit that performs the addition of three bits is a full adder. It consists
of three inputs and two outputs.
Unit 2
Sixteen marks
1. Determine the prime-implicants of the Boolean function by using the tabulation
method (w, x, y, z)=Σ(1,4,6,7,8,9,10,11,15). (A.U.DEC-2010).
2.     Simplify the following Boolean expression using K-map
F(W,X,Y,Z) = ∑(0,1,2,4,5,6,8,9,12,13,14). (A.U.MAY-2010).
3.     Design a combinational logic diagram for BCD to Excess-3 code converter. (A.U.MAY-
2010)
4. Implement the full adder circuit with 1) Decoder 2) Multiplexer. (A.U.MAY-2011)
5.    Implement the full subtractor using demultiplexer. (A.U.MAY- 2012).
6. Solve g(w,x,y,z) = m(1,3,4,6,11) + d(0,8,10,12,13). A.U.DEC - 2011).

7. Reduce the given expressions using Boolean algebra: (A.U.MAY - 2011).

1. x’y’z’ + x’y’z + x’yz + xy’z + xyz
2. abc’ + ab’c + a’bc + abc.
8. Write brief note on the following: (A.UDEC - 2011).
 (i) DeMorgan’s theorem
(ii) Comparators
(iii) Binary to gray code converter
(iv) Multiplexer
Simplify the following Boolean expression using Quine McCluskey method:
F=∑m(0,9,15,24,29,30)+d(8,11,31).
3.      Design a combinational logic diagram for BCD to Excess-3 code converter.

UNIT-III
5.Draw the circuit of SR flip flop. (A.U.MAY-2010)

1.Define flip-flop
Flip - flop is a sequential device that normally samples its inputs and changes its outputs
only at times determined by clocking signal.

2. List various types of flip-flop

1] S.R. latch 2] D latch 3] Clocked J.K. flip-flop 4] T flip-flop

3. What is race around condition in Flip-flop? (A.U.DEC-2011)

In the JK latch, the output is feedback to the input, and therefore changes in the output
results change in the input. Due to this in the positive half of the clock pulse if J and K are both
high then output toggles continuously. This condition is known as race around condition.

2. What is a self starting counter? (A.U.MAY-2010)

 A self-starting counter is one in which every possible state, even those not in the desired
count sequence, has a sequence of transitions that eventually leads to a valid counter state.

3.Convert JK flip-flop to T flip-flop. (A.U.DEC-2010)

4. Mention the major application of Master Slave FF. (A.U.DEC-2010)

Master Slave FF is mainly used for edge triggering.

5. Draw the state diagram of SR FF. (A.U.DEC-2010)

6. What is Lock out? (A.U.MAY-2012)
In a counter, if the next state of some unused state is again some unused state, it may
happen that the counter remains in unused state never to arrive at a used state. Such a condition
is called Lock out condition.

7. How to avoid Lock out Condition? (A.U.MAY-2012)

1. The counter should be provided with an additional circuit. This will force the counter
from an unused state to the next state as initial state.
2. It is not always necessary to force all unused states into an initial state. Because from
unused states which are not forced, the circuit may eventually arrive at a forced unused
state. This frees the circuit from the Lock out condition.

8. Define synchronous sequential circuit (A.U.MAY-2010)

In synchronous sequential circuits, signals can affect the memory elements only at
discrete instant of time.
9. Write the characteristics table for SR flip flop. (A.U.MAY-2011)
S R Q(t+1) operation
0 0 Q(t) No change
0 1 0 Reset
1 0 1 Set
1 1 ? Undefined

10. How does the state transition diagram of a Moore model differ from Melay model?
(A.U.DEC-2011)

When the output of the sequential circuit depends only on the present state of the flip-
flop, the sequential circuit is referred to as moore circuit. When the output of the sequential
circuit depends on both the present state of flip- flop and on the input, the sequential circuit is
referred to as mealy circuit.

11. Give the characteristic equation and state diagram of JK flip-flop. (A.U.MAY-2012)
Q(t+1)=JQ1+K1Q

12. Write the excitation table for JK flip flop. (A.U.MAY-2011)

Q(t Q(t+1) J K
)
0 0 0 X

0 1 1 X
1 0 X 1
1 1 X 0
13. Define rise time and fall time?
The time required to change the voltage level from 10% to 90% is known as rise time,
and the time required to change the voltage level from 90% to 10% is known as fall time.

14. What are state table and state diagram as applicable to sequential logic circuits?
(A.U.DEC 2012)
State table
 The state table representation of a sequential circuit consists of three sections
labeled present state, next state and output. The present state designates the state of flip-flops
before the occurrence of a clock pulse. The next state shows the states of flip-flops after the
clock pulse, and the output section lists the value of the output variables during the present state.
State diagram
In addition to graphical symbols, tables or equations, flip-flops can also be represented
graphically by a state diagram. In this diagram, a state is represented by a circle, and the
transition between states is indicated by directed lines (or arcs) connecting the circles.

15. The JK flip-flop is a universal flip-flop.Justify. (A.U.DEC 2012)

JK flip-Flop is the most widely used of all the flip-flop designs and is considered to be a
universal flip-flop circuit because the JK flip-flop is basically a gated SR flip-flop with the
addition of a clock input circuitry that prevents the illegal or invalid output condition.

16. What are the types of shift register?

1. Serial in serial out shift register? 2. Serial in parallel out shift register 3. Parallel in
serial out shift register 4. Parallel in parallel out shift register 5. Bidirectional shift register shift
register.

17. What are the types of counter?

1. Synchronous counter 2. Asynchronous Counter

18. What are the two models in synchronous sequential circuits.

1. Moore circuit 2. Mealy circuit

19. What is moore circuit?

When the output of the sequential circuit depends only on the present state of the flip-
flop, the sequential circuit is referred to as moore circuit.

20. What is Mealy circuit?

 When the output of the sequential circuit depends on both the present state of flip- flop
and on the input, the sequential circuit is referred to as mealy circuit.

21. Define successor

In a state diagram, if an input sequence, x takes a machine from state si to state sj, then sj
is said to be the x - successor of si.
23. Define Latch?
It is a sequential device that checks all of its inputs continuously and changes its outputs
accordingly at any time, independent of a clocking signal.
Give state – reduction procedure.
The state – reduction procedure for completely specified state tables is based on the
algorithm that two states in a state table can be combined in to one if they can be shown to be
equivalent.
How does the state transition diagram of a Moore model differ from Mealy model?
(A.U.DEC-2011)
Moore machine
S1 and S2 are states and S1 is an accepting state or a final state. Each edge is labeled with the input.
This example shows an acceptor for strings over {0,1} that contain an even number of zeros.

Mealy machine
S0, S1, and S2 are states. Each edge is labeled with "j / k" where j is the input and k is the output.
Unit 3
Sixteen marks
Convert a SR flip-flop into JK flip-flop. (A.U.MAY- 2012).
2. Design BCD counter using T flip-flop. (A.U.MAY- 2011).
3. Draw the state transition diagram of a sequence detector circuit that detects ‘1010’ from input
data stream using Moore model Mealy model. (A.U.DEC- 2011).

6. Draw the state diagram. Derive the state equation and draw the clocked sequential circuit for
the folowing state table. (A.U.MAY - 2011).
Present state Next state Output
AB X=0 X=1 X=0 X=1
00 00 01 0 0
01 11 01 0 0
10 10 00 0 0
11 10 11 0 0
1. Design a MOD – 10 synchronous counter using JK flip-flops. Write the
excitation table and state table.
2. Design a sequential circuit with four flip-flops ABCD. The next states of B, C, and D
are equal to the present states of A, B, C respectively. The next state of A is equal to
the EX- OR of present states of C and D.
UNIT-Iv

ASYNCHRONOUS SEQUENTIAL CIRCUITS

. Define asynchronous sequential circuit? (A.U.DEC-2010)

In asynchronous sequential circuits change in input signals can affect memory element at
any instant of time
How does the operation of an asynchronous input differ from that of a asynchronous
input? (A.U.MAY-2012)
 Synchronous inputs are those whose effect on the flip-flop output is synchronized with the clock
input. R, S, J, K and D inputs are all synchronous inputs. Asynchronous inputs are those that operate
independently of the synchronous inputs and the input clock signal.

7. What is the difference between asynchronous and synchronous sequential circuits?

(A.U.MAY-2011)
Synchronous sequential circuits Asynchronous sequential circuits
Memory elements are clocked flip- Memory elements are either unlocked flip -
flops
flops or time delay elements.

Easier to design More difficult to design

. Define flow table in asynchronous sequential circuit. (A.U.MAY-2012)

In asynchronous sequential circuit state table is known as flow table because of the
behaviour of the asynchronous sequential circuit. The stage changes occur in independent of a
clock, based on the logic propagation delay, and cause the states to .flow. from one to another.

12. What is fundamental mode of operation in asynchronous sequential circuit?

(A.U.DEC-2011)
Fundamental mode circuit assumes that. The input variables change only when the
circuit is stable. Only one input variable can change at a given time and inputs are levels and not
pulses.

Sketch the block diagram of an asynchronous sequential circuit.

15. What are the types of hazards?

The 3 types of hazards are
1) Static – 0 hazards
2) Static – 1 hazard
3) Dynamic hazards

16. What are the problems involved in asynchronous circuits?

The asynchronous sequential circuits have three problems namely,
a. Cycles
b. Races
c. Hazards
17. Define cycles?
If an input change includes a feedback transition through more than unstable state then
such a situation is called a cycle.

18. Define primitive flow table?

A primitive flow table is a flow table with only one stable total state in each row.
Remember that a total state consists of the internal state combined with the input.

19. What is a ‘race condition’ in an asynchronous sequential circuit? (A.U.DEC-2012)

A race condition is said to exist in asynchronous sequential circuit when two or more
binary state variables change, the race is called non-critical race.

20. Define critical & non-critical race with example.

The final stable state that the circuit reaches does not depend on the order in which the
state variables change, the race is called non-critical race.
The final stable state that the circuit reaches depends on the order in which the state
variables change, the race is called critical race.

21. How can a race be avoided?

Races can be avoided by directing the circuit through intermediate unstable states with a
unique state – variable change.
List basic types of programmable logic devices.
1. Programmable Read only memory (PROM)
2. Programmable logic Arrays (PLA)
3. Programmable Array Logic (PAL)
4. Field Programmable Gate Array (FPGA)
5. Complex Programmable Logic Devices (CPLD)
5. What is programmable logic array (PLA)? How it differs from ROM? (A.U.MAY-2012)
A PLA is similar to a ROM in concept; however it does not provide full decoding of the
variables and does not generates all the minterms as in the ROM. In some cases the number of
don’t care conditions is excessive, it is more economical to use a second type of LSI component
called a PLA.

6. List the configurable elements in the FPGA architecture? (A.U.MAY-2012)

i)a set of congurable logic elements
ii)on chip memory blocks
iii)digital signal processing (DSP) blocks (including multipliers)
iv)connected by a congurable wire network
v)all connected to outside world by I/O pins
11. What is the advantage of PLA over ROM? (A.U.MAY-2010,DEC-2012)

PLA is the most flexible having a programmable set of ANDs combined with a
programmable set of ORs.
22. What is field programmable logic array?
The second type of PLA is called a field programmable logic array. The EPLA can be
programmed by the user by means of certain recommended procedures.

23. Give the comparison between prom and PLA.

PROM
1. AND array is fixed and OR array is programmable
2. Cheaper and simple to use.
PLA
1. Both AND and OR arrays are Programmable
2. Costliest and complex than PROMS.

Unit 4
Sixteen marks
Design an asynchronous sequential circuit that has two inputs X1 and X1 and one output Z.
When X1=0, the output Z is 0. The first change in X2 that occurs while X1 is 1 will cause output
Z to be 1. The output Z will remain 1 until X1 returns to 0.
Implement the following two Boolean functions with a PLA: F1(A,B,C) = (0, 1, 2, 4)
F2(A,B,C) = (0,5,6,7).(A.U.MAY- 2011).

.   Draw the state diagram and obtain the primitive flow table for a circuit with two inputs x1
and x2 and two outputs z1 and z2 that satisfies the following conditions.
1. When x1x2=00, output z1z2=00.
2. When x1=1 and x2 changes from 0 to 1, the output z1z2=01.
3. When x2=1 and x1 changes from 0 to 1, output z1z2=10.
Otherwise output does not change.

UNIT-V
VHDL

TWO MARK QUESTIONS AND ANSWERS

1. Write the VHDL code for AND gate. (A.U.DEC-2010)

entity ha1 is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c: out STD_LOGIC;);
end ha1;
architecture Behavioral of ha1 is
begin
c<=a and b;
end Behavioral;

2. List the operators available in VHDL. (A.U.DEC-2010, DEC-2011,DEC-2012)

i)Logical Operators

ii)Arithmetic Operators
iii)Relational Operators

iv)Shift Operators

3.Write HDL for half adder? (A.U.MAY-2010, MAY -2012)

Entity half is
Port(a,b:in bit;sum,carry:out bit);
End half;
Architecture half_adder of half is
begin
(Sum<= a xor b;
Carry<=a and b);
End half_adder;

4. What are the various modelling techniques in VHDL? (A.U.MAY-2010, MAY-

2012,DEC-2012)

i.Structural modelling
ii.Dataflow modelling
ii.Behavioural modelling

5. When can RTL be used to represent digital systems? (A.U.MAY-2011)

Designs using the Register-Transfer Level specify the characteristics of a circuit by
operations and the transfer of data between the registers. An explicit clock is used. RTL design
contains exact timing possibility, operations are scheduled to occur at certain times. Any code
that is synthesizable can used RTL .

6. What are ASM? (A.U.MAY-2011)

The Algorithmic State Machine (ASM) method is a method for designing finite state
machines. It is used to represent diagrams of digital integrated circuits. The ASM diagram is like
a state diagram but less formal and thus easier to understand. An ASM chart is a method of
describing the sequential operations of a digital system.

7. What are the different levels of design abstraction at physical design?

• Architectural or functional level
• Register Transfer-level (RTL)
• Logic level
• Circuit level

8. Write the VHDL coding for a sequential statement d-flip-flop.

entity dff is

port(clk,d:in std_logic;

q:out std_logic);

end;

architecture dff of dff is

begin

process(clk,d)

begin

if clk’ event and clk=’ 1’ then

q<=d;

end process;

end;

9. What are the different kinds of the test bench?

i.Stimulus only

ii.Full testbench
 iii.Simulator specific

iv.Hybrid testbench

v.Fast testbench

10. What is Moore FSM

The output of a Moore finite state machine(FSM) depends only on the state and not on its
inputs. This type of behaviour can be modeled using a single process with the case statement that
switches on the state value.

11. Write the syntax of procedure body?

Procedure procedure name (parameterlist)

12. What is test bench?

A test bench is a model which is used to exercise and verify the correctness of a hardware
model.

13. What are the two methods to generate stimulus values?

i. To create waveforms and apply stimulus at discrete time intervals.

ii. To generate stimulus based on the state of the entity or output of the entity.
iii.
14. What is a package and what is the use of these packages

A package declaration is used to store a set of common declaration such as components

types procedures and functions these declaration can then be imported into others design units
using a use caluse.

15. What is variable class, give example for variable

An object of variable class can also hold a single value of a given type, however in this
case different values can be assigned to a variable at different time.

Ex:variable ss: integer;

16. What are the data types available in VHDL?

i. Scalar type
ii. Composite type
iii. Access type
iv. File type

17. What are the types of subprograms?

Functions and Procedures are types of subprograms.

18.. What is the use of actual?

Actual in a subprogram call is used to pass the values from and to a subprogram.

19. What is HDL and VHSIC?

VHSIC Hardware description Language. Very High Sped Integrated Circuits.

20. Write the VHDL code for 1 to 4 demultiplexer.

entity demux is
port (
D0 : in std_logic_vector(7 downto 0);
D1 : in std_logic_vector(7 downto 0);
D2 : in std_logic_vector(7 downto 0);
D3 : in std_logic_vector(7 downto 0);
SEL : in std_logic_vector(1 downto 0);
Y : out std_logic_vector(7 downto 0));
end demux;
architecture behave of demux is
begin -- behave
with SEL select
Y <= D0 when "00",
D1 when "01",
D2 when "10",
 D3 when "11",
(others => 'X') when others;
end behave;
21. Write the VHDL code for AND gate.
LIBRARY ieee:
USE ieee.std_logic_1164.all;
Entity And1 is
Port(x:in std_logic;
Y: in std_logic;);
END And1;
architecture beha2 of And1 is
begin
F<=x and y;
End beha2;

Construct a VHDL module listing for a 16:1 MUX that is based on the assign statement.Use a 4-bit
select word to map the selected input Pi(i=0,….15) to the output. (A.U.DEC- 2010).