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DESIGN AND ANALYSIS OF SYNCHRONOUS 8 BIT UP COUNTER USING CMOS PROCESS
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CHAPTER-1
INTRODUCTION
1.1 INTRODUCTION TO VLSI:
1.1.1 Historical Perspective:

The electronics industry has achieved a phenomenal growth over the last two
decades, mainly due to the rapid advances in integration technologies, large-scale
systems design - in short, due to the advent of VLSI. The number of applications of
integrated circuits in high-performance computing, telecommunications, and consumer
electronics has been rising steadily, and at a very fast pace. Typically, the required
computational power (or, in other words, the intelligence) of these applications is the
driving force for the fast development of this field. Figure 1.1 gives an overview of the
prominent trends in information technologies over the next few decades. The current
leading-edge technologies (such as low bit-rate video and cellular communications)
already provide the end-users a certain amount of processing power and portability.
Figure-1.1: overview of the prominent trends in information technologies
This trend is expected to continue, with very important implications on VLSI and systems
design. One of the most important characteristics of information services is their
increasing need for very high processing power and bandwidth (in order to handle real-
time video, for example). The other important characteristic is that the information
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services tend to become more and more personalized (as opposed to collective services
such as broadcasting), which means that the devices must be more intelligent to answer
individual demands, and at the same time they must be portable to allow more
ERA DATE COMPLEXITY
(number of logic blocks per
chip)
Single transistor 1959 less than 1
Unit logic (one gate) 1960 1
Multi-function 1962 2–4
Complex function 1964 5 – 20
Medium Scale Integration 1967 20 - 200 (MSI)
Large Scale Integration 1972 200 – 2000 (LSI)
Very Large Scale Integration 1978 2000 – 20000 (VLSI)
Ultra Large Scale Integration 1989 20000 - ?(ULSI)
flexibility/mobility
As more and more complex functions are required in various data processing and
telecommunications devices, the need to integrate these functions in a small
system/package is also increasing.The level of integration as measured by the number of
logic gates in a monolithic chip has been steadily rising for almost three decades, mainly
due to the rapid progress in processing technology and interconnect technology. Table 1.1
shows the evolution of logic complexity in integrated circuits over the last three decades,
and marks the milestones of each era.
Table-1.1: Evolution of logic complexity in integrated circuits.
Here, the numbers for circuit complexity should be interpreted only as

representative examples to show the order-of-magnitude. A logic block can contain
anywhere from 10 to 100 transistors, depending on the function. State-of-the-art

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examples of ULSI chips, such as the DEC Alpha or the INTEL Pentium contain 3 to 6
million transistors.The most important message here is that the logic complexity per chip
has been (and still is) increasing exponentially. The monolithic integration of a large
number of functions on a single chip usually provides:
⮚ Less area/volume and therefore, compactness

⮚ Less power consumption
⮚ Less testing requirements at system level
⮚ Higher reliability, mainly due to improved on-chip interconnects
⮚ Higher speed, due to significantly reduced interconnection length
⮚ Significant cost savings
Figure-1.2 : Evolution of integration density and minimum feature size, as

seen in the early 1980s.
Therefore, the current trend of integration will also continue in the foreseeable
future. Advances in device manufacturing technology, and especially the steady reduction
of minimum feature size (minimum length of a transistor or an interconnect realizable on
chip) support this trend. Figure 1.2 shows the history and forecast of chip complexity -
and minimum feature size - over time, as seen in the early 1980s. At that time, a
minimum feature size of 0.3 microns was expected around the year 2000. The actual
development of the technology, however, has far exceeded these expectations. A

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minimum size of 0.25 microns was readily achievable by the year 1995. As a direct result
of this, the integration density has also exceeded previous expectations - the first 64 Mbit
DRAM, and the INTEL Pentium microprocessor chip containing more than 3 million
transistors were already available by 1994, pushing the envelope of integration density.
When comparing the integration density of integrated circuits, a clear distinction

must be made between the memory chips and logic chips. Figure 1.3 shows the level of
integration over time for memory and logic chips, starting in 1970. It can be observed
that in terms of transistor count, logic chips contain significantly fewer transistors in any
given year mainly due to large consumption of chip area for complex interconnects.
Memory circuits are highly regular and thus more cells can be integrated with much less
area for interconnects.
Figure-1.3: Level of integration over time, for memory chips and logic chips.
Generally speaking, logic chips such as microprocessor chips and digital signal
processing (DSP) chips contain not only large arrays of memory (SRAM) cells, but also
many different functional units. As a result, their design complexity is considered much
higher than that of memory chips, although advanced memory chips contain some
sophisticated logic functions. The design complexity of logic chips increases almost
exponentially with the number of transistors to be integrated. This is translated into the
increase in the design cycle time, which is the time period from the start of the chip
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development until the mask-tape delivery time. However, in order to make the best use of
the current technology, the chip development time has to be short enough to allow the
maturing of chip manufacturing and timely delivery to customers. As a result, the level of
actual logic integration tends to fall short of the integration level achievable with the
current processing technology. Sophisticated computer-aided design (CAD) tools and
methodologies are developed and applied in order to manage the rapidly increasing
design complexity.
1.1.2 VLSI Design Flow
The design process, at various levels, is usually evolutionary in nature. It starts

with a given set of requirements. Initial design is developed and tested against the
requirements. When requirements are not met, the design has to be improved.
If such improvement is either not possible or too costly, then the revision of
requirements and its impact analysis must be considered. The Y-chart (first introduced by
D. Gajski) shown in Figure1.4 illustrates a design flow for most logic chips, using design
activities on three different axes (domains) which resemble the letter Y.
The Y-chart consists of three major domains, namely:
⮚ behavioral domain,
⮚ structural domain,
⮚ geometrical layout domain.

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Figure-1.4: Typical VLSI design flow in three domains (Y-chart

representation)
The design flow starts from the algorithm that describes the behavior of the target
chip. The corresponding architecture of the processor is first defined. It is mapped onto
the chip surface by floor planning. The next design evolution in the behavioral domain
defines finite state machines (FSMs) which are structurally implemented with functional
modules such as registers and arithmetic logic units (ALUs).
These modules are then geometrically placed onto the chip surface using CAD
tools for automatic module placement followed by routing, with a goal of minimizing the
interconnects area and signal delays. The third evolution starts with a behavioral module
description. Individual modules are then implemented with leaf cells. At this stage the
chip is described in terms of logic gates (leaf cells), which can be placed and
interconnected by using a cell placement & routing program. The last evolution involves
a detailed Boolean description of leaf cells followed by a transistor level implementation
of leaf cells and mask generation. In standard-cell based design, leaf cells are already pre-
designed and stored in a library for logic design use.
It provides a more simplified view of the VLSI design flow, taking into account
the various representations, or abstractions of design - behavioral, logic, circuit and mask
layout. Note that the verification of design plays a very important role in every step
during this process. The failure to properly verify a design in its early phases typically
causes significant and expensive re-design at a later stage, which ultimately increases the
time-to-market.

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Although the design process has been described in linear fashion for simplicity, in
reality there are many iterations back and forth, especially between any two neighboring
steps, and occasionally even remotely separated pairs. Although top-down design flow
provides an excellent design process control, in reality, there is no truly unidirectional
top-down design flow. Both top-down and bottom-up approaches have to be combined.
For instance, if a chip designer defined an architecture without close estimation of the
corresponding chip area, then it is very likely that the resulting chip layout exceeds the
area limit of the available technology. In such a case, in order to fit the architecture into
the allowable chip area, some functions may have to be removed and the design process
must be repeated. Such changes may require significant modification of the original
requirements. Thus, it is very important to feed forward low-level information to higher
levels (bottom up) as early as possible.
In the following, it will examine design methodologies and structured approaches

which have been developed over the years to deal with both complex hardware and
software projects. Regardless of the actual size of the project, the basic principles of
structured design will improve the prospects of success. Some of the classical techniques
for reducing the complexity of IC design are: Hierarchy, regularity, modularity and
locality.
1.1.3 Design Hierarchy:
The use of hierarchy, or divide and conquer technique involves dividing a module
into sub- modules and then repeating this operation on the sub-modules until the
complexity of the smaller parts becomes manageable. This approach is very similar to the
software case where large programs are split into smaller and smaller sections until
simple subroutines, with well-defined functions and interfaces, can be written. In this
section the design of a VLSI chip can be represented in three domains. Correspondingly,
a hierarchy structure can be described in each domain separately. However, it isimportant
for the simplicity of design that the hierarchies in different domains can be mapped into
each other easily.

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1.1.4 VLSI Design Styles:
Several design styles can be considered for chip implementation of specified

algorithms or logic functions. Each design style has its own merits ,000000 shortcomings,
and thus a proper choice has to be made by designers in order to provide the functionality
at low cost.
Counting is a fundamental function of digital circuits. A digital counter consists

of a collection of flip-flops that change state (set or reset) in a prescribed sequence. The
primary function of a counter is to produce a specified output pattern sequence. For this
reason it is also a pattern generator. This pattern sequence might correspond to portions
the number of occurrences of an event or it might be used to control several of a digital
system. In this latter case each pattern is associated with a distinct operation that the
digital system must perform.
The different number of implementations of a counter is vast. With options such

as synchronous vs. asynchronous, what flip-flops to use, and the style of counting
(binary, gray code, etc.), hundreds of different counters could be designed. The counter
described in this paper was designed to be a synchronous up-counter. This just means that
the whole design is controlled by a single clock and that the counter will only count from
0 to F and start back over. The counter is realized using D flip-flops. The D flip-flop was
chosen because of its simplicity over the JK flip-flop; it only takes 1 input instead of 2,
and it requires less interconnect which should lead to less delay. Also, the synchronous
up-counter nature of the design was chosen because it was easy to implement.
Several counter circuits have been proposed targeting on design accents such as
power, delay and area. Among those designs synchronous counters using master-slave D
flip-flops have been widely used.
1.2Motivation:
A counter is an electronic device which counts the number of times a particular event has
occurred. The main goal of this project is to optimize the area, and power of the counter

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by using CMOS technology. By decreasing the power, area and delay the performance of
the counter increases. Here the CMOS technology is used. The schematic and layout are
designed by DSCH Tool and Microwind.
1.3 Objectives :
The main objectives are
● To implement synchronous 4 bit counter using 120 nm CMOS technology.
● To implement synchronous 8 bit counter using 120 nm CMOS technology.
● To compare the results of counters in both the technologies i.e., 180 and 120nm
technologies.
1.4Software requirements:
The software tools are
1. DSCH Tool
2. Microwind Software
1.5 Design methodology:

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Figure1.5: Flow chart of design methodology
1.6 Organization of the project:

In Chapter 1, introduction to VLSI, counters and the basic theme for this project.
In Chapter 2, literature survey regarding synchronous up counters and gives the
description of circuit design.
In Chapter 3, explains about the project and describes each gate consisting in the
circuit and also explains their operation.
In Chapter 4, explains about the procedures and tools regarding the project and
its salient features, introduces the DSCH and Microwind tools step by step procedure to
implement the 8bit synchronous counter using 120nm technology.
In Chapter 5, discusses about the simulation results and the parameters that are
obtained.
In Chapter 6 concludes the thesis and future scope of project further research.
1.7Applications:
The counter can be used in many applications. Some of the applications are as follows:
1. In Real time clock: It is a computer clock which keeps track of the current time. And
also used in any electronic device which needs to keep accurate time.
2. In Digital clocks: Counters are used in digital clocks in order to count the seconds,
minutes and hours
3. Microwave ovens: Counters are used in micro ovens in order to count the time of
operation of the microwave oven
4. Other home appliances: Counters are very much used in the electronic where they are
automated i.e, like washing machines, A.C, T.V etc, counters added a special feature for
the home appliances as automatic stop.

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CHAPTER-2
LITERATURE SURVEY
2.1 Introduction:
In modern technology the digital counters have a very important role. Counters
are among the most basic of designs in digital systems; they are also good examples for
beginner designers to walk through because of their simplicity. Along with being simple
to make, counters, in general, are quintessential components of most digital systems as
they are used to store (and sometimes display) the number of times a particular event has
occurred.
The main aim is to design a 8 bit synchronous counter which has the low power
consumption and area minimized. Before there is a design and implementation of 4 bit
synchronous up counter using CMOS technology but using this counter it experience the
high power consumption and area is also high. So we are designing the synchronous up
counter with CMOS technology which consumes lesser power compared to the previous
one and analyzed the area.

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2.2 Circuit design:

There are a number of factors to consider when choosing an appropriate design
for a low voltage counter. By using a high static leakage technology, a large number of
transistors in the design can be a significant source of static power dissipation. It can
therefore be beneficial to keep the size of the circuit as small as possible. However, if in
reducing the size of the circuit, the delay is increased, then this can negatively affect the
amount of energy consumed per cycle. The simplest counter with the fewest number of
gates is the asynchronous (ripple) counter . This type of counter can be constructed using
nothing but flip-flops connected in series. Each previous flip flop acts as the clock for the
higher order flip flop. When the least significant bit makes, the information is rippled
through to each successive flip-flop changing values as necessary. The asynchronous
counter can be useful in small counters, but as the number of bits of the counter grows,
this ripple effect causes an increasing delay period in which the output of the counter is
indeterminate.
2.3Research papers:
Research paper 1:
A new D flip flop which is named as Switching Transistor Based D Flip Flop (STDFF) is
designed in this research paper. This system shows 85% Power improvement than the
Existing Data Transition look ahead D Flip-Flop and it shows an improvement of 40% in
area constraints. Thus the system is having very less power and area constraints which
will lead to improvement in the case implementation in future mobile devices. This can
be much suitable for application of battery oriented operation for less power and area. In
future we can add some other leakage reduction techniques and the power can be further
reduced.
Research paper 2:
A clock gated scheme is embedded into the flip-flop has been proposed to eliminate
redundant switching due to the clock and it minimized the power consumption. The

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experimental result using a CMOS process indicates the 15% power consumption. The
power consumption of clock gated circuit is 0.143 mw. This technique can further be
used in complex parallel counters to reduce power consumption.
Research paper 3:
This research paper includes the design of 2 bit synchronous up counter. Performance
analysis of auto generated layout and proposed layout also be done in this paper. For the
optimized area efficient proposed layout of synchronous up counter, 2 types of design has
been used. One in which D flip flop is made by transmission gate and another one in
which D flip flop is made by NMOS. From the result it is clear that optimized proposed
layout of synchronous up counter is more area efficient than auto generated layout design
.As optimized layout provide
52.16 % less area than the auto generated layout and 52.04% from the layout which used
transmission gate as d flip flop. Number of transistor requirement is also less in proposed
area efficient optimized layout
Some research papers are referred for designing the counter. They are listed below
1. YogithaHiremath, Akalpita L. Kulkarni, J.S. Baligar proposed a paper on design
and implementation of 4 Bit up counter by using 180nm CMOS technology. In
this paper they had designed the 4 bit up counter using the 180 nm technology by
cadence software tool. They designed the counter by using the master slave d
flipflop.
2. Pragati Gupta, Rajesh Mehra proposed a paper on area efficient CMOS design
analysis of synchronous up counter. In this paper they had designed a 2 bit
counter which has a more area efficient than the auto generated layout in
microwind tool.
3. Ritesh Pawar, Rajesh Mehra proposed a paper on CMOS layout design of area
efficient synchronous down counter. In this paper they had designed a 2 bit
counter which layout area is reduced by self generated counter than the automatic
generated layout area.

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CHAPTER-3
DESCRIPTION ABOUT PROJECT
3.1 Implementation of synchronous 8 bit counter:

Synchronous counter is the most popular type of counter. It typically consists of a
memory element, which is implemented using flip-flops and a combinational element,
which is traditionally implemented using logic gates. Logic gates are logic circuits with
one or more input terminals and one output terminal in which the output is switched
between two voltage levels determined by a combination of input signals. The use of
logic gates for combinational logic typically reduces the cost of components for counter
circuits to an absolute minimum, so it remains a popular approach.
Synchronous counters have an internal clock, whereas asynchronous counters do
not. As a result, all the flip-flops in a synchronous counter are driven simultaneously by a
single, common clock pulse. In an asynchronous counter, the first flip-flop is driven by a
pulse from an external clock and each successive flip-flop is driven by the output of the
preceding flip-flop in the sequence. This is the essential difference between synchronous
and asynchronous counters. The propagation delay of synchronous counter is
comparatively lower than asynchronous counter. Its performance is also better from a
reliability perspective because there is no glitch

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3.1.1 Inverter:
An inverter circuit outputs a voltage representing the opposite logic-level to its
input. Its main function is to invert the input signal applied. If the applied input is low
then the output becomes high and vice versa. If the input is low (0 V) corresponding
PMOS will be shorted and NMOS will opened then Vout is shorted to Vdd which
provides high output.
If the input is high (5V) corresponding PMOS will be opened and NMOS will shorted
then Vout which provides low output.
Figure 3.1: Inverter

Truth table:
Table 3.1-Truth table of inverter

INPUT OUTPUT
0 1
1 0

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Timing diagram:
IN
OUT
Figure3.2:Timing diagram of inverter
3.1.2 NAND gate:

CMOS NAND gate is one of the important and simple realizations. CMOS is the
combination of PMOS and NMOS. The circuit shows the realization of CMOS NAND
gate which consists of two PMOS and two NMOS gates. Here in this circuit when Va
and Vb are high i.e. at 5V then the two PMOS will be open circuited and two NMOS will
be Short circuited. The output Vout will be shorted to ground and produces zero output.
If any of the input is low (0 V) corresponding PMOS will be shorted and NMOS will
opened then Vout is shorted to Vdd which provides high output. The table 3.3 shows all
the possible operation of NAND gate using CMOS.
Figure 3.3: NAND gate

VA VB VOUT
0 0 1

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0 1 1
1 0 1
1 1 0
Truth table:
Table 3.2-Truth table of NAND gate
Timing diagram:
VA
VB
VOUT
Figure 3.4:Timing diagram of NAND Gate
3.1.3 AND gate:

CMOS AND gate is one of the important and simple realizations. CMOS is the
combination of PMOS and NMOS. The circuit shows the realization of CMOS AND gate
which consists of three PMOS and three NMOS gates. Here in this circuit when Va and
Vb are high i.e. at 5V then the two PMOS will be open circuited and two NMOS will be
short circuited.The output Vout will be shorted to vdd and produces one as output.
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If any of the input is low (0 V) corresponding PMOS will be open and NMOS will
shorted the Vout is open to Vdd which provides low output. The table 3.3 shows all the
possible operation of AND gate using CMOS.
Figure 3.5:AND gate
Truth table:
Table 3.3-Truth table of AND gate

A b ab
0 0 0
0 1 0
1 0 0
1 1 1
Timing diagram:
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Figure 3.6:Timing diagram of AND Gate
3.1.4 EX-OR gate:

The table3 .4 shows that the output of an Exclusive-OR gate ONLY goes “HIGH”
when both of its two input terminals are at “DIFFERENT” logic levels with respect to
each other. If these two inputs, A and B are both at logic level “1” or both at logic level
“0” the output is a “0” making the gate an “odd but not the even gate”.
In other words, the output is “1” when there are an odd number of 1’s in the inputs.
Figure 3.7 Exclusive OR gate

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Truth table:
Table 3.4-Truth table of Exclusive OR gate
A B OUT
0 0 0
0 1 1
1 0 1
1 1 0
Timing diagram:

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Figure 3.8: Timing diagram of Exclusive OR Gate
3.2 Master-slave d flip-flop:

A master-slave D flip-flop is created by connecting two gated D latches in series
and inverting the enable input to one of them. It is called master-slave because the second
(slave) latch in the series only changes in response to a change in the first (master) latch .
The term pulse-triggered means that data is entered on the rising edge of the clock pulse,
but the output does not reflect the change until the falling edge of the clock pulse.
Master-slave flip-flops can be constructed to behave as a J-K, R-S, T or D flip-flop.
The purpose of master-slave flip-flops is to protect a flip-flop’s output from

inadvertent changes caused by glitches on the input. Master-slave flip-flops are used in
applications where glitches may be prevalent on inputs.
The master-slave configuration has the advantage of being pulse-triggered, making it

easier to use in larger circuits, since the inputs to a flip-flop often depend on the state of
its output.
Figure3.9 shows negative pulse-triggered master-slave D flip-flop. It responds on the

negative edge of the enable input (usually a clock). The circuit consists of two D flip-
flops connected together.

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Figure 3.9: Master-slave d flip-flop
When the clock is high, the D input is stored in the first latch, but the second latch
cannot change state. When the clock is low, the first latch's output is stored in the second
latch, but the first latch cannot change state. The result is that output can only change
state when the clock makes a transition from high to low.
Figure3.10:Transient response of master slave D flip flopTruth table:
Table 3.5-Truth table of master slave dff
CLK QN+1 (NEXT STATE )
0 D

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1 Qn (present state)
Master changes its state when clock is high while the latter changes its state when
clock is low. When the clock is high the master tracks the value of D but since the slave
is in inactive state, Qs also remains unchanged. When the clock signal goes low, the
master goes to inactive state and the slave which is now in active state tracks the value of
Qm. While clock is low, Qm does not change its value. Thus only once during the clock
cycle the slave can undergo change in its value. It can also be observed that only during
the transition from high to low, the output gets change. This transition is referred to as
"negative pulse-triggered"
3.2.1 Master -slave d flip-flop with clear input:

Figure3.11 shows the implementation of master-slave D flip-flop with clear input.
Figure3.11 Master -slave d flip-flop with clear input
The circuit is designed using the truth table given in table 3.6. When the clr
(clear) input goes high, irrespective of the inputs D and clock, the output goes low.
Truth table:
Table 3.6-Truth table of master slave dff with clear input

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Clr Clk Qs (next state)
0 0 D
0 1 Qn (present state )
1 X 0
3.3 Implementation of Synchronous 4-Bit Up Counter :
The synchronous 4-bit up counter has 3 AND gates, 4 XOR gates and 4 master-
slave D flip-flops. Same clock pulse is given to each flip-flop. So with every clock pulse
the counter counts one step up. It is an up counter and starts from 0000. Then with clock
pulse counts like 0001, 0010, 0011, 0100 up to 1111. Then it starts from 0000 again. Q0
is the LSB and Q3 is the MSB. The master-slave D flip-flop actually works at the falling
edge of the clock. But because it is a master slave configuration [8], it actually stores the
input at rising edge and it is given to the output at the falling edge of the clock. So change
in counter output is observed in the falling edge of the clock. There are 2 additional
inputs in the counter, count enable (CE) and clear (clr).
1. Count Enable (CE) input: If CE=0, then counter stops counting. IF CE=1, each clock
pulse results in a counting action
2. Clear (clr) input: If clr=1, then the counter output clears to 0000. If clr=0, each clock
pulse results in a counting action.
Figure 3.12 is formally known as a state diagram because each ellipse represents one of
the states that the circuit can ever possibly be in, and each arrow shows how the circuit
moves from state to state depending on whether the enable switch (E) is 1 or 0. The
colored arrow shows that after the circuit has reached the number fifteen (1111), it will
restart at zero (0000) and continue on from there.

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Figure 3.12 State diagram of synchronous 4bit up counter
Figure 3.13 Synchronous 4-Bit Up Counter
Although a state diagram is very easy to understand, in order to use the state
diagram to build a circuit, it needs to transform the diagram into a table because it is
easier to write the Boolean expressions from a table description of the problem.
Truth table:
Table 3.7-Truth table of Synchronous 4-Bit Up Counter

NEXT STATE
Present State
E=0 E=1
0000 0000 0001
0001 0001 0010
0010 0010 0011
0011 0011 0100
0100 0100 0101
0101 0101 0110
0110 0110 0111

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0111 0111 1000

1000 1000 1001
1001 1001 1010
1010 1010 1011
1011 1011 1100
1100 1100 1101
1101 1101 1110
1110 1110 1111
1111 1111 0000

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Table 3.7 shows the state transition table. Notice that when E = 0, the circuit will
not change state; only when E = 1 does the counting continue. The control logic of the
counter is as follows: The XOR gate complements each bit. The AND chain causes
complement of a bit if all the bits toward LSB from it equal 1.The Count Enable forces
all outputs of AND chain to 0 to “hold” the state.
Model Waveforms:
Figure3.14: Transient response of counter with CE=1, clr=0
Figure3.15:Transient response of counter with CE=1, clr=1

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Figure 3.16 Transient response of counter with CE=0, clr=0
3.4 Synchronous 8-bit up counter :

The synchronous 8-bit up counter has 7 AND gates, 8 XOR gates and 8 master-
slave D flip-flops. Same clock pulse is given to each flip-flop. So with every clock pulse
the counter counts one step up. It is an up counter and starts from 00000000. Then with
clock pulse counts like 00000001, 00000010, 00000011,00000100 up to 11111111. Then
it starts from 00000000 again. Q0 is the LSB and Q7 is the MSB. The master-slave D
flip-flop actually works at the falling edge of the clock. But because it is a master slave
configuration , it actually stores the input at rising edge and it is given to the output at the
falling edge of the clock. So change in counter output is observed in the falling edge of
the clock. There are 2 additional inputs in the counter, count enable (CE) and clear (clr).
1. Count Enable (CE) input: If CE=0, then counter stops counting. IF CE=1, each clock
pulse results in a counting action
2. Clear (clr) input: If clr=1, then the counter output clears to 0000. If clr=0, each clock
pulse results in a counting action.

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The control logic of the counter is as follows: The XOR gate complements each bit. The
AND chain causes complement of a bit if all the bits toward LSB from it equal 1.The
Count Enable forces all outputs of AND chain to 0 to “hold” the state.
Figure 3.17 Synchronous 8-Bit Up Counter
3.5 Layouts:
Integrated circuit layout, also known IC layout, IC mask layout, or mask design,
is the representation of an integrated circuit in terms of planar geometric shapes which
correspond to the patterns of metal, oxide, or semiconductor layers that make up the
components of the integrated circuit.
3.5.1Stick Diagrams :
● VLSI design aims to translate circuit concepts onto silicon

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● stick diagrams are a means of capturing topography and layer information -

simple diagrams
● Stick diagrams convey layer information through colour codes (or monochrome
encoding)
STICK DIAGRAMS:
Table 3.8-Colour encoding for stick diagrams
In VLSI design, as processes become more and more complex, need for the
designer to understand the intricacies of the fabrication process and interpret the relations
between the different photo masks is really trouble some. Therefore, a set of layout rules,
also called design rules, has been defined. They act as an interface or communication link
between the circuit designer and the process engineer during the manufacturing phase.
The objective associated with layout rules is to obtain a circuit with optimum yield

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(functional circuits versus non-functional circuits) in as small as area possible without

compromising reliability of the circuit. In addition, Design rules can be conservative or
aggressive, depending on whether yield or performance is desired. Generally, they are a
compromise between the two. Manufacturing processes have their inherent limitations in
accuracy. So the need of design rules arises due to manufacturing problems like –
• Photo resist shrinkage, tearing.
• Variations in material deposition, temperature and oxide thickness.

• Impurities.
• Variations across a wafer.
These lead to various problems like :
• Transistor problems: Variations in threshold voltage: This may occur due to
variations in oxide thickness, ion-implantation and poly layer. Changes in source/drain
diffusion overlap. Variations in substrate.
• Wiring problems: Diffusion: There is variation in doping which results in variations

in resistance, capacitance. Poly, metal: Variations in height, width resulting in variations
in resistance, capacitance. Shorts and opens.
• Oxide problems: Variations in height. Lack of planarity.
• Via problems: Via may not be cut all the way through. Undersize via has too much
resistance. Via may be too large and create short. To reduce these problems, the design
rules specify to the designer certain geometric constraints on the layout artwork so that
the patterns on the processed wafers will preserve the topology and geometry of the
designs. This consists of minimum-width and minimum-spacing constraints and
requirements between objects on the same or different layers. Apart from following a
definite set of rules, design rules also come by experience.
3.5.2Types of Design Rules:

The design rules primary address two issues:

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1. The geometrical reproduction of features that can be reproduced by the maskmaking

and lithographical process ,and
2. The interaction between different layers. There are primarily two approaches in
describing the design rules.
a. Linear scaling is possible only over a limited range of dimensions.

b. Scalable design rules are conservative .This results in over dimensioned and less
dense design.
c. This rule is not used in real life.
1. Scalable Design Rules (e.g. SCMOS, λ-based design rules): In this approach, all
rules are defined in terms of a single parameter λ. The rules are so chosen that a design
can be easily ported over a cross section of industrial process ,making the layout
portable .Scaling can be easily done by simply changing the value of. The key
disadvantages of this approach are:
2. Absolute Design Rules (e.g. μ-based design rules ) : In this approach, the design
rules are expressed in absolute dimensions (e.g. 0.75μm) and therefore can exploit the
features of a given process to a maximum degree. Here, scaling and porting is more
demanding, and has to be performed either manually or using CAD tools .Also, these
rules tend to be more complex especially for deep submicron. The fundamental unity in
the definition of a set of design rules is the minimum line width .It stands for the
minimum mask dimension that can be safely transferred to the semiconductor
material .Even for the same minimum dimension, design rules tend to differ from
company to company, and from process to process. Now, CAD tools allow designs to
migrate between compatible processes

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CHAPTER-4
SOFTWARE TOOLS
4.1Design tools
Microwind is a tool for designing and simulating circuits at layout level. The tool
features full editing facilities (copy, cut, past, duplicate, move), various views (MOS
characteristics, 2D cross section, 3D process viewer), and an analog simulator. DSCH is
software for logic design. Based on primitives, a hierarchical circuit can be built and
simulated. It also includes delay and power consumption evaluation. Silicon is for 3D
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display of the atomic structure of silicon, with emphasis on the silicon lattice, the
dopants, and the silicon dioxide.
4.2 Tools from microwind

● Microwind
MICROWIND is truly integrated EDA software encompassing IC designs from
concept to completion, enabling chip designers to design beyond their imagination.
MICROWIND integrates traditionally separated front-end and back-end chip design into
an integrated flow, accelerating the design cycle and reduced design complexities. It
tightly integrates mixed-signal implementation with digital implementation, circuit
simulation, transistor-level extraction and verification providing an innovative education
initiative to help individuals to develop the skills needed for design positions in virtually
every domain of IC industry.
● DSCH (Schematic Editor and Digital Simulator)

The DSCH program is a logic editor and simulator. DSCH is used to validate the
architecture of the logic circuit before the microelectronics design is started. DSCH
provides a user-friendly environment for hierarchical logic design, and fast simulation
with delay analysis, which allows the design and validation of complex logic structures.
DSCH also features the symbols, models and assembly support for 8051 and
16F84 controllers. Designers can create logic circuits for interfacing with these
controllers and verify software programs using DSCH.
It have some important points are,
● User-friendly environment for rapid design of logic circuits.

● Supports hierarchical logic design.
● Handles both conventional pattern-based logic simulation and intuitive on screen
mouse-driven simulation.

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● Improved built-in extractor which generates a SPICE netlist from the schematic
diagram (Compatible with PSPICETM and WinSpiceTM).
● Generates a VERILOG description of the schematic for layout conversion.
● Immediate access to symbol properties (Delay, fanout).
● Model and assembly support for 8051 and PIC 16F84 microcontrollers.
● Sub-micron, deep-submicron, nanoscale technology support.
● Supported by huge symbol library.
● Prothumb (Mix-signal Simulator)
No SPICE or external simulator is needed for verification of CMOS circuits.
Microwind program has in built analog like simulator which supports MOS Level 1,
Level 3 or BSIM4 model. With features like fast time-domain, voltage and current
estimation, very intuitive post processing, frequency estimation, delay estimation, makes
PROthumb a time saver. Even power estimation of circuit simulation can be checked on-
screen.
It have some important points are,
● Built-in SPICE-like analog simulator.

● Features fast time-domain, voltage and current estimation, with very intuitive post
processing: frequency estimation, delay estimation. (No external SPICE/ analog
Simulator required).
● Supports level1, level3 and BSIM4 models for all technologies from 1.2μm till 22
nm.
● MOS characteristic viewer with access to parameters of main model.
● Time-domain voltage and current waveforms available at the press of one single
button.
● DC/AC characteristics, signal frequency vs. time, eye diagrams Min/Typ/Max
analog simulation.
● Eye diagram view for signal output.
● On screen power estimation.
● Onscreen storage of waveforms for result hold-on.
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● Forward & backward buttons to move in simulation results.
● Nanolambda (Precision CMOS Layout Editor)

MICROWIND possess a precision CMOS layout editor, which supports
technologies right from 1.2um till 22 nm with unsurpassed illustration capabilities. With
its enhanced editing commands and layout control your development times would be
shorter than you ever imagined. Some important points are,
● Huge technology support till 22 nanometers

● Design-error-free cell library (Contacts, vias, MOS devices, etc.).
● Powerful automatic compiler from Verilog structure circuit into layout.
● On-line design rule checker with large rule base.
● Protutor ( MOS Characteristics tutor)
Valuable screen to understand the MOS characteristics, with a user interface that
designers will like.Some Points are,
● Change the model parameters and see their effects on Id/Vd, Id/Vg, Id(log)/Vg,
threshold vs Length.
● You can also fit the simulations with measurements that made in test chips
fabricated in 0.35, 0.25, 0.18, 0.9µm.
● Full length tutorial on MOS models is provided in manual, with details on all
parameters.
● Documentation includes several aspects of MOS modeling.
● MEMSim (Floating Gate Memory Simulator)
The double-gate MOS has been introduced in MICROWIND for the simulation of
non-volatile memories such as EPROM, EEPROM and FLASH. The command "UV
exposure" erases floating gates and removes all electrons. The programming is performed
by a very high voltage supply on the gate (7V in 0.12μm), a 1.2V voltage difference
between drain and source. Some electrons are sufficiently accelerated to pass through the
gate oxide by hot tunneling effect. Highlights are,

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● Simulation of non-volatile memories such as EPROM, EEPROM and FLASH

using double-gate MOS.
● Erasure of floating gates and removal all electrons.
● Programming can be performed by a very high voltage supply on the gate.
● VirtualFab (Cross sectional and 3D Viewer)

You will never teach deep-sub micron technology like before. As VirtualFab
offers you a facility to analyze and view cross sectional view of silicon layers and 3D
view of circuits. With MICROWIND v3.1 enables to draw real-time images of the layout
and navigate in full-3D on the surface or inside the IC. This command is based on
OpenGL and offers outstanding picture quality. The user can modify the viewing position
in X, Y, Z and play with light sources to create illustrative views of the layout. Some
points are,
● 3D fabrication process simulator with cross sectional viewer.

● Step-by-step 3-D visualization of fabrication for any portion of layout.
● See how the contacts and metallization are created.
● See the self-aligned diffusion after the polysilicon gate is fabricated.
● Check planes of VDD, VSS, and others signals.
4.3Microwind tool design flow:

Integrated circuits have changed the way of our life. You name one gadget and
will find the power of silicon which has made such complex electronic circuits possible.
Integrated circuits come in many different flavors these days.

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Figure 4.1 Microwind tool design flow
User designed chips in particular , CPLDs and FPGAs have revolutionized the way of
system design. But ASIC remains in lead, due to their speed, power and performance
advantages. Every critical system design is flagged with ASICs. To learn the IC design
process, techniques & 'critical' requirement handling, engineers practice for hours and
hours.on EDA tools to master know-how of design fundamentals.
Modern ASIC design tools like DSCH and MICROWIND provides very easy to
go-through design flow for CMOS IC designs. It supports traditional schematic circuit
building methods, layout editing, various analysis & verification methods, and fab sign
off. But more than rights & lefts of IC design flow, it's the basic design methodology and
circuit building techniques which leads to success in fabrication. But many of times,
engineers face hurdles during simulation and failures in prototyping.
EDA tools like MICROWIND & DSCH, which offers a complete IC design
flow, which starts with schematic building of digital circuits and then converting into
verilog file for compilation in CMOS layout using MICROWIND layout compiler. Every
engineer needs to verify circuit before going for Fabrication. FPGAs are best available
platform for ASIC prototyping.
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A prototype is “A system model to test and develop the product before its final
implementation.”Field Programmable Gate Arrays (FPGA) are build around using Look-
Up Tables (LUTs) and switch matrix, and are rich in resources. Advantages like high gate
density, flexibility, moderate speed, etc. gives ideal platform to ASIC designers for
prototyping their designs before going for fabrication of ASIC.
MICROWIND supports entire front-end to back-end design flow .For front-end

designing, we have DSCH (digital schematic editor) which posses in-built pattern based
simulator for digital circuits. User can also build analog circuits and convert them into
SPICE files and use 3rd party simulators like WinSpice or PSPICE.
DSCH can convert the digital circuits into Verilog file which can be further
synthesized for FPGA/CPLD devices of any vendor. The same Verilog file can be
compiled for layout conversion in MICROWIND.
The back-end design of circuits is supported by MICROWIND. User can design

digital circuits and compile here using Verilog file. MICROWIND automatically
generates a error free CMOS layout. Although this place-route is not optimized enough as
we do not indulge in complex place & route algorithms.
User can also create CMOS layout of their own using compile one line Verilog
syntax or custom build the layouts by manual drawing.
The CMOS layouts can be verified using inbuilt mix-signal simulator and
analyzed further for DRC, cross talks, delays, 2D cross section, 3D view, etc.
4.4 Synchronous design techniques

Here are some global design guideline for successful implementation of digital circuits
for ASIC and FPGA platforms.
1. Use a single master clock and maintain synchronous flow of data.

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2. Use a single master set or reset. Preferably, use asynchronous resets because they work
independently from the clock. When an asynchronous reset establishes the initial state, it
puts the entire circuit into a known state and helps make logic simulation and
manufacturing test easier. Keep in mind that CMOS ASIC technology prefers active-low
asynchronous set or reset, but often FPGAs use active high.
3. Avoid race conditions on de-asserting concurrent set and preset signals. You cannot
predict in simulation how the flip-flop will behave when both set and reset are de-
asserted close in time.
4. Do not use delayed logic or monostable pulse generators, which relies on delays for its
operation (they are unpredictable in ASIC & FPGA). Instead use synchronous pulse
generators which have known timings and does not generates glitches.
5. Use clock-enabled flip-flops for clock division. In many FPGA implementations,
ripple clock dividers are popular. Not only can ripple clock dividers cause problems with
EDAtools, the generated clock will experience a phase delay.
6. Use clock-enabled flip-flops to avoid glitching state decoders. FPGAs are sometimes
tolerant when a state decoder goes through “11” while changing from “01” to “10.” To
ASICs, this causes implementation-dependent glitches. Using clock-enabled flip-flops
not only avoids glitches but also adds no additional clock delays.
7. Have resets and transition states for Finite State Machines. Although FSMs are usually
synchronous, they still can have issues during the conversion process. Make sure there
are no dead states because during power-up the FSM can enter an unused state. Make
sure reset is also available on your FSM to make life easier during simulation and test
vector generation.
8 .Avoid latches; use flip-flops instead. Latches cause complications with static timing
and timing-driven layout tools. Latches are difficult to analyze, and the gate savings
between a latch and a flop are less important with submicron technology.
4.5Three levels of design in microwind and dsch

• The specifications we are going to see may be different for different foundry and
technology.
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• Design Example (3 Levels): NOR Gate
– Logic Design
– Circuit Design
– Layout Design
Microwind / DSCH NOR Example: NOR Gate Logic
● Open the Schematic Editor in Microwind (DSCH3). Click on the transistor

symbol in the symbol Library on the right. Instantiate NMOS or PMOS transistors
from the symbol library and place them in the editor window.
● Instantiate 2 NMOS and 2 PMOS transistors.

● Connect the drains and sources of transistors.
● Connect Vdd and GND to the schematic.
● Connect input button and output LED.

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Figure 4.2 Schematic editor window
Now NOR schematic ready.
● Use your logic simulator to verify the functionality of your schematic.

● The next step is to simulate the circuit and check for functionality.
● Click on, Simulate -> Start simulation.
● This brings up a Simulation Control Window.
● Click on the input buttons to set them to 1 or 0. Red color in a switch indicates a
'1'. As shown,
Figure 4.3 Run simulation window
The simulation output can be observed as a waveform after the application of the
inputs as above.Click on the timing diagram icon in the icon menu to see the timing
diagram of the input and output waveforms.

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Figure 4.4 Timing diagram of input and output waveforms window
Simulate your system with your hand calculated transistor sizes.
● Click File -> Make Verilog File. The Verilog, Hierarchy and Netlist window
appears. This window shows the verilog representation of NOR gate.
● Click OK to save the Verilog as a .txt file.
Figure 4.5 Making verilog file
Microwind / DSCH NOR Example: Circuit Design

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● Open the layout editor window in Microwind. Click File -> Select Foundry and
select X.rul. This sets your layout designs in X technology.
After selecting the .txt file, a new window appears called Verilog file.Click on Size
on the right top menus. This shows up the NMOS and PMOS sizes. Set the sizes
according to choice.
● Click Compile and then Back to editor in the Verilog File Window. This creates a
layout in layout editor window using automatic layout generation procedure.
● Add a capacitance to the output of the design. The value of the capacitance depends
on your choice.
● Click on OK. The capacitance is shown on the left bottom corner with a value of
0.015fF.

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Figure 4.6 Selecting foundary
Figure 4.7 Compilation window
● Click Simulate -> Run simulation. A simulation window appears with inputs and
output, shows the tphl, tplh and tp of the circuit. The power consumption is also
shown on the right bottom portion of the window.
Figure 4.8 Layout editor window

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Figure 4.9 Output waveforms
● If you are unable to meet the specifications of the circuit change the transistor
sizes. Generate the layout again and run the simulations till you achieve your
target delays.
Depending on the input sequences assigned at the input the output is observed in the
simulation. The power value is also given.

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CHAPTER-5
RESULTS
1.INVERTER:
Figure 5.1 gives the schematic of the CMOS inverter circuit. It can be seen that
the gates are at the same bias Vin which means that they are always in a complementary
state. When Vin is high, Vin~Vdd, the voltage between gate and substrate of the nMOS
transistor is also approximately Vdd and the transistor is in on-state. The gate-substrate
bias at the pMOS on the other side is nearly zero and the transistor is turned off. The
output voltage Vout is pulled to ground, which is the low state. When the input voltage is
in a high-state, the complementary situation occurs and the pMOSFET is turned on while
the nMOSFET is turned off. The output voltage is therefore pulled to Vdd which is the
high-state. It is important to note that in both states, high and low, no static current flows
through the inverter. This is of course only valid when assuming ideal devices with zero
off- and leakage-currents.

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Figure 5.1: Schematic of Inverter
TIMING DIAGRAM:
In the below output waveform, a voltage representing the opposite logic-level to its
input. If the applied input is low then the output becomes high and vice versa. If the input
is low (0 V) corresponding PMOS will be shorted and NMOS will opened then out1 is
shorted to Vdd which provides high output

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Figure 5.2 Input and output waveforms of inverter
LAYOUT:
Figure: 5.3 Layout for inverter
2.NAND GATE:
In digital electronics, a NAND gate (negative-AND) is a logic gate which

produces an output which is false only if all its inputs are true; thus its output
is complement to that of the AND gate. A LOW (0) output results only if both the inputs
to the gate are HIGH (1); if one or both inputs are LOW (0), a HIGH (1) output results. It
is made using transistors and junction diodes.
The NAND gate is significant because any boolean function can be implemented

by using a combination of NAND gates. This property is called functional completeness.
It shares this property with the NOR gate.
Digital systems employing certain logic circuits take advantage of NAND's

functional completeness. The NAND gate has the property of functional completeness.
That is, any other logic function (AND, OR, etc.) can be implemented using only NAND
gates.

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An entire processor can be created using NAND gates alone. In TTL ICs using
multiple-emitter transistors, it also requires fewer transistors than a NOR gate.
Figure 5.4 Schematic of NAND Gate
TIMING DIAGRAM:
In the below output waveform in1 and in2 are high i.e. at 5V then the two
PMOS will be open circuited and two NMOS will be Short circuited.
The output will be shorted to ground and produces zero output. If any of the input is low
(0 V) corresponding PMOS will be shorted and NMOS will opened then out1 is shorted
to Vdd which provides high output.
Figure 5.5 Input and output waveforms of NAND Gate

LAYOUT:

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Figure:5.6 Layout for NAND gate
3.MASTER SLAVE D FLIP-FLOP:
Figure 5.7 Schematic of master slave D flip-flop
TIMING DIAGRAM:

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When the clock is high, the D input is stored in the first latch, but the second latch cannot
change state. When the clock is low, the first latch's output is stored in the second latch,
but the first latch cannot change state. The result is that output can only change state
when the clock makes a transition from high to low.
Figure 5.8 Input and output waveforms of master slave D flip-flop
LAYOUT:

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Figure:5.9 Layout for master slave dff
4.MASTER SLAVE D FLIP-FLOP WITH CLR INPUT:
Figure 5.10 schematic of master slave D flip-flop with clear input
TIMING DIAGRAM:
Figure 5.11 Input and output waveforms of master slave D flip-flop with clear
input
LAYOUT:
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Figure:5.12 Layout for master slave dff with clear input
5.AND GATE:
Figure 5.13 Schematic of AND Gate
TIMING DIAGRAM:
In the below output waveform when in1 and in2 are high i.e. at 5V then the two PMOS
will be open circuited and two NMOS will be short circuited.The output out1 will be

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shorted to vdd and produces one as output. If any of the input is low (0 V) corresponding
PMOS will be open and NMOS will shorted the out1 is open to Vdd which provides low
output.
Figure 5.14 Input and output waveforms of AND Gate
LAYOUT:
Figure 5.15 Layout for AND gate
6. EXCLUSIVE OR GATE:

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Figure 5.16 Schematic of EX-OR Gate
TIMING DIAGRAM:
In the below output waveform of an Exclusive-OR gate ONLY goes “HIGH” when both
of its two input terminals are at “DIFFERENT” logic levels with respect to each other. If
these two inputs, in1 and in2 are both at logic level “1” or both at logic level “0” the out1
is a “0”
Figure 5.17 Input and output waveforms of EX-OR Gate
LAYOUT:

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Figure 5.18 Layout for EX-OR Gate
7.4-BIT SYNCHRONOUS COUNTER:
Figure 5.19 Schematic of 4-bit synchronous counter

TIMING DIAGRAM:
1. Count Enable (CE) input: If CE=0, then counter stops counting. IF CE=1, each
clock pulse results in a counting action
2. Clr: If clr=0, then counter stops counting. IF clr=1, each clock pulse results in a
counting action.

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In the below output waveform Q3 and Q0 are MSB and LSB bits.
Figure 5.20 Input and output waveforms of 4-bit synchronous counter
LAYOUT:
The results obtained for 4-bit synchronous up counter are
● Power : 30.398µW
● Area:1540.1µm2
Figure 5.21 Layout for 4-bit synchronous up counter

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8.8-BIT SYNCH RONOUS COUNTER:
Synchronous 8-bit up counter has 7 AND gates, 8 XOR gates and 8 master-slave
D flip-flops. Same clock pulse is given to each flip-flop. So with every clock pulse the
counter counts one step up. It is an up counter and starts from 00000000. Then with clock
pulse counts like 00000001, 00000010, 00000011,00000100 up to 11111111. Then it
starts from 00000000 again. Q0 is the LSB and Q7 is the MSB.
The master-slave D flip-flop actually works at the falling edge of the clock. But because
it is a master slave configuration , it actually stores the input at rising edge and it is given
to the output at the falling edge of the clock. So change in counter output is observed in
the falling edge of the clock.

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Figure 5.22 Schematic of 8-bit synchronous counter
The control logic of the counter is as follows: The XOR gate complements each
bit. The AND chain causes complement of a bit if all the bits toward LSB from it equal
1.The Count Enable forces all outputs of AND chain to 0 to “hold” the state.
TIMING DIAGRAM:
1. Count Enable (CE) input: If CE=0, then counter stops counting. IF CE=1, each
clock pulse results in a counting action.
2. Clr: If clr=0, then counter stops counting. IF clr=1, each clock pulse results in a
counting action.
In the output waveform Q7 and Q0 are MSB and LSB bits.
Figure 5.23 Input and output waveforms of 8-bit synchronous counter

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LAYOUT:
The results obtained for 8-bit synchronous up counter are
● Power : 67.956µW
● Area: 4148.9µm2
Figure 5.24 Layout for 8-bit synchronous up counter

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CHAPTER-6
CONCLUSION & FUTURE WORK
Hence the power reduction can be observed in this counter and also comparing it
with CMOS technology. Hence the performance of the different components of counter
are assessed in terms of power, and also area is also estimated for different components
The synchronous up counter has been implemented, simulated and analyzed. The
performance of the counter is assessed in terms of area and power consumption.
The logic and characteristics of the master-slave D flip-flop and synchronous 8-

bit up counter are easily verified with the simulation results. Thus synchronous 8-bit up
counter is design and implemented.
Power consumptions in both technologies:
Table 6.1-Comparision power results of 4-bit synchronous up counter
Circuit 180nm technology 120nm technology
4 bit synchronous 90.97µW 30.398µW

up counter

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Implementation of 8 bit synchronous up counter:
Table 6.2-Analysis of 8 bit synchronous up counter in 120nm technology
CIRCUTS POWER AREA
Synchronous 4 bit 30.398µW 1540.1µm2

up Counter
Synchronous 8 bit 67.956µW 4148.9µm2

up counter
As the technology is increasing the size of the components is decreasing. So in the

future, the size of vlsi components have been further reduced so that the area is reduced
as well as power and the cost is reduced.
The main purpose of the counter is to count the number of times a particular event
has been occurred but its applications are very wide.
This counter adds special features for the electronic devices like micro oven to
automatically off after certain time and washing machine to automatic. Like this the
applications are very wide with this counters and in the future there will be many more
special features like automatic lights on after 6 o clock and lights off after 10 o clock.
Like this many applications can be designed in future.
CHAPTER-7

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REFERENCES
[1]. Donald D. Givone, “Digital principles and Design”, TataMC Grawhill 1st edition.
[2]. D. Prasanna Kumari, R. Surya Prakasha Rao, B. Vijaya Bhaskar,”A Future Technology For
Enhanced Operation In Flip-Flop Oriented Circuits”, International Journal of Engineering
Research and Applications, Vol. 2, Issue4, July-August 2012, pp.2177-2180.
[3]. H. Mahmoodi, V. Tirumalashetty, M. Cooke, and K. Roy, “Ultra low power clocking
scheme using energy recovery and clock gating” IEEE Transactions on Very Large Scale
Integration (VLSI) System, Vol. 17, pp. 33-44, 2009.
[4]. John M. Yarbrough, “Digital logic- Applications and Design”.
[5]. M. Nogawa and Y. Ohtomo, “A data-transition look-ahead DFF circuit for statistical
reduction in power consumption” , IEEE Transactions on Solid-State Circuits, Vol. 33,
pp. 702-706, 1998.
[6]. Sung-Hyun YANG, Younggap YOU, Kyoung-Rok CHO, “A new Dynamic D-flip-flop
aiming at Glitch and Charge Sharing Free”, ICICE TRANS. ELECTRON., VOl.E86-C,
NO.3 MARCH 2003.
[7]. Upwinder Kaur, Rajesh Mehra, “Low Power CMOS Counter Using Clock Gated Flip-
Flop”,International Journal of Engineering and Advanced Technology (IJEAT) ISSN:
2249 – 8958, Volume-2, Issue-4, April 2013.
[8]. Synchronous counter", Digital, Play hookey.
[9]. Singh, Arun Kumar (2006). Digital Principles Foundation of Circuit Design and Application.
New Age Publishers.
[10].Horowitz, Paul; Hill, Winfield (1989). The Art of Electronics. Cambridge University
[11].Graf, Rudolf F (1999). Modern Dictionary of Electronics. Newnes. ISBN
[12]. S. Vinoth Kumar and M. Malathi, ―Low Power Synchronous Counter Using Improvised
Conditional Capture Flip-Flop‖, Second International Conference on Sustainable Energy
and Intelligent System (SEISCON),pp. 589-592 Dr. M.G.R. University, Chennai, Tamil
Nadu, India. July. 20-22, 2011.
[13]. N. H. E. Weste and D. Harris, ―CMOS VLSI Design‖, Reading, MA:Pearson Education,
Fourth Edition,,pp-379 & 13, 2005.

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[14]. A. Ramya, R. Arunya,p. Umaraniand V.Balaamuguran,―Design of Asynchronous up-

down, up-down Counter Using power efficient D-Flip Flop, International Journal For
Advance Research In Engineering And Technology,Vol. 1 ,Issue 9,pp. 59-63,2013.
[15]. M. R. Stan, A. F. Tenca, and M. D. Ercegovac, ―Long and fast up/down counters,‖ IEEE
Transaction. Computer, vol. 47, no. 7, pp. 722–735, Jul. 1998.

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DESIGN AND ANALYSIS OF SYNCHRONOUS 8 BIT UP COUNTER USING CMOS PROCESS

1.1 INTRODUCTION TO VLSI:

1.1.1 Historical Perspective:

Figure-1.1: overview of the prominent trends in information technologies

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Unit logic (one gate) 1960 1

Multi-function 1962 2–4

Complex function 1964 5 – 20

Medium Scale Integration 1967 20 - 200 (MSI)

Large Scale Integration 1972 200 – 2000 (LSI)

Very Large Scale Integration 1978 2000 – 20000 (VLSI)

Ultra Large Scale Integration 1989 20000 - ?(ULSI)

Table-1.1: Evolution of logic complexity in integrated circuits.

Here, the numbers for circuit complexity should be interpreted only as

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⮚ Less area/volume and therefore, compactness

Figure-1.2 : Evolution of integration density and minimum feature size, as

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When comparing the integration density of integrated circuits, a clear distinction

1.1.2 VLSI Design Flow

The design process, at various levels, is usually evolutionary in nature. It starts

The Y-chart consists of three major domains, namely:

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Figure-1.4: Typical VLSI design flow in three domains (Y-chart

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In the following, it will examine design methodologies and structured approaches

1.1.3 Design Hierarchy:

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1.1.4 VLSI Design Styles:

Several design styles can be considered for chip implementation of specified

Counting is a fundamental function of digital circuits. A digital counter consists

The different number of implementations of a counter is vast. With options such

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1.5 Design methodology:

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Figure1.5: Flow chart of design methodology

1.6 Organization of the project:

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2.2 Circuit design:

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DESCRIPTION ABOUT PROJECT

3.1 Implementation of synchronous 8 bit counter:

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Figure 3.1: Inverter

Table 3.1-Truth table of inverter

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Figure3.2:Timing diagram of inverter

3.1.2 NAND gate:

Figure 3.3: NAND gate

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Table 3.2-Truth table of NAND gate

Figure 3.4:Timing diagram of NAND Gate

3.1.3 AND gate:

Figure 3.5:AND gate

Table 3.3-Truth table of AND gate

Figure 3.6:Timing diagram of AND Gate

3.1.4 EX-OR gate:

Figure 3.7 Exclusive OR gate

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Table 3.4-Truth table of Exclusive OR gate

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